1
2
3
4
5
6
7
8
9
10
11
12#ifndef CNIC_H
13#define CNIC_H
14
15#define HC_INDEX_ISCSI_EQ_CONS 6
16
17#define HC_INDEX_FCOE_EQ_CONS 3
18
19#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
20#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
21
22#define KWQ_PAGE_CNT 4
23#define KCQ_PAGE_CNT 16
24
25#define KWQ_CID 24
26#define KCQ_CID 25
27
28
29
30
31#define L5_KRNLQ_FLAGS 0x00000000
32#define L5_KRNLQ_SIZE 0x00000000
33#define L5_KRNLQ_TYPE 0x00000000
34#define KRNLQ_FLAGS_PG_SZ (0xf<<0)
35#define KRNLQ_FLAGS_PG_SZ_256 (0<<0)
36#define KRNLQ_FLAGS_PG_SZ_512 (1<<0)
37#define KRNLQ_FLAGS_PG_SZ_1K (2<<0)
38#define KRNLQ_FLAGS_PG_SZ_2K (3<<0)
39#define KRNLQ_FLAGS_PG_SZ_4K (4<<0)
40#define KRNLQ_FLAGS_PG_SZ_8K (5<<0)
41#define KRNLQ_FLAGS_PG_SZ_16K (6<<0)
42#define KRNLQ_FLAGS_PG_SZ_32K (7<<0)
43#define KRNLQ_FLAGS_PG_SZ_64K (8<<0)
44#define KRNLQ_FLAGS_PG_SZ_128K (9<<0)
45#define KRNLQ_FLAGS_PG_SZ_256K (10<<0)
46#define KRNLQ_FLAGS_PG_SZ_512K (11<<0)
47#define KRNLQ_FLAGS_PG_SZ_1M (12<<0)
48#define KRNLQ_FLAGS_PG_SZ_2M (13<<0)
49#define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15)
50#define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16)
51#define KRNLQ_TYPE_TYPE (0xf<<28)
52#define KRNLQ_TYPE_TYPE_EMPTY (0<<28)
53#define KRNLQ_TYPE_TYPE_KRNLQ (6<<28)
54
55#define L5_KRNLQ_HOST_QIDX 0x00000004
56#define L5_KRNLQ_HOST_FW_QIDX 0x00000008
57#define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c
58#define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c
59#define L5_KRNLQ_NX_QE_HADDR_HI 0x00000010
60#define L5_KRNLQ_NX_QE_HADDR_LO 0x00000014
61#define L5_KRNLQ_PGTBL_PGIDX 0x00000018
62#define L5_KRNLQ_NX_PG_QIDX 0x00000018
63#define L5_KRNLQ_PGTBL_NPAGES 0x0000001c
64#define L5_KRNLQ_QIDX_INCR 0x0000001c
65#define L5_KRNLQ_PGTBL_HADDR_HI 0x00000020
66#define L5_KRNLQ_PGTBL_HADDR_LO 0x00000024
67
68#define BNX2_PG_CTX_MAP 0x1a0034
69#define BNX2_ISCSI_CTX_MAP 0x1a0074
70
71#define MAX_COMPLETED_KCQE 64
72
73#define MAX_CNIC_L5_CONTEXT 256
74
75#define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT
76
77#define MAX_ISCSI_TBL_SZ 256
78
79#define CNIC_LOCAL_PORT_MIN 60000
80#define CNIC_LOCAL_PORT_MAX 61024
81#define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
82
83#define KWQE_CNT (BCM_PAGE_SIZE / sizeof(struct kwqe))
84#define KCQE_CNT (BCM_PAGE_SIZE / sizeof(struct kcqe))
85#define MAX_KWQE_CNT (KWQE_CNT - 1)
86#define MAX_KCQE_CNT (KCQE_CNT - 1)
87
88#define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1)
89#define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1)
90
91#define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BCM_PAGE_BITS - 5))
92#define KWQ_IDX(x) ((x) & MAX_KWQE_CNT)
93
94#define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BCM_PAGE_BITS - 5))
95#define KCQ_IDX(x) ((x) & MAX_KCQE_CNT)
96
97#define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \
98 (MAX_KCQE_CNT - 1)) ? \
99 (x) + 2 : (x) + 1
100
101#define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp)
102#define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp)
103#define BNX2X_KWQ_DATA(cp, x) \
104 &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)]
105
106#define DEF_IPID_START 0x8000
107
108#define DEF_KA_TIMEOUT 10000
109#define DEF_KA_INTERVAL 300000
110#define DEF_KA_MAX_PROBE_COUNT 3
111#define DEF_TOS 0
112#define DEF_TTL 0xfe
113#define DEF_SND_SEQ_SCALE 0
114#define DEF_RCV_BUF 0xffff
115#define DEF_SND_BUF 0xffff
116#define DEF_SEED 0
117#define DEF_MAX_RT_TIME 500
118#define DEF_MAX_DA_COUNT 2
119#define DEF_SWS_TIMER 1000
120#define DEF_MAX_CWND 0xffff
121
122struct cnic_ctx {
123 u32 cid;
124 void *ctx;
125 dma_addr_t mapping;
126};
127
128#define BNX2_MAX_CID 0x2000
129
130struct cnic_dma {
131 int num_pages;
132 void **pg_arr;
133 dma_addr_t *pg_map_arr;
134 int pgtbl_size;
135 u32 *pgtbl;
136 dma_addr_t pgtbl_map;
137};
138
139struct cnic_id_tbl {
140 spinlock_t lock;
141 u32 start;
142 u32 max;
143 u32 next;
144 unsigned long *table;
145};
146
147#define CNIC_KWQ16_DATA_SIZE 128
148
149struct kwqe_16_data {
150 u8 data[CNIC_KWQ16_DATA_SIZE];
151};
152
153struct cnic_iscsi {
154 struct cnic_dma task_array_info;
155 struct cnic_dma r2tq_info;
156 struct cnic_dma hq_info;
157};
158
159struct cnic_context {
160 u32 cid;
161 struct kwqe_16_data *kwqe_data;
162 dma_addr_t kwqe_data_mapping;
163 wait_queue_head_t waitq;
164 int wait_cond;
165 unsigned long timestamp;
166 unsigned long ctx_flags;
167#define CTX_FL_OFFLD_START 0
168#define CTX_FL_DELETE_WAIT 1
169#define CTX_FL_CID_ERROR 2
170 u8 ulp_proto_id;
171 union {
172 struct cnic_iscsi *iscsi;
173 } proto;
174};
175
176struct kcq_info {
177 struct cnic_dma dma;
178 struct kcqe **kcq;
179
180 u16 *hw_prod_idx_ptr;
181 u16 sw_prod_idx;
182 u16 *status_idx_ptr;
183 u32 io_addr;
184
185 u16 (*next_idx)(u16);
186 u16 (*hw_idx)(u16);
187};
188
189struct iro {
190 u32 base;
191 u16 m1;
192 u16 m2;
193 u16 m3;
194 u16 size;
195};
196
197struct cnic_uio_dev {
198 struct uio_info cnic_uinfo;
199 u32 uio_dev;
200
201 int l2_ring_size;
202 void *l2_ring;
203 dma_addr_t l2_ring_map;
204
205 int l2_buf_size;
206 void *l2_buf;
207 dma_addr_t l2_buf_map;
208
209 struct cnic_dev *dev;
210 struct pci_dev *pdev;
211 struct list_head list;
212};
213
214struct cnic_local {
215
216 spinlock_t cnic_ulp_lock;
217 void *ulp_handle[MAX_CNIC_ULP_TYPE];
218 unsigned long ulp_flags[MAX_CNIC_ULP_TYPE];
219#define ULP_F_INIT 0
220#define ULP_F_START 1
221#define ULP_F_CALL_PENDING 2
222 struct cnic_ulp_ops __rcu *ulp_ops[MAX_CNIC_ULP_TYPE];
223
224 unsigned long cnic_local_flags;
225#define CNIC_LCL_FL_KWQ_INIT 0x0
226#define CNIC_LCL_FL_L2_WAIT 0x1
227#define CNIC_LCL_FL_RINGS_INITED 0x2
228#define CNIC_LCL_FL_STOP_ISCSI 0x4
229
230 struct cnic_dev *dev;
231
232 struct cnic_eth_dev *ethdev;
233
234 struct cnic_uio_dev *udev;
235
236 int l2_rx_ring_size;
237 int l2_single_buf_size;
238
239 u16 *rx_cons_ptr;
240 u16 *tx_cons_ptr;
241 u16 rx_cons;
242 u16 tx_cons;
243
244 const struct iro *iro_arr;
245#define IRO (((struct cnic_local *) dev->cnic_priv)->iro_arr)
246
247 struct cnic_dma kwq_info;
248 struct kwqe **kwq;
249
250 struct cnic_dma kwq_16_data_info;
251
252 u16 max_kwq_idx;
253
254 u16 kwq_prod_idx;
255 u32 kwq_io_addr;
256
257 u16 *kwq_con_idx_ptr;
258 u16 kwq_con_idx;
259
260 struct kcq_info kcq1;
261 struct kcq_info kcq2;
262
263 union {
264 void *gen;
265 struct status_block_msix *bnx2;
266 struct host_hc_status_block_e1x *bnx2x_e1x;
267
268 #define SM_RX_ID 0
269 #define SM_TX_ID 1
270 } status_blk;
271
272 struct host_sp_status_block *bnx2x_def_status_blk;
273
274 u32 status_blk_num;
275 u32 bnx2x_igu_sb_id;
276 u32 int_num;
277 u32 last_status_idx;
278 struct tasklet_struct cnic_irq_task;
279
280 struct kcqe *completed_kcq[MAX_COMPLETED_KCQE];
281
282 struct cnic_sock *csk_tbl;
283 struct cnic_id_tbl csk_port_tbl;
284
285 struct cnic_dma gbl_buf_info;
286
287 struct cnic_iscsi *iscsi_tbl;
288 struct cnic_context *ctx_tbl;
289 struct cnic_id_tbl cid_tbl;
290 atomic_t iscsi_conn;
291 u32 iscsi_start_cid;
292
293 u32 fcoe_init_cid;
294 u32 fcoe_start_cid;
295 struct cnic_id_tbl fcoe_cid_tbl;
296
297 u32 max_cid_space;
298
299
300 int num_iscsi_tasks;
301 int num_ccells;
302 int task_array_size;
303 int r2tq_size;
304 int hq_size;
305 int num_cqs;
306
307 struct delayed_work delete_task;
308
309 struct cnic_ctx *ctx_arr;
310 int ctx_blks;
311 int ctx_blk_size;
312 unsigned long ctx_align;
313 int cids_per_blk;
314
315 u32 chip_id;
316 int func;
317 u32 pfid;
318 u8 port_mode;
319#define CHIP_4_PORT_MODE 0
320#define CHIP_2_PORT_MODE 1
321#define CHIP_PORT_MODE_NONE 2
322
323 u32 shmem_base;
324
325 struct cnic_ops *cnic_ops;
326 int (*start_hw)(struct cnic_dev *);
327 void (*stop_hw)(struct cnic_dev *);
328 void (*setup_pgtbl)(struct cnic_dev *,
329 struct cnic_dma *);
330 int (*alloc_resc)(struct cnic_dev *);
331 void (*free_resc)(struct cnic_dev *);
332 int (*start_cm)(struct cnic_dev *);
333 void (*stop_cm)(struct cnic_dev *);
334 void (*enable_int)(struct cnic_dev *);
335 void (*disable_int_sync)(struct cnic_dev *);
336 void (*ack_int)(struct cnic_dev *);
337 void (*close_conn)(struct cnic_sock *, u32 opcode);
338};
339
340struct bnx2x_bd_chain_next {
341 u32 addr_lo;
342 u32 addr_hi;
343 u8 reserved[8];
344};
345
346#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
347
348#define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN)
349#define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT)
350
351#define CDU_REGION_NUMBER_XCM_AG 2
352#define CDU_REGION_NUMBER_UCM_AG 4
353
354#define CDU_VALID_DATA(_cid, _region, _type) \
355 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
356
357#define CDU_CRC8(_cid, _region, _type) \
358 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
359
360#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
361 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
362
363#define BNX2X_CONTEXT_MEM_SIZE 1024
364#define BNX2X_FCOE_CID 16
365
366#define BNX2X_ISCSI_START_CID 18
367#define BNX2X_ISCSI_NUM_CONNECTIONS 128
368#define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128
369#define BNX2X_ISCSI_MAX_PENDING_R2TS 4
370#define BNX2X_ISCSI_R2TQE_SIZE 8
371#define BNX2X_ISCSI_HQ_BD_SIZE 64
372#define BNX2X_ISCSI_GLB_BUF_SIZE 64
373#define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
374#define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
375
376#define BNX2X_FCOE_NUM_CONNECTIONS 1024
377
378#define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ
379
380#define BNX2X_CHIP_NUM_57710 0x164e
381#define BNX2X_CHIP_NUM_57711 0x164f
382#define BNX2X_CHIP_NUM_57711E 0x1650
383#define BNX2X_CHIP_NUM_57712 0x1662
384#define BNX2X_CHIP_NUM_57712E 0x1663
385#define BNX2X_CHIP_NUM_57713 0x1651
386#define BNX2X_CHIP_NUM_57713E 0x1652
387#define BNX2X_CHIP_NUM_57800 0x168a
388#define BNX2X_CHIP_NUM_57810 0x168e
389#define BNX2X_CHIP_NUM_57840 0x168d
390
391#define BNX2X_CHIP_NUM(x) (x >> 16)
392#define BNX2X_CHIP_IS_57710(x) \
393 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57710)
394#define BNX2X_CHIP_IS_57711(x) \
395 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711)
396#define BNX2X_CHIP_IS_57711E(x) \
397 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57711E)
398#define BNX2X_CHIP_IS_E1H(x) \
399 (BNX2X_CHIP_IS_57711(x) || BNX2X_CHIP_IS_57711E(x))
400#define BNX2X_CHIP_IS_57712(x) \
401 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712)
402#define BNX2X_CHIP_IS_57712E(x) \
403 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57712E)
404#define BNX2X_CHIP_IS_57713(x) \
405 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713)
406#define BNX2X_CHIP_IS_57713E(x) \
407 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57713E)
408#define BNX2X_CHIP_IS_57800(x) \
409 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57800)
410#define BNX2X_CHIP_IS_57810(x) \
411 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57810)
412#define BNX2X_CHIP_IS_57840(x) \
413 (BNX2X_CHIP_NUM(x) == BNX2X_CHIP_NUM_57840)
414#define BNX2X_CHIP_IS_E2(x) \
415 (BNX2X_CHIP_IS_57712(x) || BNX2X_CHIP_IS_57712E(x) || \
416 BNX2X_CHIP_IS_57713(x) || BNX2X_CHIP_IS_57713E(x))
417#define BNX2X_CHIP_IS_E3(x) \
418 (BNX2X_CHIP_IS_57800(x) || BNX2X_CHIP_IS_57810(x) || \
419 BNX2X_CHIP_IS_57840(x))
420#define BNX2X_CHIP_IS_E2_PLUS(x) (BNX2X_CHIP_IS_E2(x) || BNX2X_CHIP_IS_E3(x))
421
422#define IS_E1H_OFFSET BNX2X_CHIP_IS_E1H(cp->chip_id)
423
424#define BNX2X_RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
425#define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2)
426#define BNX2X_RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
427#define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1)
428
429#define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \
430 (BNX2X_MAX_RCQ_DESC_CNT - 1)) ? \
431 ((x) + 2) : ((x) + 1)
432
433#define BNX2X_DEF_SB_ID HC_SP_SB_ID
434
435#define BNX2X_SHMEM_MF_BLK_OFFSET 0x7e4
436
437#define BNX2X_SHMEM_ADDR(base, field) (base + \
438 offsetof(struct shmem_region, field))
439
440#define BNX2X_SHMEM2_ADDR(base, field) (base + \
441 offsetof(struct shmem2_region, field))
442
443#define BNX2X_SHMEM2_HAS(base, field) \
444 ((base) && \
445 (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
446 offsetof(struct shmem2_region, field)))
447
448#define BNX2X_MF_CFG_ADDR(base, field) \
449 ((base) + offsetof(struct mf_cfg, field))
450
451#ifndef ETH_MAX_RX_CLIENTS_E2
452#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
453#endif
454
455#define CNIC_PORT(cp) ((cp)->pfid & 1)
456#define CNIC_FUNC(cp) ((cp)->func)
457#define CNIC_PATH(cp) (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ? \
458 0 : (CNIC_FUNC(cp) & 1))
459#define CNIC_E1HVN(cp) ((cp)->pfid >> 1)
460
461#define BNX2X_HW_CID(cp, x) ((CNIC_PORT(cp) << 23) | \
462 (CNIC_E1HVN(cp) << 17) | (x))
463
464#define BNX2X_SW_CID(x) (x & 0x1ffff)
465
466#define BNX2X_CL_QZONE_ID(cp, cli) \
467 (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ? cli : \
468 cli + (CNIC_PORT(cp) * ETH_MAX_RX_CLIENTS_E1H))
469
470#ifndef MAX_STAT_COUNTER_ID
471#define MAX_STAT_COUNTER_ID \
472 (BNX2X_CHIP_IS_E1H((cp)->chip_id) ? MAX_STAT_COUNTER_ID_E1H : \
473 ((BNX2X_CHIP_IS_E2_PLUS((cp)->chip_id)) ? MAX_STAT_COUNTER_ID_E2 :\
474 MAX_STAT_COUNTER_ID_E1))
475#endif
476
477#define CNIC_RAMROD_TMO (HZ / 4)
478
479#endif
480
481
