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15#ifndef _HWM_
16#define _HWM_
17
18#include "mbuf.h"
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33#ifndef DRV_BUF_FLUSH
34#define DRV_BUF_FLUSH(desc,flag)
35#define DDI_DMA_SYNC_FORCPU
36#define DDI_DMA_SYNC_FORDEV
37#endif
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42#define RX_ENABLE_PASS_SMT 21
43#define RX_DISABLE_PASS_SMT 22
44#define RX_ENABLE_PASS_NSA 23
45#define RX_DISABLE_PASS_NSA 24
46#define RX_ENABLE_PASS_DB 25
47#define RX_DISABLE_PASS_DB 26
48#define RX_DISABLE_PASS_ALL 27
49#define RX_DISABLE_LLC_PROMISC 28
50#define RX_ENABLE_LLC_PROMISC 29
51
52
53#ifndef DMA_RD
54#define DMA_RD 1
55#endif
56#ifndef DMA_WR
57#define DMA_WR 2
58#endif
59#define SMT_BUF 0x80
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64#define EN_IRQ_EOF 0x02
65#define LOC_TX 0x04
66#define LAST_FRAG 0x08
67#define FIRST_FRAG 0x10
68#define LAN_TX 0x20
69#define RING_DOWN 0x40
70#define OUT_OF_TXD 0x80
71
72
73#ifndef NULL
74#define NULL 0
75#endif
76
77#ifdef LITTLE_ENDIAN
78#define HWM_REVERSE(x) (x)
79#else
80#define HWM_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
81 (((x)<< 8L)&0x00ff0000L) + \
82 (((x)>> 8L)&0x0000ff00L) + \
83 (((x)>>24L)&0x000000ffL))
84#endif
85
86#define C_INDIC (1L<<25)
87#define A_INDIC (1L<<26)
88#define RD_FS_LOCAL 0x80
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93#define DEBUG_SMTF 1
94#define DEBUG_SMT 2
95#define DEBUG_ECM 3
96#define DEBUG_RMT 4
97#define DEBUG_CFM 5
98#define DEBUG_PCM 6
99#define DEBUG_SBA 7
100#define DEBUG_ESS 8
101
102#define DB_HWM_RX 10
103#define DB_HWM_TX 11
104#define DB_HWM_GEN 12
105
106struct s_mbuf_pool {
107#ifndef MB_OUTSIDE_SMC
108 SMbuf mb[MAX_MBUF] ;
109#endif
110 SMbuf *mb_start ;
111 SMbuf *mb_free ;
112} ;
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114struct hwm_r {
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118 u_int len ;
119 char *mb_pos ;
120} ;
121
122struct hw_modul {
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126 struct s_mbuf_pool mbuf_pool ;
127 struct hwm_r r ;
128
129 union s_fp_descr volatile *descr_p ;
130
131 u_short pass_SMT ;
132 u_short pass_NSA ;
133 u_short pass_DB ;
134 u_short pass_llc_promisc ;
135
136 SMbuf *llc_rx_pipe ;
137 SMbuf *llc_rx_tail ;
138 int queued_rx_frames ;
139
140 SMbuf *txd_tx_pipe ;
141 SMbuf *txd_tx_tail ;
142 int queued_txd_mb ;
143
144 int rx_break ;
145 int leave_isr ;
146 int isr_flag ;
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150 struct s_smt_tx_queue *tx_p ;
151 u_long tx_descr ;
152 int tx_len ;
153 SMbuf *tx_mb ;
154 char *tx_data ;
155
156 int detec_count ;
157 u_long rx_len_error ;
158} ;
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164
165#ifdef DEBUG
166struct os_debug {
167 int hwm_rx ;
168 int hwm_tx ;
169 int hwm_gen ;
170} ;
171#endif
172
173#ifdef DEBUG
174#ifdef DEBUG_BRD
175#define DB_P smc->debug
176#else
177#define DB_P debug
178#endif
179
180#define DB_RX(a,b,c,lev) if (DB_P.d_os.hwm_rx >= (lev)) printf(a,b,c)
181#define DB_TX(a,b,c,lev) if (DB_P.d_os.hwm_tx >= (lev)) printf(a,b,c)
182#define DB_GEN(a,b,c,lev) if (DB_P.d_os.hwm_gen >= (lev)) printf(a,b,c)
183#else
184#define DB_RX(a,b,c,lev)
185#define DB_TX(a,b,c,lev)
186#define DB_GEN(a,b,c,lev)
187#endif
188
189#ifndef SK_BREAK
190#define SK_BREAK()
191#endif
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210#define HWM_GET_TX_PHYS(txd) (u_long)AIX_REVERSE((txd)->txd_tbadr)
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226#define HWM_GET_TX_LEN(txd) ((int)AIX_REVERSE((txd)->txd_tbctrl)& RD_LENGTH)
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243#define HWM_GET_TX_USED(smc,queue) (int) (smc)->hw.fp.tx_q[queue].tx_used
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261#define HWM_GET_CURR_TXD(smc,queue) (struct s_smt_fp_txd volatile *)\
262 (smc)->hw.fp.tx_q[queue].tx_curr_put
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278#define HWM_GET_RX_FRAG_LEN(rxd) ((int)AIX_REVERSE((rxd)->rxd_rbctrl)& \
279 RD_LENGTH)
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295#define HWM_GET_RX_PHYS(rxd) (u_long)AIX_REVERSE((rxd)->rxd_rbadr)
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312#define HWM_GET_RX_USED(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_used)
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326#define HWM_GET_RX_FREE(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_free-1)
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341#define HWM_GET_CURR_RXD(smc) (struct s_smt_fp_rxd volatile *)\
342 (smc)->hw.fp.rx_q[QUEUE_R1].rx_curr_put
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358#ifndef HWM_NO_FLOW_CTL
359#define HWM_RX_CHECK(smc,low_water) {\
360 if ((low_water) >= (smc)->hw.fp.rx_q[QUEUE_R1].rx_used) {\
361 mac_drv_fill_rxd(smc) ;\
362 }\
363}
364#else
365#define HWM_RX_CHECK(smc,low_water) mac_drv_fill_rxd(smc)
366#endif
367
368#ifndef HWM_EBASE
369#define HWM_EBASE 500
370#endif
371
372#define HWM_E0001 HWM_EBASE + 1
373#define HWM_E0001_MSG "HWM: Wrong size of s_rxd_os struct"
374#define HWM_E0002 HWM_EBASE + 2
375#define HWM_E0002_MSG "HWM: Wrong size of s_txd_os struct"
376#define HWM_E0003 HWM_EBASE + 3
377#define HWM_E0003_MSG "HWM: smt_free_mbuf() called with NULL pointer"
378#define HWM_E0004 HWM_EBASE + 4
379#define HWM_E0004_MSG "HWM: Parity error rx queue 1"
380#define HWM_E0005 HWM_EBASE + 5
381#define HWM_E0005_MSG "HWM: Encoding error rx queue 1"
382#define HWM_E0006 HWM_EBASE + 6
383#define HWM_E0006_MSG "HWM: Encoding error async tx queue"
384#define HWM_E0007 HWM_EBASE + 7
385#define HWM_E0007_MSG "HWM: Encoding error sync tx queue"
386#define HWM_E0008 HWM_EBASE + 8
387#define HWM_E0008_MSG ""
388#define HWM_E0009 HWM_EBASE + 9
389#define HWM_E0009_MSG "HWM: Out of RxD condition detected"
390#define HWM_E0010 HWM_EBASE + 10
391#define HWM_E0010_MSG "HWM: A protocol layer has tried to send a frame with an invalid frame control"
392#define HWM_E0011 HWM_EBASE + 11
393#define HWM_E0011_MSG "HWM: mac_drv_clear_tx_queue was called although the hardware wasn't stopped"
394#define HWM_E0012 HWM_EBASE + 12
395#define HWM_E0012_MSG "HWM: mac_drv_clear_rx_queue was called although the hardware wasn't stopped"
396#define HWM_E0013 HWM_EBASE + 13
397#define HWM_E0013_MSG "HWM: mac_drv_repair_descr was called although the hardware wasn't stopped"
398
399#endif
400