LXR linux/drivers/scsi/mpt2sas/mpi/mpi2

   1/*
   2 *  Copyright (c) 2000-2011 LSI Corporation.
   3 *
   4 *
   5 *           Name:  mpi2_cnfg.h
   6 *          Title:  MPI Configuration messages and pages
   7 *  Creation Date:  November 10, 2006
   8 *
   9 *    mpi2_cnfg.h Version:  02.00.21
  10 *
  11 *  Version History
  12 *  ---------------
  13 *
  14 *  Date      Version   Description
  15 *  --------  --------  ------------------------------------------------------
  16 *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  17 *  06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
  18 *                      Added Manufacturing Page 11.
  19 *                      Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
  20 *                      define.
  21 *  06-26-07  02.00.02  Adding generic structure for product-specific
  22 *                      Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
  23 *                      Rework of BIOS Page 2 configuration page.
  24 *                      Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
  25 *                      forms.
  26 *                      Added configuration pages IOC Page 8 and Driver
  27 *                      Persistent Mapping Page 0.
  28 *  08-31-07  02.00.03  Modified configuration pages dealing with Integrated
  29 *                      RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
  30 *                      RAID Physical Disk Pages 0 and 1, RAID Configuration
  31 *                      Page 0).
  32 *                      Added new value for AccessStatus field of SAS Device
  33 *                      Page 0 (_SATA_NEEDS_INITIALIZATION).
  34 *  10-31-07  02.00.04  Added missing SEPDevHandle field to
  35 *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
  36 *  12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
  37 *                      NVDATA.
  38 *                      Modified IOC Page 7 to use masks and added field for
  39 *                      SASBroadcastPrimitiveMasks.
  40 *                      Added MPI2_CONFIG_PAGE_BIOS_4.
  41 *                      Added MPI2_CONFIG_PAGE_LOG_0.
  42 *  02-29-08  02.00.06  Modified various names to make them 32-character unique.
  43 *                      Added SAS Device IDs.
  44 *                      Updated Integrated RAID configuration pages including
  45 *                      Manufacturing Page 4, IOC Page 6, and RAID Configuration
  46 *                      Page 0.
  47 *  05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
  48 *                      Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
  49 *                      Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
  50 *                      Added missing MaxNumRoutedSasAddresses field to
  51 *                      MPI2_CONFIG_PAGE_EXPANDER_0.
  52 *                      Added SAS Port Page 0.
  53 *                      Modified structure layout for
  54 *                      MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
  55 *  06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
  56 *                      MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
  57 *  10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
  58 *                      to 0x000000FF.
  59 *                      Added two new values for the Physical Disk Coercion Size
  60 *                      bits in the Flags field of Manufacturing Page 4.
  61 *                      Added product-specific Manufacturing pages 16 to 31.
  62 *                      Modified Flags bits for controlling write cache on SATA
  63 *                      drives in IO Unit Page 1.
  64 *                      Added new bit to AdditionalControlFlags of SAS IO Unit
  65 *                      Page 1 to control Invalid Topology Correction.
  66 *                      Added additional defines for RAID Volume Page 0
  67 *                      VolumeStatusFlags field.
  68 *                      Modified meaning of RAID Volume Page 0 VolumeSettings
  69 *                      define for auto-configure of hot-swap drives.
  70 *                      Added SupportedPhysDisks field to RAID Volume Page 1 and
  71 *                      added related defines.
  72 *                      Added PhysDiskAttributes field (and related defines) to
  73 *                      RAID Physical Disk Page 0.
  74 *                      Added MPI2_SAS_PHYINFO_PHY_VACANT define.
  75 *                      Added three new DiscoveryStatus bits for SAS IO Unit
  76 *                      Page 0 and SAS Expander Page 0.
  77 *                      Removed multiplexing information from SAS IO Unit pages.
  78 *                      Added BootDeviceWaitTime field to SAS IO Unit Page 4.
  79 *                      Removed Zone Address Resolved bit from PhyInfo and from
  80 *                      Expander Page 0 Flags field.
  81 *                      Added two new AccessStatus values to SAS Device Page 0
  82 *                      for indicating routing problems. Added 3 reserved words
  83 *                      to this page.
  84 *  01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
  85 *                      Inserted missing reserved field into structure for IOC
  86 *                      Page 6.
  87 *                      Added more pending task bits to RAID Volume Page 0
  88 *                      VolumeStatusFlags defines.
  89 *                      Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
  90 *                      Added a new DiscoveryStatus bit for SAS IO Unit Page 0
  91 *                      and SAS Expander Page 0 to flag a downstream initiator
  92 *                      when in simplified routing mode.
  93 *                      Removed SATA Init Failure defines for DiscoveryStatus
  94 *                      fields of SAS IO Unit Page 0 and SAS Expander Page 0.
  95 *                      Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
  96 *                      Added PortGroups, DmaGroup, and ControlGroup fields to
  97 *                      SAS Device Page 0.
  98 *  05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
  99 *                      Unit Page 6.
 100 *                      Added expander reduced functionality data to SAS
 101 *                      Expander Page 0.
 102 *                      Added SAS PHY Page 2 and SAS PHY Page 3.
 103 *  07-30-09  02.00.12  Added IO Unit Page 7.
 104 *                      Added new device ids.
 105 *                      Added SAS IO Unit Page 5.
 106 *                      Added partial and slumber power management capable flags
 107 *                      to SAS Device Page 0 Flags field.
 108 *                      Added PhyInfo defines for power condition.
 109 *                      Added Ethernet configuration pages.
 110 *  10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
 111 *                      Added SAS PHY Page 4 structure and defines.
 112 *  02-10-10  02.00.14  Modified the comments for the configuration page
 113 *                      structures that contain an array of data. The host
 114 *                      should use the "count" field in the page data (e.g. the
 115 *                      NumPhys field) to determine the number of valid elements
 116 *                      in the array.
 117 *                      Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
 118 *                      Added PowerManagementCapabilities to IO Unit Page 7.
 119 *                      Added PortWidthModGroup field to
 120 *                      MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
 121 *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
 122 *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
 123 *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
 124 *  05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
 125 *                      define.
 126 *                      Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
 127 *                      Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
 128 *  08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
 129 *                      defines.
 130 *  11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
 131 *                      MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
 132 *                      the Pinout field.
 133 *                      Added BoardTemperature and BoardTemperatureUnits fields
 134 *                      to MPI2_CONFIG_PAGE_IO_UNIT_7.
 135 *                      Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
 136 *                      and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
 137 *  02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
 138 *                      Added IO Unit Page 8, IO Unit Page 9,
 139 *                      and IO Unit Page 10.
 140 *                      Added SASNotifyPrimitiveMasks field to
 141 *                      MPI2_CONFIG_PAGE_IOC_7.
 142 *  03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
 143 *  05-25-11  02.00.20  Cleaned up a few comments.
 144 *  08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
 145 *                      for PCIe link as obsolete.
 146 *                      Added SpinupFlags field containing a Disable Spin-up
 147 *                      bit to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of
 148 *                      SAS IO Unit Page 4.
 149
 150 *  --------------------------------------------------------------------------
 151 */
 152
 153#ifndef MPI2_CNFG_H
 154#define MPI2_CNFG_H
 155
 156/*****************************************************************************
 157*   Configuration Page Header and defines
 158*****************************************************************************/
 159
 160/* Config Page Header */
 161typedef struct _MPI2_CONFIG_PAGE_HEADER
 162{
 163    U8                 PageVersion;                /* 0x00 */
 164    U8                 PageLength;                 /* 0x01 */
 165    U8                 PageNumber;                 /* 0x02 */
 166    U8                 PageType;                   /* 0x03 */
 167} MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
 168  Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
 169
 170typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
 171{
 172   MPI2_CONFIG_PAGE_HEADER  Struct;
 173   U8                       Bytes[4];
 174   U16                      Word16[2];
 175   U32                      Word32;
 176} MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
 177  Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
 178
 179/* Extended Config Page Header */
 180typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
 181{
 182    U8                  PageVersion;                /* 0x00 */
 183    U8                  Reserved1;                  /* 0x01 */
 184    U8                  PageNumber;                 /* 0x02 */
 185    U8                  PageType;                   /* 0x03 */
 186    U16                 ExtPageLength;              /* 0x04 */
 187    U8                  ExtPageType;                /* 0x06 */
 188    U8                  Reserved2;                  /* 0x07 */
 189} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
 190  MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
 191  Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
 192
 193typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
 194{
 195   MPI2_CONFIG_PAGE_HEADER          Struct;
 196   MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
 197   U8                               Bytes[8];
 198   U16                              Word16[4];
 199   U32                              Word32[2];
 200} MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
 201  Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
 202
 203
 204/* PageType field values */
 205#define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
 206#define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
 207#define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
 208#define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
 209
 210#define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
 211#define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
 212#define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
 213#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
 214#define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
 215#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
 216#define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
 217#define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
 218
 219#define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
 220
 221
 222/* ExtPageType field values */
 223#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
 224#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
 225#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
 226#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
 227#define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
 228#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
 229#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
 230#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
 231#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
 232#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
 233#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
 234
 235
 236/*****************************************************************************
 237*   PageAddress defines
 238*****************************************************************************/
 239
 240/* RAID Volume PageAddress format */
 241#define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
 242#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
 243#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
 244
 245#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
 246
 247
 248/* RAID Physical Disk PageAddress format */
 249#define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
 250#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
 251#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
 252#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
 253
 254#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
 255#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
 256
 257
 258/* SAS Expander PageAddress format */
 259#define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
 260#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
 261#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
 262#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
 263
 264#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
 265#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
 266#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
 267
 268
 269/* SAS Device PageAddress format */
 270#define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
 271#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
 272#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
 273
 274#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
 275
 276
 277/* SAS PHY PageAddress format */
 278#define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
 279#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
 280#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
 281
 282#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
 283#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
 284
 285
 286/* SAS Port PageAddress format */
 287#define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
 288#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
 289#define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
 290
 291#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
 292
 293
 294/* SAS Enclosure PageAddress format */
 295#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
 296#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
 297#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
 298
 299#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
 300
 301
 302/* RAID Configuration PageAddress format */
 303#define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
 304#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
 305#define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
 306#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
 307
 308#define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
 309
 310
 311/* Driver Persistent Mapping PageAddress format */
 312#define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
 313#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
 314
 315#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
 316#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
 317#define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
 318
 319
 320/* Ethernet PageAddress format */
 321#define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
 322#define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
 323
 324#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
 325
 326
 327
 328/****************************************************************************
 329*   Configuration messages
 330****************************************************************************/
 331
 332/* Configuration Request Message */
 333typedef struct _MPI2_CONFIG_REQUEST
 334{
 335    U8                      Action;                     /* 0x00 */
 336    U8                      SGLFlags;                   /* 0x01 */
 337    U8                      ChainOffset;                /* 0x02 */
 338    U8                      Function;                   /* 0x03 */
 339    U16                     ExtPageLength;              /* 0x04 */
 340    U8                      ExtPageType;                /* 0x06 */
 341    U8                      MsgFlags;                   /* 0x07 */
 342    U8                      VP_ID;                      /* 0x08 */
 343    U8                      VF_ID;                      /* 0x09 */
 344    U16                     Reserved1;                  /* 0x0A */
 345        U8                      Reserved2;                  /* 0x0C */
 346        U8                      ProxyVF_ID;                 /* 0x0D */
 347        U16                     Reserved4;                  /* 0x0E */
 348    U32                     Reserved3;                  /* 0x10 */
 349    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
 350    U32                     PageAddress;                /* 0x18 */
 351    MPI2_SGE_IO_UNION       PageBufferSGE;              /* 0x1C */
 352} MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
 353  Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
 354
 355/* values for the Action field */
 356#define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
 357#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
 358#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
 359#define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
 360#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
 361#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
 362#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
 363#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
 364
 365/* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
 366
 367
 368/* Config Reply Message */
 369typedef struct _MPI2_CONFIG_REPLY
 370{
 371    U8                      Action;                     /* 0x00 */
 372    U8                      SGLFlags;                   /* 0x01 */
 373    U8                      MsgLength;                  /* 0x02 */
 374    U8                      Function;                   /* 0x03 */
 375    U16                     ExtPageLength;              /* 0x04 */
 376    U8                      ExtPageType;                /* 0x06 */
 377    U8                      MsgFlags;                   /* 0x07 */
 378    U8                      VP_ID;                      /* 0x08 */
 379    U8                      VF_ID;                      /* 0x09 */
 380    U16                     Reserved1;                  /* 0x0A */
 381    U16                     Reserved2;                  /* 0x0C */
 382    U16                     IOCStatus;                  /* 0x0E */
 383    U32                     IOCLogInfo;                 /* 0x10 */
 384    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
 385} MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
 386  Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
 387
 388
 389
 390/*****************************************************************************
 391*
 392*               C o n f i g u r a t i o n    P a g e s
 393*
 394*****************************************************************************/
 395
 396/****************************************************************************
 397*   Manufacturing Config pages
 398****************************************************************************/
 399
 400#define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
 401
 402/* SAS */
 403#define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
 404#define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
 405#define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
 406#define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
 407#define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
 408#define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
 409#define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
 410
 411#define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
 412
 413#define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
 414#define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
 415#define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
 416#define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
 417#define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
 418#define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
 419#define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
 420#define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
 421#define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
 422
 423
 424
 425
 426/* Manufacturing Page 0 */
 427
 428typedef struct _MPI2_CONFIG_PAGE_MAN_0
 429{
 430    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 431    U8                      ChipName[16];               /* 0x04 */
 432    U8                      ChipRevision[8];            /* 0x14 */
 433    U8                      BoardName[16];              /* 0x1C */
 434    U8                      BoardAssembly[16];          /* 0x2C */
 435    U8                      BoardTracerNumber[16];      /* 0x3C */
 436} MPI2_CONFIG_PAGE_MAN_0,
 437  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
 438  Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
 439
 440#define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
 441
 442
 443/* Manufacturing Page 1 */
 444
 445typedef struct _MPI2_CONFIG_PAGE_MAN_1
 446{
 447    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 448    U8                      VPD[256];                   /* 0x04 */
 449} MPI2_CONFIG_PAGE_MAN_1,
 450  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
 451  Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
 452
 453#define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
 454
 455
 456typedef struct _MPI2_CHIP_REVISION_ID
 457{
 458    U16 DeviceID;                                       /* 0x00 */
 459    U8  PCIRevisionID;                                  /* 0x02 */
 460    U8  Reserved;                                       /* 0x03 */
 461} MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
 462  Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
 463
 464
 465/* Manufacturing Page 2 */
 466
 467/*
 468 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 469 * one and check Header.PageLength at runtime.
 470 */
 471#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
 472#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
 473#endif
 474
 475typedef struct _MPI2_CONFIG_PAGE_MAN_2
 476{
 477    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 478    MPI2_CHIP_REVISION_ID   ChipId;                     /* 0x04 */
 479    U32                     HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
 480} MPI2_CONFIG_PAGE_MAN_2,
 481  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
 482  Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
 483
 484#define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
 485
 486
 487/* Manufacturing Page 3 */
 488
 489/*
 490 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 491 * one and check Header.PageLength at runtime.
 492 */
 493#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
 494#define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
 495#endif
 496
 497typedef struct _MPI2_CONFIG_PAGE_MAN_3
 498{
 499    MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
 500    MPI2_CHIP_REVISION_ID               ChipId;         /* 0x04 */
 501    U32                                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
 502} MPI2_CONFIG_PAGE_MAN_3,
 503  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
 504  Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
 505
 506#define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
 507
 508
 509/* Manufacturing Page 4 */
 510
 511typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
 512{
 513    U8                          PowerSaveFlags;                 /* 0x00 */
 514    U8                          InternalOperationsSleepTime;    /* 0x01 */
 515    U8                          InternalOperationsRunTime;      /* 0x02 */
 516    U8                          HostIdleTime;                   /* 0x03 */
 517} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
 518  MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
 519  Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
 520
 521/* defines for the PowerSaveFlags field */
 522#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
 523#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
 524#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
 525#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
 526
 527typedef struct _MPI2_CONFIG_PAGE_MAN_4
 528{
 529    MPI2_CONFIG_PAGE_HEADER             Header;                 /* 0x00 */
 530    U32                                 Reserved1;              /* 0x04 */
 531    U32                                 Flags;                  /* 0x08 */
 532    U8                                  InquirySize;            /* 0x0C */
 533    U8                                  Reserved2;              /* 0x0D */
 534    U16                                 Reserved3;              /* 0x0E */
 535    U8                                  InquiryData[56];        /* 0x10 */
 536    U32                                 RAID0VolumeSettings;    /* 0x48 */
 537    U32                                 RAID1EVolumeSettings;   /* 0x4C */
 538    U32                                 RAID1VolumeSettings;    /* 0x50 */
 539    U32                                 RAID10VolumeSettings;   /* 0x54 */
 540    U32                                 Reserved4;              /* 0x58 */
 541    U32                                 Reserved5;              /* 0x5C */
 542    MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /* 0x60 */
 543    U8                                  MaxOCEDisks;            /* 0x64 */
 544    U8                                  ResyncRate;             /* 0x65 */
 545    U16                                 DataScrubDuration;      /* 0x66 */
 546    U8                                  MaxHotSpares;           /* 0x68 */
 547    U8                                  MaxPhysDisksPerVol;     /* 0x69 */
 548    U8                                  MaxPhysDisks;           /* 0x6A */
 549    U8                                  MaxVolumes;             /* 0x6B */
 550} MPI2_CONFIG_PAGE_MAN_4,
 551  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
 552  Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
 553
 554#define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
 555
 556/* Manufacturing Page 4 Flags field */
 557#define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
 558#define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
 559
 560#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
 561#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
 562#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
 563
 564#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
 565#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
 566#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
 567#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
 568#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
 569
 570#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
 571#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
 572#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
 573#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
 574
 575#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
 576#define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
 577#define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
 578#define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
 579#define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
 580#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
 581#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
 582#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
 583
 584
 585/* Manufacturing Page 5 */
 586
 587/*
 588 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 589 * one and check the value returned for NumPhys at runtime.
 590 */
 591#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
 592#define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
 593#endif
 594
 595typedef struct _MPI2_MANUFACTURING5_ENTRY
 596{
 597    U64                                 WWID;           /* 0x00 */
 598    U64                                 DeviceName;     /* 0x08 */
 599} MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
 600  Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
 601
 602typedef struct _MPI2_CONFIG_PAGE_MAN_5
 603{
 604    MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
 605    U8                                  NumPhys;        /* 0x04 */
 606    U8                                  Reserved1;      /* 0x05 */
 607    U16                                 Reserved2;      /* 0x06 */
 608    U32                                 Reserved3;      /* 0x08 */
 609    U32                                 Reserved4;      /* 0x0C */
 610    MPI2_MANUFACTURING5_ENTRY           Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
 611} MPI2_CONFIG_PAGE_MAN_5,
 612  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
 613  Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
 614
 615#define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
 616
 617
 618/* Manufacturing Page 6 */
 619
 620typedef struct _MPI2_CONFIG_PAGE_MAN_6
 621{
 622    MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 623    U32                             ProductSpecificInfo;/* 0x04 */
 624} MPI2_CONFIG_PAGE_MAN_6,
 625  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
 626  Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
 627
 628#define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
 629
 630
 631/* Manufacturing Page 7 */
 632
 633typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
 634{
 635    U32                         Pinout;                 /* 0x00 */
 636    U8                          Connector[16];          /* 0x04 */
 637    U8                          Location;               /* 0x14 */
 638        U8                          ReceptacleID;           /* 0x15 */
 639    U16                         Slot;                   /* 0x16 */
 640    U32                         Reserved2;              /* 0x18 */
 641} MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
 642  Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
 643
 644/* defines for the Pinout field */
 645#define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
 646#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
 647
 648#define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
 649#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
 650#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
 651#define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
 652#define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
 653#define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
 654#define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
 655#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
 656#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
 657#define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
 658#define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
 659#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
 660#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
 661#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
 662#define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
 663
 664/* defines for the Location field */
 665#define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
 666#define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
 667#define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
 668#define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
 669#define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
 670#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
 671#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
 672
 673/*
 674 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 675 * one and check the value returned for NumPhys at runtime.
 676 */
 677#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
 678#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
 679#endif
 680
 681typedef struct _MPI2_CONFIG_PAGE_MAN_7
 682{
 683    MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 684    U32                             Reserved1;          /* 0x04 */
 685    U32                             Reserved2;          /* 0x08 */
 686    U32                             Flags;              /* 0x0C */
 687    U8                              EnclosureName[16];  /* 0x10 */
 688    U8                              NumPhys;            /* 0x20 */
 689    U8                              Reserved3;          /* 0x21 */
 690    U16                             Reserved4;          /* 0x22 */
 691    MPI2_MANPAGE7_CONNECTOR_INFO    ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
 692} MPI2_CONFIG_PAGE_MAN_7,
 693  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
 694  Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
 695
 696#define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
 697
 698/* defines for the Flags field */
 699#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
 700
 701
 702/*
 703 * Generic structure to use for product-specific manufacturing pages
 704 * (currently Manufacturing Page 8 through Manufacturing Page 31).
 705 */
 706
 707typedef struct _MPI2_CONFIG_PAGE_MAN_PS
 708{
 709    MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
 710    U32                             ProductSpecificInfo;/* 0x04 */
 711} MPI2_CONFIG_PAGE_MAN_PS,
 712  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
 713  Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
 714
 715#define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
 716#define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
 717#define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
 718#define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
 719#define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
 720#define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
 721#define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
 722#define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
 723#define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
 724#define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
 725#define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
 726#define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
 727#define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
 728#define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
 729#define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
 730#define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
 731#define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
 732#define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
 733#define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
 734#define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
 735#define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
 736#define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
 737#define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
 738#define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
 739
 740
 741/****************************************************************************
 742*   IO Unit Config Pages
 743****************************************************************************/
 744
 745/* IO Unit Page 0 */
 746
 747typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
 748{
 749    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 750    U64                     UniqueValue;                /* 0x04 */
 751    MPI2_VERSION_UNION      NvdataVersionDefault;       /* 0x08 */
 752    MPI2_VERSION_UNION      NvdataVersionPersistent;    /* 0x0A */
 753} MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
 754  Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
 755
 756#define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
 757
 758
 759/* IO Unit Page 1 */
 760
 761typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
 762{
 763    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 764    U32                     Flags;                      /* 0x04 */
 765} MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
 766  Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
 767
 768#define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
 769
 770/* IO Unit Page 1 Flags defines */
 771#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
 772#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
 773#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
 774#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
 775#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
 776#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
 777#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
 778#define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
 779#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
 780#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
 781
 782
 783/* IO Unit Page 3 */
 784
 785/*
 786 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 787 * one and check the value returned for GPIOCount at runtime.
 788 */
 789#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
 790#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
 791#endif
 792
 793typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
 794{
 795    MPI2_CONFIG_PAGE_HEADER Header;                                   /* 0x00 */
 796    U8                      GPIOCount;                                /* 0x04 */
 797    U8                      Reserved1;                                /* 0x05 */
 798    U16                     Reserved2;                                /* 0x06 */
 799    U16                     GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
 800} MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
 801  Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
 802
 803#define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
 804
 805/* defines for IO Unit Page 3 GPIOVal field */
 806#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
 807#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
 808#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
 809#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
 810
 811
 812/* IO Unit Page 5 */
 813
 814/*
 815 * Upper layer code (drivers, utilities, etc.) should leave this define set to
 816 * one and check the value returned for NumDmaEngines at runtime.
 817 */
 818#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
 819#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
 820#endif
 821
 822typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
 823    MPI2_CONFIG_PAGE_HEADER Header;                             /* 0x00 */
 824    U64                     RaidAcceleratorBufferBaseAddress;  /* 0x04 */
 825    U64                     RaidAcceleratorBufferSize;         /* 0x0C */
 826    U64                     RaidAcceleratorControlBaseAddress; /* 0x14 */
 827    U8                      RAControlSize;                     /* 0x1C */
 828    U8                      NumDmaEngines;                     /* 0x1D */
 829    U8                      RAMinControlSize;                  /* 0x1E */
 830    U8                      RAMaxControlSize;                  /* 0x1F */
 831    U32                     Reserved1;                         /* 0x20 */
 832    U32                     Reserved2;                         /* 0x24 */
 833    U32                     Reserved3;                         /* 0x28 */
 834    U32                     DmaEngineCapabilities
 835                                [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
 836} MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
 837  Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
 838
 839#define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
 840
 841/* defines for IO Unit Page 5 DmaEngineCapabilities field */
 842#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFF00)
 843#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
 844
 845#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
 846#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
 847#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
 848#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
 849
 850
 851/* IO Unit Page 6 */
 852
 853typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
 854    MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 855    U16                     Flags;                                  /* 0x04 */
 856    U8                      RAHostControlSize;                      /* 0x06 */
 857    U8                      Reserved0;                              /* 0x07 */
 858    U64                     RaidAcceleratorHostControlBaseAddress;  /* 0x08 */
 859    U32                     Reserved1;                              /* 0x10 */
 860    U32                     Reserved2;                              /* 0x14 */
 861    U32                     Reserved3;                              /* 0x18 */
 862} MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
 863  Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
 864
 865#define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
 866
 867/* defines for IO Unit Page 6 Flags field */
 868#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
 869
 870
 871/* IO Unit Page 7 */
 872
 873typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
 874    MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 875    U16                     Reserved1;                              /* 0x04 */
 876    U8                      PCIeWidth;                              /* 0x06 */
 877    U8                      PCIeSpeed;                              /* 0x07 */
 878    U32                     ProcessorState;                         /* 0x08 */
 879    U32                     PowerManagementCapabilities;            /* 0x0C */
 880    U16                     IOCTemperature;                         /* 0x10 */
 881    U8                      IOCTemperatureUnits;                    /* 0x12 */
 882    U8                      IOCSpeed;                               /* 0x13 */
 883        U16                     BoardTemperature;              /* 0x14 */
 884        U8                      BoardTemperatureUnits;         /* 0x16 */
 885        U8                      Reserved3;                     /* 0x17 */
 886} MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
 887  Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
 888
 889#define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x02)
 890
 891/* defines for IO Unit Page 7 PCIeWidth field */
 892#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
 893#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
 894#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
 895#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
 896
 897/* defines for IO Unit Page 7 PCIeSpeed field */
 898#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
 899#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
 900#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
 901
 902/* defines for IO Unit Page 7 ProcessorState field */
 903#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
 904#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
 905
 906#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
 907#define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
 908#define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
 909
 910/* defines for IO Unit Page 7 PowerManagementCapabilities field */
 911#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
 912#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
 913#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
 914#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /* obsolete */
 915#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /* obsolete */
 916
 917/* defines for IO Unit Page 7 IOCTemperatureUnits field */
 918#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
 919#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
 920#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
 921
 922/* defines for IO Unit Page 7 IOCSpeed field */
 923#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
 924#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
 925#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
 926#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
 927
 928/* defines for IO Unit Page 7 BoardTemperatureUnits field */
 929#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
 930#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
 931#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
 932
 933/* IO Unit Page 8 */
 934
 935#define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
 936
 937typedef struct _MPI2_IOUNIT8_SENSOR {
 938        U16                     Flags;                /* 0x00 */
 939        U16                     Reserved1;            /* 0x02 */
 940        U16
 941                Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
 942        U32                     Reserved2;            /* 0x0C */
 943        U32                     Reserved3;            /* 0x10 */
 944        U32                     Reserved4;            /* 0x14 */
 945} MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
 946Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
 947
 948/* defines for IO Unit Page 8 Sensor Flags field */
 949#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
 950#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
 951#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
 952#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
 953
 954/*
 955 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 956 * one and check the value returned for NumSensors at runtime.
 957 */
 958#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
 959#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
 960#endif
 961
 962typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
 963        MPI2_CONFIG_PAGE_HEADER Header;               /* 0x00 */
 964        U32                     Reserved1;            /* 0x04 */
 965        U32                     Reserved2;            /* 0x08 */
 966        U8                      NumSensors;           /* 0x0C */
 967        U8                      PollingInterval;      /* 0x0D */
 968        U16                     Reserved3;            /* 0x0E */
 969        MPI2_IOUNIT8_SENSOR
 970                        Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
 971} MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
 972Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
 973
 974#define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
 975
 976
 977/* IO Unit Page 9 */
 978
 979typedef struct _MPI2_IOUNIT9_SENSOR {
 980        U16                     CurrentTemperature;     /* 0x00 */
 981        U16                     Reserved1;              /* 0x02 */
 982        U8                      Flags;                  /* 0x04 */
 983        U8                      Reserved2;              /* 0x05 */
 984        U16                     Reserved3;              /* 0x06 */
 985        U32                     Reserved4;              /* 0x08 */
 986        U32                     Reserved5;              /* 0x0C */
 987} MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
 988Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
 989
 990/* defines for IO Unit Page 9 Sensor Flags field */
 991#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
 992
 993/*
 994 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 995 * one and check the value returned for NumSensors at runtime.
 996 */
 997#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
 998#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
 999#endif
1000

1001typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1002        MPI2_CONFIG_PAGE_HEADER Header;                /* 0x00 */
1003        U32                     Reserved1;             /* 0x04 */
1004        U32                     Reserved2;             /* 0x08 */
1005        U8                      NumSensors;            /* 0x0C */
1006        U8                      Reserved4;             /* 0x0D */
1007        U16                     Reserved3;             /* 0x0E */
1008        MPI2_IOUNIT9_SENSOR
1009                        Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1010} MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1011Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1012
1013#define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1014
1015
1016/* IO Unit Page 10 */
1017
1018typedef struct _MPI2_IOUNIT10_FUNCTION {
1019        U8                      CreditPercent;      /* 0x00 */
1020        U8                      Reserved1;          /* 0x01 */
1021        U16                     Reserved2;          /* 0x02 */
1022} MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1023Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1024
1025/*
1026 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1027 * one and check the value returned for NumFunctions at runtime.
1028 */
1029#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1030#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1031#endif
1032
1033typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1034        MPI2_CONFIG_PAGE_HEADER Header;                    /* 0x00 */
1035        U8                      NumFunctions;             /* 0x04 */
1036        U8                      Reserved1;              /* 0x05 */
1037        U16                     Reserved2;              /* 0x06 */
1038        U32                     Reserved3;              /* 0x08 */
1039        U32                     Reserved4;              /* 0x0C */
1040        MPI2_IOUNIT10_FUNCTION
1041                Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
1042} MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1043Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1044
1045#define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1046
1047
1048
1049/****************************************************************************
1050*   IOC Config Pages
1051****************************************************************************/
1052
1053/* IOC Page 0 */
1054
1055typedef struct _MPI2_CONFIG_PAGE_IOC_0
1056{
1057    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1058    U32                     Reserved1;                  /* 0x04 */
1059    U32                     Reserved2;                  /* 0x08 */
1060    U16                     VendorID;                   /* 0x0C */
1061    U16                     DeviceID;                   /* 0x0E */
1062    U8                      RevisionID;                 /* 0x10 */
1063    U8                      Reserved3;                  /* 0x11 */
1064    U16                     Reserved4;                  /* 0x12 */
1065    U32                     ClassCode;                  /* 0x14 */
1066    U16                     SubsystemVendorID;          /* 0x18 */
1067    U16                     SubsystemID;                /* 0x1A */
1068} MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1069  Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1070
1071#define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1072
1073
1074/* IOC Page 1 */
1075
1076typedef struct _MPI2_CONFIG_PAGE_IOC_1
1077{
1078    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1079    U32                     Flags;                      /* 0x04 */
1080    U32                     CoalescingTimeout;          /* 0x08 */
1081    U8                      CoalescingDepth;            /* 0x0C */
1082    U8                      PCISlotNum;                 /* 0x0D */
1083    U8                      PCIBusNum;                  /* 0x0E */
1084    U8                      PCIDomainSegment;           /* 0x0F */
1085    U32                     Reserved1;                  /* 0x10 */
1086    U32                     Reserved2;                  /* 0x14 */
1087} MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1088  Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1089
1090#define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1091
1092/* defines for IOC Page 1 Flags field */
1093#define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1094
1095#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1096#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1097#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1098
1099/* IOC Page 6 */
1100
1101typedef struct _MPI2_CONFIG_PAGE_IOC_6
1102{
1103    MPI2_CONFIG_PAGE_HEADER Header;                         /* 0x00 */
1104    U32                     CapabilitiesFlags;              /* 0x04 */
1105    U8                      MaxDrivesRAID0;                 /* 0x08 */
1106    U8                      MaxDrivesRAID1;                 /* 0x09 */
1107    U8                      MaxDrivesRAID1E;                /* 0x0A */
1108    U8                      MaxDrivesRAID10;                /* 0x0B */
1109    U8                      MinDrivesRAID0;                 /* 0x0C */
1110    U8                      MinDrivesRAID1;                 /* 0x0D */
1111    U8                      MinDrivesRAID1E;                /* 0x0E */
1112    U8                      MinDrivesRAID10;                /* 0x0F */
1113    U32                     Reserved1;                      /* 0x10 */
1114    U8                      MaxGlobalHotSpares;             /* 0x14 */
1115    U8                      MaxPhysDisks;                   /* 0x15 */
1116    U8                      MaxVolumes;                     /* 0x16 */
1117    U8                      MaxConfigs;                     /* 0x17 */
1118    U8                      MaxOCEDisks;                    /* 0x18 */
1119    U8                      Reserved2;                      /* 0x19 */
1120    U16                     Reserved3;                      /* 0x1A */
1121    U32                     SupportedStripeSizeMapRAID0;    /* 0x1C */
1122    U32                     SupportedStripeSizeMapRAID1E;   /* 0x20 */
1123    U32                     SupportedStripeSizeMapRAID10;   /* 0x24 */
1124    U32                     Reserved4;                      /* 0x28 */
1125    U32                     Reserved5;                      /* 0x2C */
1126    U16                     DefaultMetadataSize;            /* 0x30 */
1127    U16                     Reserved6;                      /* 0x32 */
1128    U16                     MaxBadBlockTableEntries;        /* 0x34 */
1129    U16                     Reserved7;                      /* 0x36 */
1130    U32                     IRNvsramVersion;                /* 0x38 */
1131} MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1132  Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1133
1134#define MPI2_IOCPAGE6_PAGEVERSION                       (0x04)
1135
1136/* defines for IOC Page 6 CapabilitiesFlags */
1137#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1138#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1139#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1140#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1141#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1142
1143
1144/* IOC Page 7 */
1145
1146#define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1147
1148typedef struct _MPI2_CONFIG_PAGE_IOC_7
1149{
1150    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1151    U32                     Reserved1;                  /* 0x04 */
1152    U32                     EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1153    U16                     SASBroadcastPrimitiveMasks; /* 0x18 */
1154        U16                     SASNotifyPrimitiveMasks;    /* 0x1A */
1155    U32                     Reserved3;                  /* 0x1C */
1156} MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1157  Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1158
1159#define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1160
1161
1162/* IOC Page 8 */
1163
1164typedef struct _MPI2_CONFIG_PAGE_IOC_8
1165{
1166    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1167    U8                      NumDevsPerEnclosure;        /* 0x04 */
1168    U8                      Reserved1;                  /* 0x05 */
1169    U16                     Reserved2;                  /* 0x06 */
1170    U16                     MaxPersistentEntries;       /* 0x08 */
1171    U16                     MaxNumPhysicalMappedIDs;    /* 0x0A */
1172    U16                     Flags;                      /* 0x0C */
1173    U16                     Reserved3;                  /* 0x0E */
1174    U16                     IRVolumeMappingFlags;       /* 0x10 */
1175    U16                     Reserved4;                  /* 0x12 */
1176    U32                     Reserved5;                  /* 0x14 */
1177} MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1178  Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1179
1180#define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1181
1182/* defines for IOC Page 8 Flags field */
1183#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1184#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1185
1186#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1187#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1188#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1189
1190#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1191#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1192
1193/* defines for IOC Page 8 IRVolumeMappingFlags */
1194#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1195#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1196#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1197
1198
1199/****************************************************************************
1200*   BIOS Config Pages
1201****************************************************************************/
1202
1203/* BIOS Page 1 */
1204
1205typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1206{
1207    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1208    U32                     BiosOptions;                /* 0x04 */
1209    U32                     IOCSettings;                /* 0x08 */
1210    U32                     Reserved1;                  /* 0x0C */
1211    U32                     DeviceSettings;             /* 0x10 */
1212    U16                     NumberOfDevices;            /* 0x14 */
1213    U16                     Reserved2;                  /* 0x16 */
1214    U16                     IOTimeoutBlockDevicesNonRM; /* 0x18 */
1215    U16                     IOTimeoutSequential;        /* 0x1A */
1216    U16                     IOTimeoutOther;             /* 0x1C */
1217    U16                     IOTimeoutBlockDevicesRM;    /* 0x1E */
1218} MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1219  Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1220
1221#define MPI2_BIOSPAGE1_PAGEVERSION                      (0x04)
1222
1223/* values for BIOS Page 1 BiosOptions field */
1224#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS             (0x00000001)
1225
1226/* values for BIOS Page 1 IOCSettings field */
1227#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1228#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1229#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1230
1231#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1232#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1233#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1234#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1235
1236#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1237#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1238#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1239#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1240#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1241
1242#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1243
1244/* values for BIOS Page 1 DeviceSettings field */
1245#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1246#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1247#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1248#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1249#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1250
1251
1252/* BIOS Page 2 */
1253
1254typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1255{
1256    U32         Reserved1;                              /* 0x00 */
1257    U32         Reserved2;                              /* 0x04 */
1258    U32         Reserved3;                              /* 0x08 */
1259    U32         Reserved4;                              /* 0x0C */
1260    U32         Reserved5;                              /* 0x10 */
1261    U32         Reserved6;                              /* 0x14 */
1262} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1263  MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1264  Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1265
1266typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1267{
1268    U64         SASAddress;                             /* 0x00 */
1269    U8          LUN[8];                                 /* 0x08 */
1270    U32         Reserved1;                              /* 0x10 */
1271    U32         Reserved2;                              /* 0x14 */
1272} MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1273  Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1274
1275typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1276{
1277    U64         EnclosureLogicalID;                     /* 0x00 */
1278    U32         Reserved1;                              /* 0x08 */
1279    U32         Reserved2;                              /* 0x0C */
1280    U16         SlotNumber;                             /* 0x10 */
1281    U16         Reserved3;                              /* 0x12 */
1282    U32         Reserved4;                              /* 0x14 */
1283} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1284  MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1285  Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1286
1287typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1288{
1289    U64         DeviceName;                             /* 0x00 */
1290    U8          LUN[8];                                 /* 0x08 */
1291    U32         Reserved1;                              /* 0x10 */
1292    U32         Reserved2;                              /* 0x14 */
1293} MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1294  Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1295
1296typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1297{
1298    MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1299    MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1300    MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1301    MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1302} MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1303  Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1304
1305typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1306{
1307    MPI2_CONFIG_PAGE_HEADER     Header;                 /* 0x00 */
1308    U32                         Reserved1;              /* 0x04 */
1309    U32                         Reserved2;              /* 0x08 */
1310    U32                         Reserved3;              /* 0x0C */
1311    U32                         Reserved4;              /* 0x10 */
1312    U32                         Reserved5;              /* 0x14 */
1313    U32                         Reserved6;              /* 0x18 */
1314    U8                          ReqBootDeviceForm;      /* 0x1C */
1315    U8                          Reserved7;              /* 0x1D */
1316    U16                         Reserved8;              /* 0x1E */
1317    MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /* 0x20 */
1318    U8                          ReqAltBootDeviceForm;   /* 0x38 */
1319    U8                          Reserved9;              /* 0x39 */
1320    U16                         Reserved10;             /* 0x3A */
1321    MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /* 0x3C */
1322    U8                          CurrentBootDeviceForm;  /* 0x58 */
1323    U8                          Reserved11;             /* 0x59 */
1324    U16                         Reserved12;             /* 0x5A */
1325    MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /* 0x58 */
1326} MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1327  Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1328
1329#define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1330
1331/* values for BIOS Page 2 BootDeviceForm fields */
1332#define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1333#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1334#define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1335#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1336#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1337
1338
1339/* BIOS Page 3 */
1340
1341typedef struct _MPI2_ADAPTER_INFO
1342{
1343    U8      PciBusNumber;                               /* 0x00 */
1344    U8      PciDeviceAndFunctionNumber;                 /* 0x01 */
1345    U16     AdapterFlags;                               /* 0x02 */
1346} MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1347  Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1348
1349#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1350#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1351
1352typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1353{
1354    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1355    U32                     GlobalFlags;                /* 0x04 */
1356    U32                     BiosVersion;                /* 0x08 */
1357    MPI2_ADAPTER_INFO       AdapterOrder[4];            /* 0x0C */
1358    U32                     Reserved1;                  /* 0x1C */
1359} MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1360  Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1361
1362#define MPI2_BIOSPAGE3_PAGEVERSION                      (0x00)
1363
1364/* values for BIOS Page 3 GlobalFlags */
1365#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1366#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1367#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1368
1369#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1370#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1371#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1372#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1373
1374
1375/* BIOS Page 4 */
1376
1377/*
1378 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1379 * one and check the value returned for NumPhys at runtime.
1380 */
1381#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1382#define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1383#endif
1384
1385typedef struct _MPI2_BIOS4_ENTRY
1386{
1387    U64                     ReassignmentWWID;       /* 0x00 */
1388    U64                     ReassignmentDeviceName; /* 0x08 */
1389} MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1390  Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1391
1392typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1393{
1394    MPI2_CONFIG_PAGE_HEADER Header;                             /* 0x00 */
1395    U8                      NumPhys;                            /* 0x04 */
1396    U8                      Reserved1;                          /* 0x05 */
1397    U16                     Reserved2;                          /* 0x06 */
1398    MPI2_BIOS4_ENTRY        Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /* 0x08 */
1399} MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1400  Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1401
1402#define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1403
1404
1405/****************************************************************************
1406*   RAID Volume Config Pages
1407****************************************************************************/
1408
1409/* RAID Volume Page 0 */
1410
1411typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1412{
1413    U8                      RAIDSetNum;                 /* 0x00 */
1414    U8                      PhysDiskMap;                /* 0x01 */
1415    U8                      PhysDiskNum;                /* 0x02 */
1416    U8                      Reserved;                   /* 0x03 */
1417} MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1418  Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1419
1420/* defines for the PhysDiskMap field */
1421#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1422#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1423
1424typedef struct _MPI2_RAIDVOL0_SETTINGS
1425{
1426    U16                     Settings;                   /* 0x00 */
1427    U8                      HotSparePool;               /* 0x01 */
1428    U8                      Reserved;                   /* 0x02 */
1429} MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1430  Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1431
1432/* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1433#define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1434#define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1435#define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1436#define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1437#define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1438#define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1439#define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1440#define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1441
1442/* RAID Volume Page 0 VolumeSettings defines */
1443#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1444#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1445
1446#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1447#define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1448#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1449#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1450
1451/*
1452 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1453 * one and check the value returned for NumPhysDisks at runtime.
1454 */
1455#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1456#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1457#endif
1458
1459typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1460{
1461    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1462    U16                     DevHandle;                  /* 0x04 */
1463    U8                      VolumeState;                /* 0x06 */
1464    U8                      VolumeType;                 /* 0x07 */
1465    U32                     VolumeStatusFlags;          /* 0x08 */
1466    MPI2_RAIDVOL0_SETTINGS  VolumeSettings;             /* 0x0C */
1467    U64                     MaxLBA;                     /* 0x10 */
1468    U32                     StripeSize;                 /* 0x18 */
1469    U16                     BlockSize;                  /* 0x1C */
1470    U16                     Reserved1;                  /* 0x1E */
1471    U8                      SupportedPhysDisks;         /* 0x20 */
1472    U8                      ResyncRate;                 /* 0x21 */
1473    U16                     DataScrubDuration;          /* 0x22 */
1474    U8                      NumPhysDisks;               /* 0x24 */
1475    U8                      Reserved2;                  /* 0x25 */
1476    U8                      Reserved3;                  /* 0x26 */
1477    U8                      InactiveStatus;             /* 0x27 */
1478    MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1479} MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1480  Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1481
1482#define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1483
1484/* values for RAID VolumeState */
1485#define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1486#define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1487#define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1488#define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1489#define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1490#define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1491
1492/* values for RAID VolumeType */
1493#define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1494#define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1495#define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1496#define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1497#define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1498
1499/* values for RAID Volume Page 0 VolumeStatusFlags field */
1500#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1501#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1502#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1503#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1504#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1505#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1506#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1507#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1508#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1509#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1510#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1511#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1512#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1513#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1514#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1515#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1516#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1517#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1518#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1519
1520/* values for RAID Volume Page 0 SupportedPhysDisks field */
1521#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1522#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1523#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1524#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1525
1526/* values for RAID Volume Page 0 InactiveStatus field */
1527#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1528#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1529#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1530#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1531#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1532#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1533#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1534
1535
1536/* RAID Volume Page 1 */
1537
1538typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1539{
1540    MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
1541    U16                     DevHandle;                  /* 0x04 */
1542    U16                     Reserved0;                  /* 0x06 */
1543    U8                      GUID[24];                   /* 0x08 */
1544    U8                      Name[16];                   /* 0x20 */
1545    U64                     WWID;                       /* 0x30 */
1546    U32                     Reserved1;                  /* 0x38 */
1547    U32                     Reserved2;                  /* 0x3C */
1548} MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1549  Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1550
1551#define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1552
1553
1554/****************************************************************************
1555*   RAID Physical Disk Config Pages
1556****************************************************************************/
1557
1558/* RAID Physical Disk Page 0 */
1559
1560typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1561{
1562    U16                     Reserved1;                  /* 0x00 */
1563    U8                      HotSparePool;               /* 0x02 */
1564    U8                      Reserved2;                  /* 0x03 */
1565} MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1566  Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1567
1568/* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1569
1570typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1571{
1572    U8                      VendorID[8];                /* 0x00 */
1573    U8                      ProductID[16];              /* 0x08 */
1574    U8                      ProductRevLevel[4];         /* 0x18 */
1575    U8                      SerialNum[32];              /* 0x1C */
1576} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1577  MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1578  Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1579
1580typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1581{
1582    MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1583    U16                             DevHandle;                  /* 0x04 */
1584    U8                              Reserved1;                  /* 0x06 */
1585    U8                              PhysDiskNum;                /* 0x07 */
1586    MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;           /* 0x08 */
1587    U32                             Reserved2;                  /* 0x0C */
1588    MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;                /* 0x10 */
1589    U32                             Reserved3;                  /* 0x4C */
1590    U8                              PhysDiskState;              /* 0x50 */
1591    U8                              OfflineReason;              /* 0x51 */
1592    U8                              IncompatibleReason;         /* 0x52 */
1593    U8                              PhysDiskAttributes;         /* 0x53 */
1594    U32                             PhysDiskStatusFlags;        /* 0x54 */
1595    U64                             DeviceMaxLBA;               /* 0x58 */
1596    U64                             HostMaxLBA;                 /* 0x60 */
1597    U64                             CoercedMaxLBA;              /* 0x68 */
1598    U16                             BlockSize;                  /* 0x70 */
1599    U16                             Reserved5;                  /* 0x72 */
1600    U32                             Reserved6;                  /* 0x74 */
1601} MPI2_CONFIG_PAGE_RD_PDISK_0,
1602  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1603  Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1604
1605#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1606
1607/* PhysDiskState defines */
1608#define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1609#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1610#define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
1611#define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
1612#define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
1613#define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
1614#define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
1615#define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
1616
1617/* OfflineReason defines */
1618#define MPI2_PHYSDISK0_ONLINE                           (0x00)
1619#define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
1620#define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
1621#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
1622#define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
1623#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
1624#define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
1625
1626/* IncompatibleReason defines */
1627#define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
1628#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
1629#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
1630#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
1631#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
1632#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
1633#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
1634#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
1635
1636/* PhysDiskAttributes defines */
1637#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
1638#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
1639#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
1640
1641#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
1642#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
1643#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
1644
1645/* PhysDiskStatusFlags defines */
1646#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
1647#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
1648#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
1649#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
1650#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1651#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
1652#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
1653#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
1654
1655
1656/* RAID Physical Disk Page 1 */
1657
1658/*
1659 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1660 * one and check the value returned for NumPhysDiskPaths at runtime.
1661 */
1662#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1663#define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
1664#endif
1665
1666typedef struct _MPI2_RAIDPHYSDISK1_PATH
1667{
1668    U16             DevHandle;          /* 0x00 */
1669    U16             Reserved1;          /* 0x02 */
1670    U64             WWID;               /* 0x04 */
1671    U64             OwnerWWID;          /* 0x0C */
1672    U8              OwnerIdentifier;    /* 0x14 */
1673    U8              Reserved2;          /* 0x15 */
1674    U16             Flags;              /* 0x16 */
1675} MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1676  Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1677
1678/* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1679#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
1680#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
1681#define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
1682
1683typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1684{
1685    MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
1686    U8                              NumPhysDiskPaths;           /* 0x04 */
1687    U8                              PhysDiskNum;                /* 0x05 */
1688    U16                             Reserved1;                  /* 0x06 */
1689    U32                             Reserved2;                  /* 0x08 */
1690    MPI2_RAIDPHYSDISK1_PATH         PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1691} MPI2_CONFIG_PAGE_RD_PDISK_1,
1692  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1693  Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1694
1695#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
1696
1697
1698/****************************************************************************
1699*   values for fields used by several types of SAS Config Pages
1700****************************************************************************/
1701
1702/* values for NegotiatedLinkRates fields */
1703#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
1704#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
1705#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
1706/* link rates used for Negotiated Physical and Logical Link Rate */
1707#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
1708#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
1709#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
1710#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
1711#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
1712#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
1713#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
1714#define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
1715#define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
1716#define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
1717
1718
1719/* values for AttachedPhyInfo fields */
1720#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
1721#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
1722#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
1723
1724#define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
1725#define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
1726#define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
1727#define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
1728#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
1729#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
1730#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
1731#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
1732#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
1733#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
1734
1735
1736/* values for PhyInfo fields */
1737#define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
1738
1739#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
1740#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
1741#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
1742#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
1743#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
1744
1745#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
1746#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
1747#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
1748#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
1749#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
1750#define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
1751
1752#define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
1753#define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
1754#define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
1755#define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
1756#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
1757#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
1758#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
1759#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
1760#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
1761#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
1762
1763#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
1764#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
1765#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
1766#define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
1767
1768#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
1769#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
1770
1771#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
1772#define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
1773#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
1774#define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
1775
1776
1777/* values for SAS ProgrammedLinkRate fields */
1778#define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
1779#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
1780#define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
1781#define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
1782#define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
1783#define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
1784#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
1785#define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
1786#define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
1787#define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
1788
1789
1790/* values for SAS HwLinkRate fields */
1791#define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
1792#define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
1793#define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
1794#define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
1795#define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
1796#define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
1797#define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
1798#define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
1799
1800
1801
1802/****************************************************************************
1803*   SAS IO Unit Config Pages
1804****************************************************************************/
1805
1806/* SAS IO Unit Page 0 */
1807
1808typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1809{
1810    U8          Port;                   /* 0x00 */
1811    U8          PortFlags;              /* 0x01 */
1812    U8          PhyFlags;               /* 0x02 */
1813    U8          NegotiatedLinkRate;     /* 0x03 */
1814    U32         ControllerPhyDeviceInfo;/* 0x04 */
1815    U16         AttachedDevHandle;      /* 0x08 */
1816    U16         ControllerDevHandle;    /* 0x0A */
1817    U32         DiscoveryStatus;        /* 0x0C */
1818    U32         Reserved;               /* 0x10 */
1819} MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1820  Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1821
1822/*
1823 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1824 * one and check the value returned for NumPhys at runtime.
1825 */
1826#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1827#define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
1828#endif
1829
1830typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1831{
1832    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
1833    U32                                 Reserved1;                          /* 0x08 */
1834    U8                                  NumPhys;                            /* 0x0C */
1835    U8                                  Reserved2;                          /* 0x0D */
1836    U16                                 Reserved3;                          /* 0x0E */
1837    MPI2_SAS_IO_UNIT0_PHY_DATA          PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];  /* 0x10 */
1838} MPI2_CONFIG_PAGE_SASIOUNIT_0,
1839  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1840  Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1841
1842#define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
1843
1844/* values for SAS IO Unit Page 0 PortFlags */
1845#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
1846#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
1847
1848/* values for SAS IO Unit Page 0 PhyFlags */
1849#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
1850#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
1851
1852/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1853
1854/* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1855
1856/* values for SAS IO Unit Page 0 DiscoveryStatus */
1857#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
1858#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
1859#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
1860#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
1861#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
1862#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
1863#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
1864#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
1865#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
1866#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
1867#define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
1868#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
1869#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
1870#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
1871#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
1872#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
1873#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
1874#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
1875#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
1876#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
1877
1878
1879/* SAS IO Unit Page 1 */
1880
1881typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1882{
1883    U8          Port;                       /* 0x00 */
1884    U8          PortFlags;                  /* 0x01 */
1885    U8          PhyFlags;                   /* 0x02 */
1886    U8          MaxMinLinkRate;             /* 0x03 */
1887    U32         ControllerPhyDeviceInfo;    /* 0x04 */
1888    U16         MaxTargetPortConnectTime;   /* 0x08 */
1889    U16         Reserved1;                  /* 0x0A */
1890} MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1891  Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1892
1893/*
1894 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1895 * one and check the value returned for NumPhys at runtime.
1896 */
1897#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1898#define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
1899#endif
1900
1901typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1902{
1903    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
1904    U16                                 ControlFlags;                       /* 0x08 */
1905    U16                                 SASNarrowMaxQueueDepth;             /* 0x0A */
1906    U16                                 AdditionalControlFlags;             /* 0x0C */
1907    U16                                 SASWideMaxQueueDepth;               /* 0x0E */
1908    U8                                  NumPhys;                            /* 0x10 */
1909    U8                                  SATAMaxQDepth;                      /* 0x11 */
1910    U8                                  ReportDeviceMissingDelay;           /* 0x12 */
1911    U8                                  IODeviceMissingDelay;               /* 0x13 */
1912    MPI2_SAS_IO_UNIT1_PHY_DATA          PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /* 0x14 */
1913} MPI2_CONFIG_PAGE_SASIOUNIT_1,
1914  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1915  Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1916
1917#define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
1918
1919/* values for SAS IO Unit Page 1 ControlFlags */
1920#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
1921#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
1922#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000)
1923#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
1924
1925#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
1926#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
1927#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
1928#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
1929#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
1930
1931#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
1932#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
1933#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
1934#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
1935#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
1936#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
1937#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
1938#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001)
1939
1940/* values for SAS IO Unit Page 1 AdditionalControlFlags */
1941#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
1942#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
1943#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
1944#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
1945#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
1946#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
1947#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
1948#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
1949
1950/* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1951#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
1952#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
1953
1954/* values for SAS IO Unit Page 1 PortFlags */
1955#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
1956
1957/* values for SAS IO Unit Page 1 PhyFlags */
1958#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
1959#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
1960
1961/* values for SAS IO Unit Page 1 MaxMinLinkRate */
1962#define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
1963#define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
1964#define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
1965#define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
1966#define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
1967#define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
1968#define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
1969#define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
1970
1971/* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1972
1973
1974/* SAS IO Unit Page 4 */
1975
1976typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1977{
1978    U8          MaxTargetSpinup;            /* 0x00 */
1979    U8          SpinupDelay;                /* 0x01 */
1980        U8          SpinupFlags;                /* 0x02 */
1981        U8          Reserved1;                  /* 0x03 */
1982} MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
1983  Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
1984
1985/* defines for SAS IO Unit Page 4 SpinupFlags */
1986#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
1987
1988/*
1989 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1990 * one and check the value returned for NumPhys at runtime.
1991 */
1992#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
1993#define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
1994#endif
1995
1996typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
1997{
1998    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
1999    MPI2_SAS_IOUNIT4_SPINUP_GROUP       SpinupGroupParameters[4];       /* 0x08 */
2000    U32                                 Reserved1;                      /* 0x18 */

2001    U32                                 Reserved2;                      /* 0x1C */
2002    U32                                 Reserved3;                      /* 0x20 */
2003    U8                                  BootDeviceWaitTime;             /* 0x24 */
2004    U8                                  Reserved4;                      /* 0x25 */
2005    U16                                 Reserved5;                      /* 0x26 */
2006    U8                                  NumPhys;                        /* 0x28 */
2007    U8                                  PEInitialSpinupDelay;           /* 0x29 */
2008    U8                                  PEReplyDelay;                   /* 0x2A */
2009    U8                                  Flags;                          /* 0x2B */
2010    U8                                  PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /* 0x2C */
2011} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2012  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2013  Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2014
2015#define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2016
2017/* defines for Flags field */
2018#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2019
2020/* defines for PHY field */
2021#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2022
2023
2024/* SAS IO Unit Page 5 */
2025
2026typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2027    U8          ControlFlags;               /* 0x00 */
2028    U8          PortWidthModGroup;          /* 0x01 */
2029    U16         InactivityTimerExponent;    /* 0x02 */
2030    U8          SATAPartialTimeout;         /* 0x04 */
2031    U8          Reserved2;                  /* 0x05 */
2032    U8          SATASlumberTimeout;         /* 0x06 */
2033    U8          Reserved3;                  /* 0x07 */
2034    U8          SASPartialTimeout;          /* 0x08 */
2035    U8          Reserved4;                  /* 0x09 */
2036    U8          SASSlumberTimeout;          /* 0x0A */
2037    U8          Reserved5;                  /* 0x0B */
2038} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2039  MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2040  Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2041
2042/* defines for ControlFlags field */
2043#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2044#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2045#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2046#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2047
2048/* defines for PortWidthModeGroup field */
2049#define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2050
2051/* defines for InactivityTimerExponent field */
2052#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2053#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2054#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2055#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2056#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2057#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2058#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2059#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2060
2061#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2062#define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2063#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2064#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2065#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2066#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2067#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2068#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2069
2070/*
2071 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2072 * one and check the value returned for NumPhys at runtime.
2073 */
2074#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2075#define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2076#endif
2077
2078typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2079    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;         /* 0x00 */
2080    U8                                  NumPhys;        /* 0x08 */
2081    U8                                  Reserved1;      /* 0x09 */
2082    U16                                 Reserved2;      /* 0x0A */
2083    U32                                 Reserved3;      /* 0x0C */
2084    MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS   SASPhyPowerManagementSettings
2085                                        [MPI2_SAS_IOUNIT5_PHY_MAX];  /* 0x10 */
2086} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2087  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2088  Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2089
2090#define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2091
2092
2093/* SAS IO Unit Page 6 */
2094
2095typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2096    U8          CurrentStatus;              /* 0x00 */
2097    U8          CurrentModulation;          /* 0x01 */
2098    U8          CurrentUtilization;         /* 0x02 */
2099    U8          Reserved1;                  /* 0x03 */
2100    U32         Reserved2;                  /* 0x04 */
2101} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2102  MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2103  Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2104  MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2105
2106/* defines for CurrentStatus field */
2107#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2108#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2109#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2110#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2111#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2112#define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2113#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2114#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2115
2116/* defines for CurrentModulation field */
2117#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2118#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2119#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2120#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2121
2122/*
2123 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2124 * one and check the value returned for NumGroups at runtime.
2125 */
2126#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2127#define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2128#endif
2129
2130typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2131    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2132    U32                                 Reserved1;                  /* 0x08 */
2133    U32                                 Reserved2;                  /* 0x0C */
2134    U8                                  NumGroups;                  /* 0x10 */
2135    U8                                  Reserved3;                  /* 0x11 */
2136    U16                                 Reserved4;                  /* 0x12 */
2137    MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2138        PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2139} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2140  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2141  Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2142
2143#define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2144
2145
2146/* SAS IO Unit Page 7 */
2147
2148typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2149    U8          Flags;                      /* 0x00 */
2150    U8          Reserved1;                  /* 0x01 */
2151    U16         Reserved2;                  /* 0x02 */
2152    U8          Threshold75Pct;             /* 0x04 */
2153    U8          Threshold50Pct;             /* 0x05 */
2154    U8          Threshold25Pct;             /* 0x06 */
2155    U8          Reserved3;                  /* 0x07 */
2156} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2157  MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2158  Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2159  MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2160
2161/* defines for Flags field */
2162#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2163
2164
2165/*
2166 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2167 * one and check the value returned for NumGroups at runtime.
2168 */
2169#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2170#define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2171#endif
2172
2173typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2174    MPI2_CONFIG_EXTENDED_PAGE_HEADER            Header;             /* 0x00 */
2175    U8                                          SamplingInterval;   /* 0x08 */
2176    U8                                          WindowLength;       /* 0x09 */
2177    U16                                         Reserved1;          /* 0x0A */
2178    U32                                         Reserved2;          /* 0x0C */
2179    U32                                         Reserved3;          /* 0x10 */
2180    U8                                          NumGroups;          /* 0x14 */
2181    U8                                          Reserved4;          /* 0x15 */
2182    U16                                         Reserved5;          /* 0x16 */
2183    MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2184        PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2185} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2186  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2187  Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2188
2189#define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2190
2191
2192/* SAS IO Unit Page 8 */
2193
2194typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2195    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2196    U32                                 Reserved1;              /* 0x08 */
2197    U32                                 PowerManagementCapabilities;/* 0x0C */
2198    U32                                 Reserved2;              /* 0x10 */
2199} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2200  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2201  Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2202
2203#define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2204
2205/* defines for PowerManagementCapabilities field */
2206#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2207#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2208#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2209#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2210#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2211#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2212#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2213#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2214#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2215#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2216
2217
2218
2219
2220/****************************************************************************
2221*   SAS Expander Config Pages
2222****************************************************************************/
2223
2224/* SAS Expander Page 0 */
2225
2226typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2227{
2228    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2229    U8                                  PhysicalPort;               /* 0x08 */
2230    U8                                  ReportGenLength;            /* 0x09 */
2231    U16                                 EnclosureHandle;            /* 0x0A */
2232    U64                                 SASAddress;                 /* 0x0C */
2233    U32                                 DiscoveryStatus;            /* 0x14 */
2234    U16                                 DevHandle;                  /* 0x18 */
2235    U16                                 ParentDevHandle;            /* 0x1A */
2236    U16                                 ExpanderChangeCount;        /* 0x1C */
2237    U16                                 ExpanderRouteIndexes;       /* 0x1E */
2238    U8                                  NumPhys;                    /* 0x20 */
2239    U8                                  SASLevel;                   /* 0x21 */
2240    U16                                 Flags;                      /* 0x22 */
2241    U16                                 STPBusInactivityTimeLimit;  /* 0x24 */
2242    U16                                 STPMaxConnectTimeLimit;     /* 0x26 */
2243    U16                                 STP_SMP_NexusLossTime;      /* 0x28 */
2244    U16                                 MaxNumRoutedSasAddresses;   /* 0x2A */
2245    U64                                 ActiveZoneManagerSASAddress;/* 0x2C */
2246    U16                                 ZoneLockInactivityLimit;    /* 0x34 */
2247    U16                                 Reserved1;                  /* 0x36 */
2248    U8                                  TimeToReducedFunc;          /* 0x38 */
2249    U8                                  InitialTimeToReducedFunc;   /* 0x39 */
2250    U8                                  MaxReducedFuncTime;         /* 0x3A */
2251    U8                                  Reserved2;                  /* 0x3B */
2252} MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2253  Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2254
2255#define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2256
2257/* values for SAS Expander Page 0 DiscoveryStatus field */
2258#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2259#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2260#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2261#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2262#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2263#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2264#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2265#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2266#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2267#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2268#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2269#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2270#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2271#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2272#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2273#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2274#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2275#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2276#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2277#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2278
2279/* values for SAS Expander Page 0 Flags field */
2280#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2281#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2282#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2283#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2284#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2285#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2286#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2287#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2288#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2289#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2290#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2291
2292
2293/* SAS Expander Page 1 */
2294
2295typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2296{
2297    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2298    U8                                  PhysicalPort;               /* 0x08 */
2299    U8                                  Reserved1;                  /* 0x09 */
2300    U16                                 Reserved2;                  /* 0x0A */
2301    U8                                  NumPhys;                    /* 0x0C */
2302    U8                                  Phy;                        /* 0x0D */
2303    U16                                 NumTableEntriesProgrammed;  /* 0x0E */
2304    U8                                  ProgrammedLinkRate;         /* 0x10 */
2305    U8                                  HwLinkRate;                 /* 0x11 */
2306    U16                                 AttachedDevHandle;          /* 0x12 */
2307    U32                                 PhyInfo;                    /* 0x14 */
2308    U32                                 AttachedDeviceInfo;         /* 0x18 */
2309    U16                                 ExpanderDevHandle;          /* 0x1C */
2310    U8                                  ChangeCount;                /* 0x1E */
2311    U8                                  NegotiatedLinkRate;         /* 0x1F */
2312    U8                                  PhyIdentifier;              /* 0x20 */
2313    U8                                  AttachedPhyIdentifier;      /* 0x21 */
2314    U8                                  Reserved3;                  /* 0x22 */
2315    U8                                  DiscoveryInfo;              /* 0x23 */
2316    U32                                 AttachedPhyInfo;            /* 0x24 */
2317    U8                                  ZoneGroup;                  /* 0x28 */
2318    U8                                  SelfConfigStatus;           /* 0x29 */
2319    U16                                 Reserved4;                  /* 0x2A */
2320} MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2321  Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2322
2323#define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2324
2325/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2326
2327/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2328
2329/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2330
2331/* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2332
2333/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2334
2335/* values for SAS Expander Page 1 DiscoveryInfo field */
2336#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2337#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2338#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2339
2340/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2341
2342/****************************************************************************
2343*   SAS Device Config Pages
2344****************************************************************************/
2345
2346/* SAS Device Page 0 */
2347
2348typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2349{
2350    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2351    U16                                 Slot;                   /* 0x08 */
2352    U16                                 EnclosureHandle;        /* 0x0A */
2353    U64                                 SASAddress;             /* 0x0C */
2354    U16                                 ParentDevHandle;        /* 0x14 */
2355    U8                                  PhyNum;                 /* 0x16 */
2356    U8                                  AccessStatus;           /* 0x17 */
2357    U16                                 DevHandle;              /* 0x18 */
2358    U8                                  AttachedPhyIdentifier;  /* 0x1A */
2359    U8                                  ZoneGroup;              /* 0x1B */
2360    U32                                 DeviceInfo;             /* 0x1C */
2361    U16                                 Flags;                  /* 0x20 */
2362    U8                                  PhysicalPort;           /* 0x22 */
2363    U8                                  MaxPortConnections;     /* 0x23 */
2364    U64                                 DeviceName;             /* 0x24 */
2365    U8                                  PortGroups;             /* 0x2C */
2366    U8                                  DmaGroup;               /* 0x2D */
2367    U8                                  ControlGroup;           /* 0x2E */
2368    U8                                  Reserved1;              /* 0x2F */
2369    U32                                 Reserved2;              /* 0x30 */
2370    U32                                 Reserved3;              /* 0x34 */
2371} MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2372  Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2373
2374#define MPI2_SASDEVICE0_PAGEVERSION         (0x08)
2375
2376/* values for SAS Device Page 0 AccessStatus field */
2377#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2378#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2379#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2380#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2381#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2382#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2383#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2384#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2385/* specific values for SATA Init failures */
2386#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2387#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2388#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2389#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2390#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2391#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2392#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2393#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2394#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2395#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2396#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2397
2398/* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2399
2400/* values for SAS Device Page 0 Flags field */
2401#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2402#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2403#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2404#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2405#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2406#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2407#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2408#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2409#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2410#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2411#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2412#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2413
2414
2415/* SAS Device Page 1 */
2416
2417typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2418{
2419    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2420    U32                                 Reserved1;              /* 0x08 */
2421    U64                                 SASAddress;             /* 0x0C */
2422    U32                                 Reserved2;              /* 0x14 */
2423    U16                                 DevHandle;              /* 0x18 */
2424    U16                                 Reserved3;              /* 0x1A */
2425    U8                                  InitialRegDeviceFIS[20];/* 0x1C */
2426} MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2427  Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2428
2429#define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2430
2431
2432/****************************************************************************
2433*   SAS PHY Config Pages
2434****************************************************************************/
2435
2436/* SAS PHY Page 0 */
2437
2438typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2439{
2440    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2441    U16                                 OwnerDevHandle;         /* 0x08 */
2442    U16                                 Reserved1;              /* 0x0A */
2443    U16                                 AttachedDevHandle;      /* 0x0C */
2444    U8                                  AttachedPhyIdentifier;  /* 0x0E */
2445    U8                                  Reserved2;              /* 0x0F */
2446    U32                                 AttachedPhyInfo;        /* 0x10 */
2447    U8                                  ProgrammedLinkRate;     /* 0x14 */
2448    U8                                  HwLinkRate;             /* 0x15 */
2449    U8                                  ChangeCount;            /* 0x16 */
2450    U8                                  Flags;                  /* 0x17 */
2451    U32                                 PhyInfo;                /* 0x18 */
2452    U8                                  NegotiatedLinkRate;     /* 0x1C */
2453    U8                                  Reserved3;              /* 0x1D */
2454    U16                                 Reserved4;              /* 0x1E */
2455} MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2456  Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2457
2458#define MPI2_SASPHY0_PAGEVERSION            (0x03)
2459
2460/* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2461
2462/* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2463
2464/* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2465
2466/* values for SAS PHY Page 0 Flags field */
2467#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
2468
2469/* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2470
2471/* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2472
2473
2474/* SAS PHY Page 1 */
2475
2476typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2477{
2478    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2479    U32                                 Reserved1;                  /* 0x08 */
2480    U32                                 InvalidDwordCount;          /* 0x0C */
2481    U32                                 RunningDisparityErrorCount; /* 0x10 */
2482    U32                                 LossDwordSynchCount;        /* 0x14 */
2483    U32                                 PhyResetProblemCount;       /* 0x18 */
2484} MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2485  Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2486
2487#define MPI2_SASPHY1_PAGEVERSION            (0x01)
2488
2489
2490/* SAS PHY Page 2 */
2491
2492typedef struct _MPI2_SASPHY2_PHY_EVENT {
2493    U8          PhyEventCode;       /* 0x00 */
2494    U8          Reserved1;          /* 0x01 */
2495    U16         Reserved2;          /* 0x02 */
2496    U32         PhyEventInfo;       /* 0x04 */
2497} MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2498  Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2499
2500/* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2501
2502
2503/*
2504 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2505 * one and check the value returned for NumPhyEvents at runtime.
2506 */
2507#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2508#define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
2509#endif
2510
2511typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2512    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2513    U32                                 Reserved1;                  /* 0x08 */
2514    U8                                  NumPhyEvents;               /* 0x0C */
2515    U8                                  Reserved2;                  /* 0x0D */
2516    U16                                 Reserved3;                  /* 0x0E */
2517    MPI2_SASPHY2_PHY_EVENT              PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2518                                                                /* 0x10 */
2519} MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2520  Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2521
2522#define MPI2_SASPHY2_PAGEVERSION            (0x00)
2523
2524
2525/* SAS PHY Page 3 */
2526
2527typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2528    U8          PhyEventCode;       /* 0x00 */
2529    U8          Reserved1;          /* 0x01 */
2530    U16         Reserved2;          /* 0x02 */
2531    U8          CounterType;        /* 0x04 */
2532    U8          ThresholdWindow;    /* 0x05 */
2533    U8          TimeUnits;          /* 0x06 */
2534    U8          Reserved3;          /* 0x07 */
2535    U32         EventThreshold;     /* 0x08 */
2536    U16         ThresholdFlags;     /* 0x0C */
2537    U16         Reserved4;          /* 0x0E */
2538} MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2539  Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2540
2541/* values for PhyEventCode field */
2542#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
2543#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
2544#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
2545#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
2546#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
2547#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
2548#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
2549#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
2550#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
2551#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
2552#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
2553#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
2554#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
2555#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
2556#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
2557#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
2558#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
2559#define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
2560#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
2561#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
2562#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
2563#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
2564#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
2565#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
2566#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
2567#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
2568#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
2569#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
2570#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
2571#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
2572#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
2573#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
2574#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
2575#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
2576#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
2577#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
2578#define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
2579
2580/* values for the CounterType field */
2581#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
2582#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
2583#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
2584
2585/* values for the TimeUnits field */
2586#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
2587#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
2588#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
2589#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
2590
2591/* values for the ThresholdFlags field */
2592#define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
2593#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
2594
2595/*
2596 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2597 * one and check the value returned for NumPhyEvents at runtime.
2598 */
2599#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2600#define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
2601#endif
2602
2603typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2604    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2605    U32                                 Reserved1;                  /* 0x08 */
2606    U8                                  NumPhyEvents;               /* 0x0C */
2607    U8                                  Reserved2;                  /* 0x0D */
2608    U16                                 Reserved3;                  /* 0x0E */
2609    MPI2_SASPHY3_PHY_EVENT_CONFIG       PhyEventConfig
2610                                        [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2611} MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2612  Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2613
2614#define MPI2_SASPHY3_PAGEVERSION            (0x00)
2615
2616
2617/* SAS PHY Page 4 */
2618
2619typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2620    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2621    U16                                 Reserved1;                  /* 0x08 */
2622    U8                                  Reserved2;                  /* 0x0A */
2623    U8                                  Flags;                      /* 0x0B */
2624    U8                                  InitialFrame[28];           /* 0x0C */
2625} MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2626  Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2627
2628#define MPI2_SASPHY4_PAGEVERSION            (0x00)
2629
2630/* values for the Flags field */
2631#define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
2632#define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
2633
2634
2635
2636
2637/****************************************************************************
2638*   SAS Port Config Pages
2639****************************************************************************/
2640
2641/* SAS Port Page 0 */
2642
2643typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2644{
2645    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2646    U8                                  PortNumber;                 /* 0x08 */
2647    U8                                  PhysicalPort;               /* 0x09 */
2648    U8                                  PortWidth;                  /* 0x0A */
2649    U8                                  PhysicalPortWidth;          /* 0x0B */
2650    U8                                  ZoneGroup;                  /* 0x0C */
2651    U8                                  Reserved1;                  /* 0x0D */
2652    U16                                 Reserved2;                  /* 0x0E */
2653    U64                                 SASAddress;                 /* 0x10 */
2654    U32                                 DeviceInfo;                 /* 0x18 */
2655    U32                                 Reserved3;                  /* 0x1C */
2656    U32                                 Reserved4;                  /* 0x20 */
2657} MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2658  Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2659
2660#define MPI2_SASPORT0_PAGEVERSION           (0x00)
2661
2662/* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2663
2664
2665/****************************************************************************
2666*   SAS Enclosure Config Pages
2667****************************************************************************/
2668
2669/* SAS Enclosure Page 0 */
2670
2671typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2672{
2673    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2674    U32                                 Reserved1;                  /* 0x08 */
2675    U64                                 EnclosureLogicalID;         /* 0x0C */
2676    U16                                 Flags;                      /* 0x14 */
2677    U16                                 EnclosureHandle;            /* 0x16 */
2678    U16                                 NumSlots;                   /* 0x18 */
2679    U16                                 StartSlot;                  /* 0x1A */
2680    U16                                 Reserved2;                  /* 0x1C */
2681    U16                                 SEPDevHandle;               /* 0x1E */
2682    U32                                 Reserved3;                  /* 0x20 */
2683    U32                                 Reserved4;                  /* 0x24 */
2684} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2685  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2686  Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2687
2688#define MPI2_SASENCLOSURE0_PAGEVERSION      (0x03)
2689
2690/* values for SAS Enclosure Page 0 Flags field */
2691#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
2692#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
2693#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
2694#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
2695#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
2696#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
2697#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
2698
2699
2700/****************************************************************************
2701*   Log Config Page
2702****************************************************************************/
2703
2704/* Log Page 0 */
2705
2706/*
2707 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2708 * one and check the value returned for NumLogEntries at runtime.
2709 */
2710#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2711#define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
2712#endif
2713
2714#define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
2715
2716typedef struct _MPI2_LOG_0_ENTRY
2717{
2718    U64         TimeStamp;                          /* 0x00 */
2719    U32         Reserved1;                          /* 0x08 */
2720    U16         LogSequence;                        /* 0x0C */
2721    U16         LogEntryQualifier;                  /* 0x0E */
2722    U8          VP_ID;                              /* 0x10 */
2723    U8          VF_ID;                              /* 0x11 */
2724    U16         Reserved2;                          /* 0x12 */
2725    U8          LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2726} MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2727  Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2728
2729/* values for Log Page 0 LogEntry LogEntryQualifier field */
2730#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
2731#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
2732#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
2733#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
2734#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
2735
2736typedef struct _MPI2_CONFIG_PAGE_LOG_0
2737{
2738    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2739    U32                                 Reserved1;                  /* 0x08 */
2740    U32                                 Reserved2;                  /* 0x0C */
2741    U16                                 NumLogEntries;              /* 0x10 */
2742    U16                                 Reserved3;                  /* 0x12 */
2743    MPI2_LOG_0_ENTRY                    LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2744} MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2745  Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2746
2747#define MPI2_LOG_0_PAGEVERSION              (0x02)
2748
2749
2750/****************************************************************************
2751*   RAID Config Page
2752****************************************************************************/
2753
2754/* RAID Page 0 */
2755
2756/*
2757 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2758 * one and check the value returned for NumElements at runtime.
2759 */
2760#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2761#define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
2762#endif
2763
2764typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2765{
2766    U16                     ElementFlags;               /* 0x00 */
2767    U16                     VolDevHandle;               /* 0x02 */
2768    U8                      HotSparePool;               /* 0x04 */
2769    U8                      PhysDiskNum;                /* 0x05 */
2770    U16                     PhysDiskDevHandle;          /* 0x06 */
2771} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2772  MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2773  Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2774
2775/* values for the ElementFlags field */
2776#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
2777#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
2778#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
2779#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
2780#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
2781
2782
2783typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2784{
2785    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2786    U8                                  NumHotSpares;               /* 0x08 */
2787    U8                                  NumPhysDisks;               /* 0x09 */
2788    U8                                  NumVolumes;                 /* 0x0A */
2789    U8                                  ConfigNum;                  /* 0x0B */
2790    U32                                 Flags;                      /* 0x0C */
2791    U8                                  ConfigGUID[24];             /* 0x10 */
2792    U32                                 Reserved1;                  /* 0x28 */
2793    U8                                  NumElements;                /* 0x2C */
2794    U8                                  Reserved2;                  /* 0x2D */
2795    U16                                 Reserved3;                  /* 0x2E */
2796    MPI2_RAIDCONFIG0_CONFIG_ELEMENT     ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2797} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2798  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2799  Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2800
2801#define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
2802
2803/* values for RAID Configuration Page 0 Flags field */
2804#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
2805
2806
2807/****************************************************************************
2808*   Driver Persistent Mapping Config Pages
2809****************************************************************************/
2810
2811/* Driver Persistent Mapping Page 0 */
2812
2813typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2814{
2815    U64                                 PhysicalIdentifier;         /* 0x00 */
2816    U16                                 MappingInformation;         /* 0x08 */
2817    U16                                 DeviceIndex;                /* 0x0A */
2818    U32                                 PhysicalBitsMapping;        /* 0x0C */
2819    U32                                 Reserved1;                  /* 0x10 */
2820} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2821  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2822  Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2823
2824typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2825{
2826    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
2827    MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;                      /* 0x08 */
2828} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2829  MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2830  Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2831
2832#define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
2833
2834/* values for Driver Persistent Mapping Page 0 MappingInformation field */
2835#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
2836#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
2837#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
2838
2839
2840/****************************************************************************
2841*   Ethernet Config Pages
2842****************************************************************************/
2843
2844/* Ethernet Page 0 */
2845
2846/* IP address (union of IPv4 and IPv6) */
2847typedef union _MPI2_ETHERNET_IP_ADDR {
2848    U32     IPv4Addr;
2849    U32     IPv6Addr[4];
2850} MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2851  Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2852
2853#define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
2854
2855typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2856    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2857    U8                                  NumInterfaces;          /* 0x08 */
2858    U8                                  Reserved0;              /* 0x09 */
2859    U16                                 Reserved1;              /* 0x0A */
2860    U32                                 Status;                 /* 0x0C */
2861    U8                                  MediaState;             /* 0x10 */
2862    U8                                  Reserved2;              /* 0x11 */
2863    U16                                 Reserved3;              /* 0x12 */
2864    U8                                  MacAddress[6];          /* 0x14 */
2865    U8                                  Reserved4;              /* 0x1A */
2866    U8                                  Reserved5;              /* 0x1B */
2867    MPI2_ETHERNET_IP_ADDR               IpAddress;              /* 0x1C */
2868    MPI2_ETHERNET_IP_ADDR               SubnetMask;             /* 0x2C */
2869    MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;       /* 0x3C */
2870    MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;          /* 0x4C */
2871    MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;          /* 0x5C */
2872    MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;          /* 0x6C */
2873    U8                                  HostName
2874                                [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2875} MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2876  Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2877
2878#define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
2879
2880/* values for Ethernet Page 0 Status field */
2881#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
2882#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
2883#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
2884#define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
2885#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
2886#define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
2887#define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
2888#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
2889#define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
2890#define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
2891#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
2892#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
2893
2894/* values for Ethernet Page 0 MediaState field */
2895#define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
2896#define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
2897#define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
2898
2899#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
2900#define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
2901#define MPI2_ETHPG0_MS_10MBIT                       (0x01)
2902#define MPI2_ETHPG0_MS_100MBIT                      (0x02)
2903#define MPI2_ETHPG0_MS_1GBIT                        (0x03)
2904
2905
2906/* Ethernet Page 1 */
2907
2908typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2909    MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2910    U32                                 Reserved0;              /* 0x08 */
2911    U32                                 Flags;                  /* 0x0C */
2912    U8                                  MediaState;             /* 0x10 */
2913    U8                                  Reserved1;              /* 0x11 */
2914    U16                                 Reserved2;              /* 0x12 */
2915    U8                                  MacAddress[6];          /* 0x14 */
2916    U8                                  Reserved3;              /* 0x1A */
2917    U8                                  Reserved4;              /* 0x1B */
2918    MPI2_ETHERNET_IP_ADDR               StaticIpAddress;        /* 0x1C */
2919    MPI2_ETHERNET_IP_ADDR               StaticSubnetMask;       /* 0x2C */
2920    MPI2_ETHERNET_IP_ADDR               StaticGatewayIpAddress; /* 0x3C */
2921    MPI2_ETHERNET_IP_ADDR               StaticDNS1IpAddress;    /* 0x4C */
2922    MPI2_ETHERNET_IP_ADDR               StaticDNS2IpAddress;    /* 0x5C */
2923    U32                                 Reserved5;              /* 0x6C */
2924    U32                                 Reserved6;              /* 0x70 */
2925    U32                                 Reserved7;              /* 0x74 */
2926    U32                                 Reserved8;              /* 0x78 */
2927    U8                                  HostName
2928                                [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2929} MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2930  Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2931
2932#define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
2933
2934/* values for Ethernet Page 1 Flags field */
2935#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
2936#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
2937#define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
2938#define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
2939#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
2940#define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
2941#define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
2942#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
2943#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
2944
2945/* values for Ethernet Page 1 MediaState field */
2946#define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
2947#define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
2948#define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
2949
2950#define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
2951#define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
2952#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
2953#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
2954#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
2955
2956
2957/****************************************************************************
2958*   Extended Manufacturing Config Pages
2959****************************************************************************/
2960
2961/*
2962 * Generic structure to use for product-specific extended manufacturing pages
2963 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
2964 * Page 60).
2965 */
2966
2967typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
2968        MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
2969        U32                                 ProductSpecificInfo;    /* 0x08 */
2970}       MPI2_CONFIG_PAGE_EXT_MAN_PS,
2971        MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
2972        Mpi2ExtManufacturingPagePS_t,
2973        MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
2974
2975/* PageVersion should be provided by product-specific code */
2976
2977#endif
2978
2979