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9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/sysfs.h>
13#include <linux/i2c.h>
14#include <linux/regulator/consumer.h>
15#include <linux/slab.h>
16#include <linux/types.h>
17#include <linux/err.h>
18#include <linux/delay.h>
19#include <linux/module.h>
20#include <asm/div64.h>
21
22#include "../iio.h"
23#include "../sysfs.h"
24#include "../buffer.h"
25#include "../ring_sw.h"
26
27#include "ad5933.h"
28
29
30#define AD5933_REG_CONTROL_HB 0x80
31#define AD5933_REG_CONTROL_LB 0x81
32#define AD5933_REG_FREQ_START 0x82
33#define AD5933_REG_FREQ_INC 0x85
34#define AD5933_REG_INC_NUM 0x88
35#define AD5933_REG_SETTLING_CYCLES 0x8A
36#define AD5933_REG_STATUS 0x8F
37#define AD5933_REG_TEMP_DATA 0x92
38#define AD5933_REG_REAL_DATA 0x94
39#define AD5933_REG_IMAG_DATA 0x96
40
41
42#define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
43#define AD5933_CTRL_START_SWEEP (0x2 << 4)
44#define AD5933_CTRL_INC_FREQ (0x3 << 4)
45#define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
46#define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
47#define AD5933_CTRL_POWER_DOWN (0xA << 4)
48#define AD5933_CTRL_STANDBY (0xB << 4)
49
50#define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
51#define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
52#define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
53#define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
54#define AD5933_CTRL_RANGE(x) ((x) << 1)
55
56#define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
57#define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
58
59
60#define AD5933_CTRL_RESET (0x1 << 4)
61#define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
62#define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
63
64
65#define AD5933_STAT_TEMP_VALID (0x1 << 0)
66#define AD5933_STAT_DATA_VALID (0x1 << 1)
67#define AD5933_STAT_SWEEP_DONE (0x1 << 2)
68
69
70#define AD5933_I2C_BLOCK_WRITE 0xA0
71#define AD5933_I2C_BLOCK_READ 0xA1
72#define AD5933_I2C_ADDR_POINTER 0xB0
73
74
75#define AD5933_INT_OSC_FREQ_Hz 16776000
76#define AD5933_MAX_OUTPUT_FREQ_Hz 100000
77#define AD5933_MAX_RETRIES 100
78
79#define AD5933_OUT_RANGE 1
80#define AD5933_OUT_RANGE_AVAIL 2
81#define AD5933_OUT_SETTLING_CYCLES 3
82#define AD5933_IN_PGA_GAIN 4
83#define AD5933_IN_PGA_GAIN_AVAIL 5
84#define AD5933_FREQ_POINTS 6
85
86#define AD5933_POLL_TIME_ms 10
87#define AD5933_INIT_EXCITATION_TIME_ms 100
88
89struct ad5933_state {
90 struct i2c_client *client;
91 struct regulator *reg;
92 struct ad5933_platform_data *pdata;
93 struct delayed_work work;
94 unsigned long mclk_hz;
95 unsigned char ctrl_hb;
96 unsigned char ctrl_lb;
97 unsigned range_avail[4];
98 unsigned short vref_mv;
99 unsigned short settling_cycles;
100 unsigned short freq_points;
101 unsigned freq_start;
102 unsigned freq_inc;
103 unsigned state;
104 unsigned poll_time_jiffies;
105};
106
107static struct ad5933_platform_data ad5933_default_pdata = {
108 .vref_mv = 3300,
109};
110
111static struct iio_chan_spec ad5933_channels[] = {
112 IIO_CHAN(IIO_TEMP, 0, 1, 1, NULL, 0, 0, 0,
113 0, AD5933_REG_TEMP_DATA, IIO_ST('s', 14, 16, 0), 0),
114
115 IIO_CHAN(IIO_VOLTAGE, 0, 1, 0, "real_raw", 0, 0,
116 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
117 AD5933_REG_REAL_DATA, 0, IIO_ST('s', 16, 16, 0), 0),
118 IIO_CHAN(IIO_VOLTAGE, 0, 1, 0, "imag_raw", 0, 0,
119 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
120 AD5933_REG_IMAG_DATA, 1, IIO_ST('s', 16, 16, 0), 0),
121};
122
123static int ad5933_i2c_write(struct i2c_client *client,
124 u8 reg, u8 len, u8 *data)
125{
126 int ret;
127
128 while (len--) {
129 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
130 if (ret < 0) {
131 dev_err(&client->dev, "I2C write error\n");
132 return ret;
133 }
134 }
135 return 0;
136}
137
138static int ad5933_i2c_read(struct i2c_client *client,
139 u8 reg, u8 len, u8 *data)
140{
141 int ret;
142
143 while (len--) {
144 ret = i2c_smbus_read_byte_data(client, reg++);
145 if (ret < 0) {
146 dev_err(&client->dev, "I2C read error\n");
147 return ret;
148 }
149 *data++ = ret;
150 }
151 return 0;
152}
153
154static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
155{
156 unsigned char dat = st->ctrl_hb | cmd;
157
158 return ad5933_i2c_write(st->client,
159 AD5933_REG_CONTROL_HB, 1, &dat);
160}
161
162static int ad5933_reset(struct ad5933_state *st)
163{
164 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
165 return ad5933_i2c_write(st->client,
166 AD5933_REG_CONTROL_LB, 1, &dat);
167}
168
169static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
170{
171 unsigned char val, timeout = AD5933_MAX_RETRIES;
172 int ret;
173
174 while (timeout--) {
175 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
176 if (ret < 0)
177 return ret;
178 if (val & event)
179 return val;
180 cpu_relax();
181 mdelay(1);
182 }
183
184 return -EAGAIN;
185}
186
187static int ad5933_set_freq(struct ad5933_state *st,
188 unsigned reg, unsigned long freq)
189{
190 unsigned long long freqreg;
191 union {
192 u32 d32;
193 u8 d8[4];
194 } dat;
195
196 freqreg = (u64) freq * (u64) (1 << 27);
197 do_div(freqreg, st->mclk_hz / 4);
198
199 switch (reg) {
200 case AD5933_REG_FREQ_START:
201 st->freq_start = freq;
202 break;
203 case AD5933_REG_FREQ_INC:
204 st->freq_inc = freq;
205 break;
206 default:
207 return -EINVAL;
208 }
209
210 dat.d32 = cpu_to_be32(freqreg);
211 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
212}
213
214static int ad5933_setup(struct ad5933_state *st)
215{
216 unsigned short dat;
217 int ret;
218
219 ret = ad5933_reset(st);
220 if (ret < 0)
221 return ret;
222
223 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
224 if (ret < 0)
225 return ret;
226
227 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
228 if (ret < 0)
229 return ret;
230
231 st->settling_cycles = 10;
232 dat = cpu_to_be16(st->settling_cycles);
233
234 ret = ad5933_i2c_write(st->client,
235 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
236 if (ret < 0)
237 return ret;
238
239 st->freq_points = 100;
240 dat = cpu_to_be16(st->freq_points);
241
242 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
243}
244
245static void ad5933_calc_out_ranges(struct ad5933_state *st)
246{
247 int i;
248 unsigned normalized_3v3[4] = {1980, 198, 383, 970};
249
250 for (i = 0; i < 4; i++)
251 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
252
253}
254
255
256
257
258
259static ssize_t ad5933_show_frequency(struct device *dev,
260 struct device_attribute *attr,
261 char *buf)
262{
263 struct iio_dev *indio_dev = dev_get_drvdata(dev);
264 struct ad5933_state *st = iio_priv(indio_dev);
265 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
266 int ret;
267 unsigned long long freqreg;
268 union {
269 u32 d32;
270 u8 d8[4];
271 } dat;
272
273 mutex_lock(&indio_dev->mlock);
274 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
275 mutex_unlock(&indio_dev->mlock);
276 if (ret < 0)
277 return ret;
278
279 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
280
281 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4);
282 do_div(freqreg, 1 << 27);
283
284 return sprintf(buf, "%d\n", (int) freqreg);
285}
286
287static ssize_t ad5933_store_frequency(struct device *dev,
288 struct device_attribute *attr,
289 const char *buf,
290 size_t len)
291{
292 struct iio_dev *indio_dev = dev_get_drvdata(dev);
293 struct ad5933_state *st = iio_priv(indio_dev);
294 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
295 long val;
296 int ret;
297
298 ret = strict_strtoul(buf, 10, &val);
299 if (ret)
300 return ret;
301
302 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
303 return -EINVAL;
304
305 mutex_lock(&indio_dev->mlock);
306 ret = ad5933_set_freq(st, this_attr->address, val);
307 mutex_unlock(&indio_dev->mlock);
308
309 return ret ? ret : len;
310}
311
312static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR,
313 ad5933_show_frequency,
314 ad5933_store_frequency,
315 AD5933_REG_FREQ_START);
316
317static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR,
318 ad5933_show_frequency,
319 ad5933_store_frequency,
320 AD5933_REG_FREQ_INC);
321
322static ssize_t ad5933_show(struct device *dev,
323 struct device_attribute *attr,
324 char *buf)
325{
326 struct iio_dev *indio_dev = dev_get_drvdata(dev);
327 struct ad5933_state *st = iio_priv(indio_dev);
328 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
329 int ret = 0, len = 0;
330
331 mutex_lock(&indio_dev->mlock);
332 switch ((u32) this_attr->address) {
333 case AD5933_OUT_RANGE:
334 len = sprintf(buf, "%d\n",
335 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
336 break;
337 case AD5933_OUT_RANGE_AVAIL:
338 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0],
339 st->range_avail[3], st->range_avail[2],
340 st->range_avail[1]);
341 break;
342 case AD5933_OUT_SETTLING_CYCLES:
343 len = sprintf(buf, "%d\n", st->settling_cycles);
344 break;
345 case AD5933_IN_PGA_GAIN:
346 len = sprintf(buf, "%s\n",
347 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
348 "1" : "0.2");
349 break;
350 case AD5933_IN_PGA_GAIN_AVAIL:
351 len = sprintf(buf, "1 0.2\n");
352 break;
353 case AD5933_FREQ_POINTS:
354 len = sprintf(buf, "%d\n", st->freq_points);
355 break;
356 default:
357 ret = -EINVAL;
358 }
359
360 mutex_unlock(&indio_dev->mlock);
361 return ret ? ret : len;
362}
363
364static ssize_t ad5933_store(struct device *dev,
365 struct device_attribute *attr,
366 const char *buf,
367 size_t len)
368{
369 struct iio_dev *indio_dev = dev_get_drvdata(dev);
370 struct ad5933_state *st = iio_priv(indio_dev);
371 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
372 long val;
373 int i, ret = 0;
374 unsigned short dat;
375
376 if (this_attr->address != AD5933_IN_PGA_GAIN) {
377 ret = strict_strtol(buf, 10, &val);
378 if (ret)
379 return ret;
380 }
381
382 mutex_lock(&indio_dev->mlock);
383 switch ((u32) this_attr->address) {
384 case AD5933_OUT_RANGE:
385 for (i = 0; i < 4; i++)
386 if (val == st->range_avail[i]) {
387 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
388 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
389 ret = ad5933_cmd(st, 0);
390 break;
391 }
392 ret = -EINVAL;
393 break;
394 case AD5933_IN_PGA_GAIN:
395 if (sysfs_streq(buf, "1")) {
396 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
397 } else if (sysfs_streq(buf, "0.2")) {
398 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
399 } else {
400 ret = -EINVAL;
401 break;
402 }
403 ret = ad5933_cmd(st, 0);
404 break;
405 case AD5933_OUT_SETTLING_CYCLES:
406 val = clamp(val, 0L, 0x7FFL);
407 st->settling_cycles = val;
408
409
410 if (val > 511)
411 val = (val >> 1) | (1 << 9);
412 else if (val > 1022)
413 val = (val >> 2) | (3 << 9);
414
415 dat = cpu_to_be16(val);
416 ret = ad5933_i2c_write(st->client,
417 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
418 break;
419 case AD5933_FREQ_POINTS:
420 val = clamp(val, 0L, 511L);
421 st->freq_points = val;
422
423 dat = cpu_to_be16(val);
424 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
425 (u8 *)&dat);
426 break;
427 default:
428 ret = -EINVAL;
429 }
430
431 mutex_unlock(&indio_dev->mlock);
432 return ret ? ret : len;
433}
434
435static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR,
436 ad5933_show,
437 ad5933_store,
438 AD5933_OUT_RANGE);
439
440static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO,
441 ad5933_show,
442 NULL,
443 AD5933_OUT_RANGE_AVAIL);
444
445static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR,
446 ad5933_show,
447 ad5933_store,
448 AD5933_IN_PGA_GAIN);
449
450static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
451 ad5933_show,
452 NULL,
453 AD5933_IN_PGA_GAIN_AVAIL);
454
455static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR,
456 ad5933_show,
457 ad5933_store,
458 AD5933_FREQ_POINTS);
459
460static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR,
461 ad5933_show,
462 ad5933_store,
463 AD5933_OUT_SETTLING_CYCLES);
464
465
466
467
468
469
470static struct attribute *ad5933_attributes[] = {
471 &iio_dev_attr_out_voltage0_scale.dev_attr.attr,
472 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr,
473 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr,
474 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr,
475 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr,
476 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr,
477 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
478 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
479 NULL
480};
481
482static const struct attribute_group ad5933_attribute_group = {
483 .attrs = ad5933_attributes,
484};
485
486static int ad5933_read_raw(struct iio_dev *indio_dev,
487 struct iio_chan_spec const *chan,
488 int *val,
489 int *val2,
490 long m)
491{
492 struct ad5933_state *st = iio_priv(indio_dev);
493 unsigned short dat;
494 int ret = -EINVAL;
495
496 mutex_lock(&indio_dev->mlock);
497 switch (m) {
498 case 0:
499 if (iio_buffer_enabled(indio_dev)) {
500 ret = -EBUSY;
501 goto out;
502 }
503 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
504 if (ret < 0)
505 goto out;
506 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
507 if (ret < 0)
508 goto out;
509
510 ret = ad5933_i2c_read(st->client,
511 AD5933_REG_TEMP_DATA, 2,
512 (u8 *)&dat);
513 if (ret < 0)
514 goto out;
515 mutex_unlock(&indio_dev->mlock);
516 ret = be16_to_cpu(dat);
517
518 if (ret < 8192)
519 *val = ret * 1000 / 32;
520 else
521 *val = (ret - 16384) * 1000 / 32;
522
523 return IIO_VAL_INT;
524 }
525
526out:
527 mutex_unlock(&indio_dev->mlock);
528 return ret;
529}
530
531static const struct iio_info ad5933_info = {
532 .read_raw = &ad5933_read_raw,
533 .attrs = &ad5933_attribute_group,
534 .driver_module = THIS_MODULE,
535};
536
537static int ad5933_ring_preenable(struct iio_dev *indio_dev)
538{
539 struct ad5933_state *st = iio_priv(indio_dev);
540 size_t d_size;
541 int ret;
542
543 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
544 return -EINVAL;
545
546 d_size = bitmap_weight(indio_dev->active_scan_mask,
547 indio_dev->masklength) *
548 ad5933_channels[1].scan_type.storagebits / 8;
549
550 if (indio_dev->buffer->access->set_bytes_per_datum)
551 indio_dev->buffer->access->
552 set_bytes_per_datum(indio_dev->buffer, d_size);
553
554 ret = ad5933_reset(st);
555 if (ret < 0)
556 return ret;
557
558 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
559 if (ret < 0)
560 return ret;
561
562 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
563 if (ret < 0)
564 return ret;
565
566 st->state = AD5933_CTRL_INIT_START_FREQ;
567
568 return 0;
569}
570
571static int ad5933_ring_postenable(struct iio_dev *indio_dev)
572{
573 struct ad5933_state *st = iio_priv(indio_dev);
574
575
576
577
578
579
580
581
582
583
584
585 schedule_delayed_work(&st->work,
586 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
587 return 0;
588}
589
590static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
591{
592 struct ad5933_state *st = iio_priv(indio_dev);
593
594 cancel_delayed_work_sync(&st->work);
595 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
596}
597
598static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
599 .preenable = &ad5933_ring_preenable,
600 .postenable = &ad5933_ring_postenable,
601 .postdisable = &ad5933_ring_postdisable,
602};
603
604static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
605{
606 indio_dev->buffer = iio_sw_rb_allocate(indio_dev);
607 if (!indio_dev->buffer)
608 return -ENOMEM;
609
610
611 indio_dev->buffer->access = &ring_sw_access_funcs;
612
613
614 indio_dev->setup_ops = &ad5933_ring_setup_ops;
615
616 indio_dev->modes |= INDIO_BUFFER_HARDWARE;
617
618 return 0;
619}
620
621static void ad5933_work(struct work_struct *work)
622{
623 struct ad5933_state *st = container_of(work,
624 struct ad5933_state, work.work);
625 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
626 struct iio_buffer *ring = indio_dev->buffer;
627 signed short buf[2];
628 unsigned char status;
629
630 mutex_lock(&indio_dev->mlock);
631 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
632
633 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
634 st->state = AD5933_CTRL_START_SWEEP;
635 schedule_delayed_work(&st->work, st->poll_time_jiffies);
636 mutex_unlock(&indio_dev->mlock);
637 return;
638 }
639
640 ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
641
642 if (status & AD5933_STAT_DATA_VALID) {
643 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
644 indio_dev->masklength);
645 ad5933_i2c_read(st->client,
646 test_bit(1, indio_dev->active_scan_mask) ?
647 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
648 scan_count * 2, (u8 *)buf);
649
650 if (scan_count == 2) {
651 buf[0] = be16_to_cpu(buf[0]);
652 buf[1] = be16_to_cpu(buf[1]);
653 } else {
654 buf[0] = be16_to_cpu(buf[0]);
655 }
656
657 ring->access->store_to(ring, (u8 *)buf, iio_get_time_ns());
658 } else {
659
660 schedule_delayed_work(&st->work, st->poll_time_jiffies);
661 mutex_unlock(&indio_dev->mlock);
662 return;
663 }
664
665 if (status & AD5933_STAT_SWEEP_DONE) {
666
667
668 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
669 } else {
670
671 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
672 schedule_delayed_work(&st->work, st->poll_time_jiffies);
673 }
674
675 mutex_unlock(&indio_dev->mlock);
676}
677
678static int __devinit ad5933_probe(struct i2c_client *client,
679 const struct i2c_device_id *id)
680{
681 int ret, voltage_uv = 0;
682 struct ad5933_platform_data *pdata = client->dev.platform_data;
683 struct ad5933_state *st;
684 struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
685 if (indio_dev == NULL)
686 return -ENOMEM;
687
688 st = iio_priv(indio_dev);
689 i2c_set_clientdata(client, indio_dev);
690 st->client = client;
691
692 if (!pdata)
693 st->pdata = &ad5933_default_pdata;
694 else
695 st->pdata = pdata;
696
697 st->reg = regulator_get(&client->dev, "vcc");
698 if (!IS_ERR(st->reg)) {
699 ret = regulator_enable(st->reg);
700 if (ret)
701 goto error_put_reg;
702 voltage_uv = regulator_get_voltage(st->reg);
703 }
704
705 if (voltage_uv)
706 st->vref_mv = voltage_uv / 1000;
707 else
708 st->vref_mv = st->pdata->vref_mv;
709
710 if (st->pdata->ext_clk_Hz) {
711 st->mclk_hz = st->pdata->ext_clk_Hz;
712 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
713 } else {
714 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
715 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
716 }
717
718 ad5933_calc_out_ranges(st);
719 INIT_DELAYED_WORK(&st->work, ad5933_work);
720 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
721
722 indio_dev->dev.parent = &client->dev;
723 indio_dev->info = &ad5933_info;
724 indio_dev->name = id->name;
725 indio_dev->modes = INDIO_DIRECT_MODE;
726 indio_dev->channels = ad5933_channels;
727 indio_dev->num_channels = 1;
728
729 ret = ad5933_register_ring_funcs_and_init(indio_dev);
730 if (ret)
731 goto error_disable_reg;
732
733
734 ret = iio_buffer_register(indio_dev, &ad5933_channels[1], 2);
735 if (ret)
736 goto error_unreg_ring;
737
738
739 iio_scan_mask_set(indio_dev, indio_dev->buffer, 0);
740 iio_scan_mask_set(indio_dev, indio_dev->buffer, 1);
741
742 ret = ad5933_setup(st);
743 if (ret)
744 goto error_uninitialize_ring;
745
746 ret = iio_device_register(indio_dev);
747 if (ret)
748 goto error_uninitialize_ring;
749
750 return 0;
751
752error_uninitialize_ring:
753 iio_buffer_unregister(indio_dev);
754error_unreg_ring:
755 iio_sw_rb_free(indio_dev->buffer);
756error_disable_reg:
757 if (!IS_ERR(st->reg))
758 regulator_disable(st->reg);
759error_put_reg:
760 if (!IS_ERR(st->reg))
761 regulator_put(st->reg);
762
763 iio_free_device(indio_dev);
764
765 return ret;
766}
767
768static __devexit int ad5933_remove(struct i2c_client *client)
769{
770 struct iio_dev *indio_dev = i2c_get_clientdata(client);
771 struct ad5933_state *st = iio_priv(indio_dev);
772
773 iio_device_unregister(indio_dev);
774 iio_buffer_unregister(indio_dev);
775 iio_sw_rb_free(indio_dev->buffer);
776 if (!IS_ERR(st->reg)) {
777 regulator_disable(st->reg);
778 regulator_put(st->reg);
779 }
780 iio_free_device(indio_dev);
781
782 return 0;
783}
784
785static const struct i2c_device_id ad5933_id[] = {
786 { "ad5933", 0 },
787 { "ad5934", 0 },
788 {}
789};
790
791MODULE_DEVICE_TABLE(i2c, ad5933_id);
792
793static struct i2c_driver ad5933_driver = {
794 .driver = {
795 .name = "ad5933",
796 },
797 .probe = ad5933_probe,
798 .remove = __devexit_p(ad5933_remove),
799 .id_table = ad5933_id,
800};
801module_i2c_driver(ad5933_driver);
802
803MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
804MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
805MODULE_LICENSE("GPL v2");
806
