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9#include <linux/interrupt.h>
10#include <linux/irq.h>
11#include <linux/delay.h>
12#include <linux/mutex.h>
13#include <linux/device.h>
14#include <linux/kernel.h>
15#include <linux/spi/spi.h>
16#include <linux/slab.h>
17#include <linux/sysfs.h>
18#include <linux/list.h>
19#include <linux/module.h>
20
21#include "../iio.h"
22#include "../sysfs.h"
23#include "meter.h"
24#include "ade7753.h"
25
26static int ade7753_spi_write_reg_8(struct device *dev,
27 u8 reg_address,
28 u8 val)
29{
30 int ret;
31 struct iio_dev *indio_dev = dev_get_drvdata(dev);
32 struct ade7753_state *st = iio_priv(indio_dev);
33
34 mutex_lock(&st->buf_lock);
35 st->tx[0] = ADE7753_WRITE_REG(reg_address);
36 st->tx[1] = val;
37
38 ret = spi_write(st->us, st->tx, 2);
39 mutex_unlock(&st->buf_lock);
40
41 return ret;
42}
43
44static int ade7753_spi_write_reg_16(struct device *dev,
45 u8 reg_address,
46 u16 value)
47{
48 int ret;
49 struct iio_dev *indio_dev = dev_get_drvdata(dev);
50 struct ade7753_state *st = iio_priv(indio_dev);
51
52 mutex_lock(&st->buf_lock);
53 st->tx[0] = ADE7753_WRITE_REG(reg_address);
54 st->tx[1] = (value >> 8) & 0xFF;
55 st->tx[2] = value & 0xFF;
56 ret = spi_write(st->us, st->tx, 3);
57 mutex_unlock(&st->buf_lock);
58
59 return ret;
60}
61
62static int ade7753_spi_read_reg_8(struct device *dev,
63 u8 reg_address,
64 u8 *val)
65{
66 struct iio_dev *indio_dev = dev_get_drvdata(dev);
67 struct ade7753_state *st = iio_priv(indio_dev);
68 ssize_t ret;
69
70 ret = spi_w8r8(st->us, ADE7753_READ_REG(reg_address));
71 if (ret < 0) {
72 dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X",
73 reg_address);
74 return ret;
75 }
76 *val = ret;
77
78 return 0;
79}
80
81static int ade7753_spi_read_reg_16(struct device *dev,
82 u8 reg_address,
83 u16 *val)
84{
85 struct iio_dev *indio_dev = dev_get_drvdata(dev);
86 struct ade7753_state *st = iio_priv(indio_dev);
87 ssize_t ret;
88
89 ret = spi_w8r16(st->us, ADE7753_READ_REG(reg_address));
90 if (ret < 0) {
91 dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
92 reg_address);
93 return ret;
94 }
95
96 *val = ret;
97 *val = be16_to_cpup(val);
98
99 return 0;
100}
101
102static int ade7753_spi_read_reg_24(struct device *dev,
103 u8 reg_address,
104 u32 *val)
105{
106 struct spi_message msg;
107 struct iio_dev *indio_dev = dev_get_drvdata(dev);
108 struct ade7753_state *st = iio_priv(indio_dev);
109 int ret;
110 struct spi_transfer xfers[] = {
111 {
112 .tx_buf = st->tx,
113 .bits_per_word = 8,
114 .len = 1,
115 }, {
116 .rx_buf = st->tx,
117 .bits_per_word = 8,
118 .len = 3,
119 }
120 };
121
122 mutex_lock(&st->buf_lock);
123 st->tx[0] = ADE7753_READ_REG(reg_address);
124
125 spi_message_init(&msg);
126 spi_message_add_tail(&xfers[0], &msg);
127 spi_message_add_tail(&xfers[1], &msg);
128 ret = spi_sync(st->us, &msg);
129 if (ret) {
130 dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X",
131 reg_address);
132 goto error_ret;
133 }
134 *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2];
135
136error_ret:
137 mutex_unlock(&st->buf_lock);
138 return ret;
139}
140
141static ssize_t ade7753_read_8bit(struct device *dev,
142 struct device_attribute *attr,
143 char *buf)
144{
145 int ret;
146 u8 val;
147 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
148
149 ret = ade7753_spi_read_reg_8(dev, this_attr->address, &val);
150 if (ret)
151 return ret;
152
153 return sprintf(buf, "%u\n", val);
154}
155
156static ssize_t ade7753_read_16bit(struct device *dev,
157 struct device_attribute *attr,
158 char *buf)
159{
160 int ret;
161 u16 val;
162 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
163
164 ret = ade7753_spi_read_reg_16(dev, this_attr->address, &val);
165 if (ret)
166 return ret;
167
168 return sprintf(buf, "%u\n", val);
169}
170
171static ssize_t ade7753_read_24bit(struct device *dev,
172 struct device_attribute *attr,
173 char *buf)
174{
175 int ret;
176 u32 val;
177 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
178
179 ret = ade7753_spi_read_reg_24(dev, this_attr->address, &val);
180 if (ret)
181 return ret;
182
183 return sprintf(buf, "%u\n", val);
184}
185
186static ssize_t ade7753_write_8bit(struct device *dev,
187 struct device_attribute *attr,
188 const char *buf,
189 size_t len)
190{
191 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
192 int ret;
193 long val;
194
195 ret = strict_strtol(buf, 10, &val);
196 if (ret)
197 goto error_ret;
198 ret = ade7753_spi_write_reg_8(dev, this_attr->address, val);
199
200error_ret:
201 return ret ? ret : len;
202}
203
204static ssize_t ade7753_write_16bit(struct device *dev,
205 struct device_attribute *attr,
206 const char *buf,
207 size_t len)
208{
209 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
210 int ret;
211 long val;
212
213 ret = strict_strtol(buf, 10, &val);
214 if (ret)
215 goto error_ret;
216 ret = ade7753_spi_write_reg_16(dev, this_attr->address, val);
217
218error_ret:
219 return ret ? ret : len;
220}
221
222static int ade7753_reset(struct device *dev)
223{
224 u16 val;
225
226 ade7753_spi_read_reg_16(dev, ADE7753_MODE, &val);
227 val |= 1 << 6;
228
229 return ade7753_spi_write_reg_16(dev, ADE7753_MODE, val);
230}
231
232static ssize_t ade7753_write_reset(struct device *dev,
233 struct device_attribute *attr,
234 const char *buf, size_t len)
235{
236 if (len < 1)
237 return -1;
238 switch (buf[0]) {
239 case '1':
240 case 'y':
241 case 'Y':
242 return ade7753_reset(dev);
243 }
244 return -1;
245}
246
247static IIO_DEV_ATTR_AENERGY(ade7753_read_24bit, ADE7753_AENERGY);
248static IIO_DEV_ATTR_LAENERGY(ade7753_read_24bit, ADE7753_LAENERGY);
249static IIO_DEV_ATTR_VAENERGY(ade7753_read_24bit, ADE7753_VAENERGY);
250static IIO_DEV_ATTR_LVAENERGY(ade7753_read_24bit, ADE7753_LVAENERGY);
251static IIO_DEV_ATTR_CFDEN(S_IWUSR | S_IRUGO,
252 ade7753_read_16bit,
253 ade7753_write_16bit,
254 ADE7753_CFDEN);
255static IIO_DEV_ATTR_CFNUM(S_IWUSR | S_IRUGO,
256 ade7753_read_8bit,
257 ade7753_write_8bit,
258 ADE7753_CFNUM);
259static IIO_DEV_ATTR_CHKSUM(ade7753_read_8bit, ADE7753_CHKSUM);
260static IIO_DEV_ATTR_PHCAL(S_IWUSR | S_IRUGO,
261 ade7753_read_16bit,
262 ade7753_write_16bit,
263 ADE7753_PHCAL);
264static IIO_DEV_ATTR_APOS(S_IWUSR | S_IRUGO,
265 ade7753_read_16bit,
266 ade7753_write_16bit,
267 ADE7753_APOS);
268static IIO_DEV_ATTR_SAGCYC(S_IWUSR | S_IRUGO,
269 ade7753_read_8bit,
270 ade7753_write_8bit,
271 ADE7753_SAGCYC);
272static IIO_DEV_ATTR_SAGLVL(S_IWUSR | S_IRUGO,
273 ade7753_read_8bit,
274 ade7753_write_8bit,
275 ADE7753_SAGLVL);
276static IIO_DEV_ATTR_LINECYC(S_IWUSR | S_IRUGO,
277 ade7753_read_8bit,
278 ade7753_write_8bit,
279 ADE7753_LINECYC);
280static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO,
281 ade7753_read_8bit,
282 ade7753_write_8bit,
283 ADE7753_WDIV);
284static IIO_DEV_ATTR_IRMS(S_IWUSR | S_IRUGO,
285 ade7753_read_24bit,
286 NULL,
287 ADE7753_IRMS);
288static IIO_DEV_ATTR_VRMS(S_IRUGO,
289 ade7753_read_24bit,
290 NULL,
291 ADE7753_VRMS);
292static IIO_DEV_ATTR_IRMSOS(S_IWUSR | S_IRUGO,
293 ade7753_read_16bit,
294 ade7753_write_16bit,
295 ADE7753_IRMSOS);
296static IIO_DEV_ATTR_VRMSOS(S_IWUSR | S_IRUGO,
297 ade7753_read_16bit,
298 ade7753_write_16bit,
299 ADE7753_VRMSOS);
300static IIO_DEV_ATTR_WGAIN(S_IWUSR | S_IRUGO,
301 ade7753_read_16bit,
302 ade7753_write_16bit,
303 ADE7753_WGAIN);
304static IIO_DEV_ATTR_VAGAIN(S_IWUSR | S_IRUGO,
305 ade7753_read_16bit,
306 ade7753_write_16bit,
307 ADE7753_VAGAIN);
308static IIO_DEV_ATTR_PGA_GAIN(S_IWUSR | S_IRUGO,
309 ade7753_read_16bit,
310 ade7753_write_16bit,
311 ADE7753_GAIN);
312static IIO_DEV_ATTR_IPKLVL(S_IWUSR | S_IRUGO,
313 ade7753_read_8bit,
314 ade7753_write_8bit,
315 ADE7753_IPKLVL);
316static IIO_DEV_ATTR_VPKLVL(S_IWUSR | S_IRUGO,
317 ade7753_read_8bit,
318 ade7753_write_8bit,
319 ADE7753_VPKLVL);
320static IIO_DEV_ATTR_IPEAK(S_IRUGO,
321 ade7753_read_24bit,
322 NULL,
323 ADE7753_IPEAK);
324static IIO_DEV_ATTR_VPEAK(S_IRUGO,
325 ade7753_read_24bit,
326 NULL,
327 ADE7753_VPEAK);
328static IIO_DEV_ATTR_VPERIOD(S_IRUGO,
329 ade7753_read_16bit,
330 NULL,
331 ADE7753_PERIOD);
332static IIO_DEV_ATTR_CH_OFF(1, S_IWUSR | S_IRUGO,
333 ade7753_read_8bit,
334 ade7753_write_8bit,
335 ADE7753_CH1OS);
336static IIO_DEV_ATTR_CH_OFF(2, S_IWUSR | S_IRUGO,
337 ade7753_read_8bit,
338 ade7753_write_8bit,
339 ADE7753_CH2OS);
340
341static int ade7753_set_irq(struct device *dev, bool enable)
342{
343 int ret;
344 u8 irqen;
345 ret = ade7753_spi_read_reg_8(dev, ADE7753_IRQEN, &irqen);
346 if (ret)
347 goto error_ret;
348
349 if (enable)
350 irqen |= 1 << 3;
351
352 else
353 irqen &= ~(1 << 3);
354
355 ret = ade7753_spi_write_reg_8(dev, ADE7753_IRQEN, irqen);
356
357error_ret:
358 return ret;
359}
360
361
362static int ade7753_stop_device(struct device *dev)
363{
364 u16 val;
365
366 ade7753_spi_read_reg_16(dev, ADE7753_MODE, &val);
367 val |= 1 << 4;
368
369 return ade7753_spi_write_reg_16(dev, ADE7753_MODE, val);
370}
371
372static int ade7753_initial_setup(struct iio_dev *indio_dev)
373{
374 int ret;
375 struct device *dev = &indio_dev->dev;
376 struct ade7753_state *st = iio_priv(indio_dev);
377
378
379 st->us->mode = SPI_MODE_3;
380 spi_setup(st->us);
381
382
383 ret = ade7753_set_irq(dev, false);
384 if (ret) {
385 dev_err(dev, "disable irq failed");
386 goto err_ret;
387 }
388
389 ade7753_reset(dev);
390 msleep(ADE7753_STARTUP_DELAY);
391
392err_ret:
393 return ret;
394}
395
396static ssize_t ade7753_read_frequency(struct device *dev,
397 struct device_attribute *attr,
398 char *buf)
399{
400 int ret, len = 0;
401 u16 t;
402 int sps;
403 ret = ade7753_spi_read_reg_16(dev, ADE7753_MODE, &t);
404 if (ret)
405 return ret;
406
407 t = (t >> 11) & 0x3;
408 sps = 27900 / (1 + t);
409
410 len = sprintf(buf, "%d\n", sps);
411 return len;
412}
413
414static ssize_t ade7753_write_frequency(struct device *dev,
415 struct device_attribute *attr,
416 const char *buf,
417 size_t len)
418{
419 struct iio_dev *indio_dev = dev_get_drvdata(dev);
420 struct ade7753_state *st = iio_priv(indio_dev);
421 unsigned long val;
422 int ret;
423 u16 reg, t;
424
425 ret = strict_strtol(buf, 10, &val);
426 if (ret)
427 return ret;
428
429 mutex_lock(&indio_dev->mlock);
430
431 t = (27900 / val);
432 if (t > 0)
433 t--;
434
435 if (t > 1)
436 st->us->max_speed_hz = ADE7753_SPI_SLOW;
437 else
438 st->us->max_speed_hz = ADE7753_SPI_FAST;
439
440 ret = ade7753_spi_read_reg_16(dev, ADE7753_MODE, ®);
441 if (ret)
442 goto out;
443
444 reg &= ~(3 << 11);
445 reg |= t << 11;
446
447 ret = ade7753_spi_write_reg_16(dev, ADE7753_MODE, reg);
448
449out:
450 mutex_unlock(&indio_dev->mlock);
451
452 return ret ? ret : len;
453}
454
455static IIO_DEV_ATTR_TEMP_RAW(ade7753_read_8bit);
456static IIO_CONST_ATTR(in_temp_offset, "-25 C");
457static IIO_CONST_ATTR(in_temp_scale, "0.67 C");
458
459static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
460 ade7753_read_frequency,
461 ade7753_write_frequency);
462
463static IIO_DEV_ATTR_RESET(ade7753_write_reset);
464
465static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("27900 14000 7000 3500");
466
467static struct attribute *ade7753_attributes[] = {
468 &iio_dev_attr_in_temp_raw.dev_attr.attr,
469 &iio_const_attr_in_temp_offset.dev_attr.attr,
470 &iio_const_attr_in_temp_scale.dev_attr.attr,
471 &iio_dev_attr_sampling_frequency.dev_attr.attr,
472 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
473 &iio_dev_attr_reset.dev_attr.attr,
474 &iio_dev_attr_phcal.dev_attr.attr,
475 &iio_dev_attr_cfden.dev_attr.attr,
476 &iio_dev_attr_aenergy.dev_attr.attr,
477 &iio_dev_attr_laenergy.dev_attr.attr,
478 &iio_dev_attr_vaenergy.dev_attr.attr,
479 &iio_dev_attr_lvaenergy.dev_attr.attr,
480 &iio_dev_attr_cfnum.dev_attr.attr,
481 &iio_dev_attr_apos.dev_attr.attr,
482 &iio_dev_attr_sagcyc.dev_attr.attr,
483 &iio_dev_attr_saglvl.dev_attr.attr,
484 &iio_dev_attr_linecyc.dev_attr.attr,
485 &iio_dev_attr_chksum.dev_attr.attr,
486 &iio_dev_attr_pga_gain.dev_attr.attr,
487 &iio_dev_attr_wgain.dev_attr.attr,
488 &iio_dev_attr_choff_1.dev_attr.attr,
489 &iio_dev_attr_choff_2.dev_attr.attr,
490 &iio_dev_attr_wdiv.dev_attr.attr,
491 &iio_dev_attr_irms.dev_attr.attr,
492 &iio_dev_attr_vrms.dev_attr.attr,
493 &iio_dev_attr_irmsos.dev_attr.attr,
494 &iio_dev_attr_vrmsos.dev_attr.attr,
495 &iio_dev_attr_vagain.dev_attr.attr,
496 &iio_dev_attr_ipklvl.dev_attr.attr,
497 &iio_dev_attr_vpklvl.dev_attr.attr,
498 &iio_dev_attr_ipeak.dev_attr.attr,
499 &iio_dev_attr_vpeak.dev_attr.attr,
500 &iio_dev_attr_vperiod.dev_attr.attr,
501 NULL,
502};
503
504static const struct attribute_group ade7753_attribute_group = {
505 .attrs = ade7753_attributes,
506};
507
508static const struct iio_info ade7753_info = {
509 .attrs = &ade7753_attribute_group,
510 .driver_module = THIS_MODULE,
511};
512
513static int __devinit ade7753_probe(struct spi_device *spi)
514{
515 int ret;
516 struct ade7753_state *st;
517 struct iio_dev *indio_dev;
518
519
520 indio_dev = iio_allocate_device(sizeof(*st));
521 if (indio_dev == NULL) {
522 ret = -ENOMEM;
523 goto error_ret;
524 }
525
526 spi_set_drvdata(spi, indio_dev);
527
528 st = iio_priv(indio_dev);
529 st->us = spi;
530 mutex_init(&st->buf_lock);
531
532 indio_dev->name = spi->dev.driver->name;
533 indio_dev->dev.parent = &spi->dev;
534 indio_dev->info = &ade7753_info;
535 indio_dev->modes = INDIO_DIRECT_MODE;
536
537
538 ret = ade7753_initial_setup(indio_dev);
539 if (ret)
540 goto error_free_dev;
541
542 ret = iio_device_register(indio_dev);
543 if (ret)
544 goto error_free_dev;
545
546 return 0;
547
548error_free_dev:
549 iio_free_device(indio_dev);
550
551error_ret:
552 return ret;
553}
554
555
556static int ade7753_remove(struct spi_device *spi)
557{
558 int ret;
559 struct iio_dev *indio_dev = spi_get_drvdata(spi);
560
561 iio_device_unregister(indio_dev);
562
563 ret = ade7753_stop_device(&(indio_dev->dev));
564 if (ret)
565 goto err_ret;
566
567 iio_free_device(indio_dev);
568err_ret:
569 return ret;
570}
571
572static struct spi_driver ade7753_driver = {
573 .driver = {
574 .name = "ade7753",
575 .owner = THIS_MODULE,
576 },
577 .probe = ade7753_probe,
578 .remove = __devexit_p(ade7753_remove),
579};
580module_spi_driver(ade7753_driver);
581
582MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
583MODULE_DESCRIPTION("Analog Devices ADE7753/6 Single-Phase Multifunction Meter");
584MODULE_LICENSE("GPL v2");
585MODULE_ALIAS("spi:ade7753");
586
