1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
22
23
24
25
26
27
28
29
30
31
32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33typedef __u32 __bitwise __hc32;
34typedef __u16 __bitwise __hc16;
35#else
36#define __hc32 __le32
37#define __hc16 __le16
38#endif
39
40
41struct ehci_stats {
42
43 unsigned long normal;
44 unsigned long error;
45 unsigned long reclaim;
46 unsigned long lost_iaa;
47
48
49 unsigned long complete;
50 unsigned long unlink;
51};
52
53
54
55
56
57
58
59
60
61
62
63#define EHCI_MAX_ROOT_PORTS 15
64
65enum ehci_rh_state {
66 EHCI_RH_HALTED,
67 EHCI_RH_SUSPENDED,
68 EHCI_RH_RUNNING
69};
70
71struct ehci_hcd {
72
73 struct ehci_caps __iomem *caps;
74 struct ehci_regs __iomem *regs;
75 struct ehci_dbg_port __iomem *debug;
76
77 __u32 hcs_params;
78 spinlock_t lock;
79 enum ehci_rh_state rh_state;
80
81
82 struct ehci_qh *async;
83 struct ehci_qh *dummy;
84 struct ehci_qh *reclaim;
85 struct ehci_qh *qh_scan_next;
86 unsigned scanning : 1;
87
88
89#define DEFAULT_I_TDPS 1024
90 unsigned periodic_size;
91 __hc32 *periodic;
92 dma_addr_t periodic_dma;
93 unsigned i_thresh;
94
95 union ehci_shadow *pshadow;
96 int next_uframe;
97 unsigned periodic_sched;
98 unsigned uframe_periodic_max;
99
100
101
102 struct list_head cached_itd_list;
103 struct list_head cached_sitd_list;
104 unsigned clock_frame;
105
106
107 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
108
109
110 unsigned long bus_suspended;
111
112 unsigned long companion_ports;
113
114 unsigned long owned_ports;
115
116 unsigned long port_c_suspend;
117
118 unsigned long suspended_ports;
119
120
121
122 struct dma_pool *qh_pool;
123 struct dma_pool *qtd_pool;
124 struct dma_pool *itd_pool;
125 struct dma_pool *sitd_pool;
126
127 struct timer_list iaa_watchdog;
128 struct timer_list watchdog;
129 unsigned long actions;
130 unsigned periodic_stamp;
131 unsigned random_frame;
132 unsigned long next_statechange;
133 ktime_t last_periodic_enable;
134 u32 command;
135
136
137 unsigned no_selective_suspend:1;
138 unsigned has_fsl_port_bug:1;
139 unsigned big_endian_mmio:1;
140 unsigned big_endian_desc:1;
141 unsigned big_endian_capbase:1;
142 unsigned has_amcc_usb23:1;
143 unsigned need_io_watchdog:1;
144 unsigned broken_periodic:1;
145 unsigned amd_pll_fix:1;
146 unsigned fs_i_thresh:1;
147 unsigned use_dummy_qh:1;
148 unsigned has_synopsys_hc_bug:1;
149 unsigned frame_index_bug:1;
150
151
152 #define OHCI_CTRL_HCFS (3 << 6)
153 #define OHCI_USB_OPER (2 << 6)
154 #define OHCI_USB_SUSPEND (3 << 6)
155
156 #define OHCI_HCCTRL_OFFSET 0x4
157 #define OHCI_HCCTRL_LEN 0x4
158 __hc32 *ohci_hcctrl_reg;
159 unsigned has_hostpc:1;
160 unsigned has_lpm:1;
161 unsigned has_ppcd:1;
162 u8 sbrn;
163
164
165#ifdef EHCI_STATS
166 struct ehci_stats stats;
167# define COUNT(x) do { (x)++; } while (0)
168#else
169# define COUNT(x) do {} while (0)
170#endif
171
172
173#ifdef DEBUG
174 struct dentry *debug_dir;
175#endif
176
177
178
179 struct otg_transceiver *transceiver;
180};
181
182
183static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
184{
185 return (struct ehci_hcd *) (hcd->hcd_priv);
186}
187static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
188{
189 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
190}
191
192
193static inline void
194iaa_watchdog_start(struct ehci_hcd *ehci)
195{
196 WARN_ON(timer_pending(&ehci->iaa_watchdog));
197 mod_timer(&ehci->iaa_watchdog,
198 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
199}
200
201static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
202{
203 del_timer(&ehci->iaa_watchdog);
204}
205
206enum ehci_timer_action {
207 TIMER_IO_WATCHDOG,
208 TIMER_ASYNC_SHRINK,
209 TIMER_ASYNC_OFF,
210};
211
212static inline void
213timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
214{
215 clear_bit (action, &ehci->actions);
216}
217
218static void free_cached_lists(struct ehci_hcd *ehci);
219
220
221
222#include <linux/usb/ehci_def.h>
223
224
225
226#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
227
228
229
230
231
232
233
234
235
236struct ehci_qtd {
237
238 __hc32 hw_next;
239 __hc32 hw_alt_next;
240 __hc32 hw_token;
241#define QTD_TOGGLE (1 << 31)
242#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
243#define QTD_IOC (1 << 15)
244#define QTD_CERR(tok) (((tok)>>10) & 0x3)
245#define QTD_PID(tok) (((tok)>>8) & 0x3)
246#define QTD_STS_ACTIVE (1 << 7)
247#define QTD_STS_HALT (1 << 6)
248#define QTD_STS_DBE (1 << 5)
249#define QTD_STS_BABBLE (1 << 4)
250#define QTD_STS_XACT (1 << 3)
251#define QTD_STS_MMF (1 << 2)
252#define QTD_STS_STS (1 << 1)
253#define QTD_STS_PING (1 << 0)
254
255#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
256#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
257#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
258
259 __hc32 hw_buf [5];
260 __hc32 hw_buf_hi [5];
261
262
263 dma_addr_t qtd_dma;
264 struct list_head qtd_list;
265 struct urb *urb;
266 size_t length;
267} __attribute__ ((aligned (32)));
268
269
270#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
271
272#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
273
274
275
276
277#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
278
279
280
281
282
283
284
285
286
287#define Q_TYPE_ITD (0 << 1)
288#define Q_TYPE_QH (1 << 1)
289#define Q_TYPE_SITD (2 << 1)
290#define Q_TYPE_FSTN (3 << 1)
291
292
293#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
294
295
296#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1)
297
298
299
300
301
302
303
304
305
306union ehci_shadow {
307 struct ehci_qh *qh;
308 struct ehci_itd *itd;
309 struct ehci_sitd *sitd;
310 struct ehci_fstn *fstn;
311 __hc32 *hw_next;
312 void *ptr;
313};
314
315
316
317
318
319
320
321
322
323
324
325
326struct ehci_qh_hw {
327 __hc32 hw_next;
328 __hc32 hw_info1;
329#define QH_HEAD 0x00008000
330 __hc32 hw_info2;
331#define QH_SMASK 0x000000ff
332#define QH_CMASK 0x0000ff00
333#define QH_HUBADDR 0x007f0000
334#define QH_HUBPORT 0x3f800000
335#define QH_MULT 0xc0000000
336 __hc32 hw_current;
337
338
339 __hc32 hw_qtd_next;
340 __hc32 hw_alt_next;
341 __hc32 hw_token;
342 __hc32 hw_buf [5];
343 __hc32 hw_buf_hi [5];
344} __attribute__ ((aligned(32)));
345
346struct ehci_qh {
347 struct ehci_qh_hw *hw;
348
349 dma_addr_t qh_dma;
350 union ehci_shadow qh_next;
351 struct list_head qtd_list;
352 struct ehci_qtd *dummy;
353 struct ehci_qh *reclaim;
354
355 struct ehci_hcd *ehci;
356 unsigned long unlink_time;
357
358
359
360
361
362
363
364 u32 refcount;
365 unsigned stamp;
366
367 u8 needs_rescan;
368 u8 qh_state;
369#define QH_STATE_LINKED 1
370#define QH_STATE_UNLINK 2
371#define QH_STATE_IDLE 3
372#define QH_STATE_UNLINK_WAIT 4
373#define QH_STATE_COMPLETING 5
374
375 u8 xacterrs;
376#define QH_XACTERR_MAX 32
377
378
379 u8 usecs;
380 u8 gap_uf;
381 u8 c_usecs;
382 u16 tt_usecs;
383 unsigned short period;
384 unsigned short start;
385#define NO_FRAME ((unsigned short)~0)
386
387 struct usb_device *dev;
388 unsigned is_out:1;
389 unsigned clearing_tt:1;
390};
391
392
393
394
395struct ehci_iso_packet {
396
397 u64 bufp;
398 __hc32 transaction;
399 u8 cross;
400
401 u32 buf1;
402};
403
404
405
406
407
408struct ehci_iso_sched {
409 struct list_head td_list;
410 unsigned span;
411 struct ehci_iso_packet packet [0];
412};
413
414
415
416
417
418struct ehci_iso_stream {
419
420 struct ehci_qh_hw *hw;
421
422 u32 refcount;
423 u8 bEndpointAddress;
424 u8 highspeed;
425 struct list_head td_list;
426 struct list_head free_list;
427 struct usb_device *udev;
428 struct usb_host_endpoint *ep;
429
430
431 int next_uframe;
432 __hc32 splits;
433
434
435
436
437
438 u8 usecs, c_usecs;
439 u16 interval;
440 u16 tt_usecs;
441 u16 maxp;
442 u16 raw_mask;
443 unsigned bandwidth;
444
445
446 __hc32 buf0;
447 __hc32 buf1;
448 __hc32 buf2;
449
450
451 __hc32 address;
452};
453
454
455
456
457
458
459
460
461
462struct ehci_itd {
463
464 __hc32 hw_next;
465 __hc32 hw_transaction [8];
466#define EHCI_ISOC_ACTIVE (1<<31)
467#define EHCI_ISOC_BUF_ERR (1<<30)
468#define EHCI_ISOC_BABBLE (1<<29)
469#define EHCI_ISOC_XACTERR (1<<28)
470#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
471#define EHCI_ITD_IOC (1 << 15)
472
473#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
474
475 __hc32 hw_bufp [7];
476 __hc32 hw_bufp_hi [7];
477
478
479 dma_addr_t itd_dma;
480 union ehci_shadow itd_next;
481
482 struct urb *urb;
483 struct ehci_iso_stream *stream;
484 struct list_head itd_list;
485
486
487 unsigned frame;
488 unsigned pg;
489 unsigned index[8];
490} __attribute__ ((aligned (32)));
491
492
493
494
495
496
497
498
499
500struct ehci_sitd {
501
502 __hc32 hw_next;
503
504 __hc32 hw_fullspeed_ep;
505 __hc32 hw_uframe;
506 __hc32 hw_results;
507#define SITD_IOC (1 << 31)
508#define SITD_PAGE (1 << 30)
509#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
510#define SITD_STS_ACTIVE (1 << 7)
511#define SITD_STS_ERR (1 << 6)
512#define SITD_STS_DBE (1 << 5)
513#define SITD_STS_BABBLE (1 << 4)
514#define SITD_STS_XACT (1 << 3)
515#define SITD_STS_MMF (1 << 2)
516#define SITD_STS_STS (1 << 1)
517
518#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
519
520 __hc32 hw_buf [2];
521 __hc32 hw_backpointer;
522 __hc32 hw_buf_hi [2];
523
524
525 dma_addr_t sitd_dma;
526 union ehci_shadow sitd_next;
527
528 struct urb *urb;
529 struct ehci_iso_stream *stream;
530 struct list_head sitd_list;
531 unsigned frame;
532 unsigned index;
533} __attribute__ ((aligned (32)));
534
535
536
537
538
539
540
541
542
543
544
545
546struct ehci_fstn {
547 __hc32 hw_next;
548 __hc32 hw_prev;
549
550
551 dma_addr_t fstn_dma;
552 union ehci_shadow fstn_next;
553} __attribute__ ((aligned (32)));
554
555
556
557
558
559#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
560 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
561
562#define ehci_prepare_ports_for_controller_resume(ehci) \
563 ehci_adjust_port_wakeup_flags(ehci, false, false);
564
565
566
567#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
568
569
570
571
572
573
574
575
576#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
577
578
579static inline unsigned int
580ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
581{
582 if (ehci_is_TDI(ehci)) {
583 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
584 case 0:
585 return 0;
586 case 1:
587 return USB_PORT_STAT_LOW_SPEED;
588 case 2:
589 default:
590 return USB_PORT_STAT_HIGH_SPEED;
591 }
592 }
593 return USB_PORT_STAT_HIGH_SPEED;
594}
595
596#else
597
598#define ehci_is_TDI(e) (0)
599
600#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
601#endif
602
603
604
605#ifdef CONFIG_PPC_83xx
606
607
608
609#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
610#else
611#define ehci_has_fsl_portno_bug(e) (0)
612#endif
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
629#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
630#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
631#else
632#define ehci_big_endian_mmio(e) 0
633#define ehci_big_endian_capbase(e) 0
634#endif
635
636
637
638
639
640#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
641#define readl_be(addr) __raw_readl((__force unsigned *)addr)
642#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
643#endif
644
645static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
646 __u32 __iomem * regs)
647{
648#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
649 return ehci_big_endian_mmio(ehci) ?
650 readl_be(regs) :
651 readl(regs);
652#else
653 return readl(regs);
654#endif
655}
656
657static inline void ehci_writel(const struct ehci_hcd *ehci,
658 const unsigned int val, __u32 __iomem *regs)
659{
660#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
661 ehci_big_endian_mmio(ehci) ?
662 writel_be(val, regs) :
663 writel(val, regs);
664#else
665 writel(val, regs);
666#endif
667}
668
669
670
671
672
673
674#ifdef CONFIG_44x
675static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
676{
677 u32 hc_control;
678
679 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
680 if (operational)
681 hc_control |= OHCI_USB_OPER;
682 else
683 hc_control |= OHCI_USB_SUSPEND;
684
685 writel_be(hc_control, ehci->ohci_hcctrl_reg);
686 (void) readl_be(ehci->ohci_hcctrl_reg);
687}
688#else
689static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
690{ }
691#endif
692
693
694
695
696
697
698
699
700
701
702#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
703#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
704
705
706static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
707{
708 return ehci_big_endian_desc(ehci)
709 ? (__force __hc32)cpu_to_be32(x)
710 : (__force __hc32)cpu_to_le32(x);
711}
712
713
714static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
715{
716 return ehci_big_endian_desc(ehci)
717 ? be32_to_cpu((__force __be32)x)
718 : le32_to_cpu((__force __le32)x);
719}
720
721static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
722{
723 return ehci_big_endian_desc(ehci)
724 ? be32_to_cpup((__force __be32 *)x)
725 : le32_to_cpup((__force __le32 *)x);
726}
727
728#else
729
730
731static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
732{
733 return cpu_to_le32(x);
734}
735
736
737static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
738{
739 return le32_to_cpu(x);
740}
741
742static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
743{
744 return le32_to_cpup(x);
745}
746
747#endif
748
749
750
751#ifdef CONFIG_PCI
752
753
754static unsigned ehci_read_frame_index(struct ehci_hcd *ehci);
755
756#else
757
758static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
759{
760 return ehci_readl(ehci, &ehci->regs->frame_index);
761}
762
763#endif
764
765
766
767#ifndef DEBUG
768#define STUB_DEBUG_FILES
769#endif
770
771
772
773#endif
774