linux/arch/arm/mach-davinci/clock.c
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   1/*
   2 * Clock and PLL control for DaVinci devices
   3 *
   4 * Copyright (C) 2006-2007 Texas Instruments.
   5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 */
  12
  13#include <linux/module.h>
  14#include <linux/kernel.h>
  15#include <linux/init.h>
  16#include <linux/errno.h>
  17#include <linux/clk.h>
  18#include <linux/err.h>
  19#include <linux/mutex.h>
  20#include <linux/io.h>
  21#include <linux/delay.h>
  22
  23#include <mach/hardware.h>
  24
  25#include <mach/clock.h>
  26#include <mach/psc.h>
  27#include <mach/cputype.h>
  28#include "clock.h"
  29
  30static LIST_HEAD(clocks);
  31static DEFINE_MUTEX(clocks_mutex);
  32static DEFINE_SPINLOCK(clockfw_lock);
  33
  34static void __clk_enable(struct clk *clk)
  35{
  36        if (clk->parent)
  37                __clk_enable(clk->parent);
  38        if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
  39                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
  40                                true, clk->flags);
  41}
  42
  43static void __clk_disable(struct clk *clk)
  44{
  45        if (WARN_ON(clk->usecount == 0))
  46                return;
  47        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
  48            (clk->flags & CLK_PSC))
  49                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
  50                                false, clk->flags);
  51        if (clk->parent)
  52                __clk_disable(clk->parent);
  53}
  54
  55int clk_enable(struct clk *clk)
  56{
  57        unsigned long flags;
  58
  59        if (clk == NULL || IS_ERR(clk))
  60                return -EINVAL;
  61
  62        spin_lock_irqsave(&clockfw_lock, flags);
  63        __clk_enable(clk);
  64        spin_unlock_irqrestore(&clockfw_lock, flags);
  65
  66        return 0;
  67}
  68EXPORT_SYMBOL(clk_enable);
  69
  70void clk_disable(struct clk *clk)
  71{
  72        unsigned long flags;
  73
  74        if (clk == NULL || IS_ERR(clk))
  75                return;
  76
  77        spin_lock_irqsave(&clockfw_lock, flags);
  78        __clk_disable(clk);
  79        spin_unlock_irqrestore(&clockfw_lock, flags);
  80}
  81EXPORT_SYMBOL(clk_disable);
  82
  83unsigned long clk_get_rate(struct clk *clk)
  84{
  85        if (clk == NULL || IS_ERR(clk))
  86                return -EINVAL;
  87
  88        return clk->rate;
  89}
  90EXPORT_SYMBOL(clk_get_rate);
  91
  92long clk_round_rate(struct clk *clk, unsigned long rate)
  93{
  94        if (clk == NULL || IS_ERR(clk))
  95                return -EINVAL;
  96
  97        if (clk->round_rate)
  98                return clk->round_rate(clk, rate);
  99
 100        return clk->rate;
 101}
 102EXPORT_SYMBOL(clk_round_rate);
 103
 104/* Propagate rate to children */
 105static void propagate_rate(struct clk *root)
 106{
 107        struct clk *clk;
 108
 109        list_for_each_entry(clk, &root->children, childnode) {
 110                if (clk->recalc)
 111                        clk->rate = clk->recalc(clk);
 112                propagate_rate(clk);
 113        }
 114}
 115
 116int clk_set_rate(struct clk *clk, unsigned long rate)
 117{
 118        unsigned long flags;
 119        int ret = -EINVAL;
 120
 121        if (clk == NULL || IS_ERR(clk))
 122                return ret;
 123
 124        if (clk->set_rate)
 125                ret = clk->set_rate(clk, rate);
 126
 127        spin_lock_irqsave(&clockfw_lock, flags);
 128        if (ret == 0) {
 129                if (clk->recalc)
 130                        clk->rate = clk->recalc(clk);
 131                propagate_rate(clk);
 132        }
 133        spin_unlock_irqrestore(&clockfw_lock, flags);
 134
 135        return ret;
 136}
 137EXPORT_SYMBOL(clk_set_rate);
 138
 139int clk_set_parent(struct clk *clk, struct clk *parent)
 140{
 141        unsigned long flags;
 142
 143        if (clk == NULL || IS_ERR(clk))
 144                return -EINVAL;
 145
 146        /* Cannot change parent on enabled clock */
 147        if (WARN_ON(clk->usecount))
 148                return -EINVAL;
 149
 150        mutex_lock(&clocks_mutex);
 151        clk->parent = parent;
 152        list_del_init(&clk->childnode);
 153        list_add(&clk->childnode, &clk->parent->children);
 154        mutex_unlock(&clocks_mutex);
 155
 156        spin_lock_irqsave(&clockfw_lock, flags);
 157        if (clk->recalc)
 158                clk->rate = clk->recalc(clk);
 159        propagate_rate(clk);
 160        spin_unlock_irqrestore(&clockfw_lock, flags);
 161
 162        return 0;
 163}
 164EXPORT_SYMBOL(clk_set_parent);
 165
 166int clk_register(struct clk *clk)
 167{
 168        if (clk == NULL || IS_ERR(clk))
 169                return -EINVAL;
 170
 171        if (WARN(clk->parent && !clk->parent->rate,
 172                        "CLK: %s parent %s has no rate!\n",
 173                        clk->name, clk->parent->name))
 174                return -EINVAL;
 175
 176        INIT_LIST_HEAD(&clk->children);
 177
 178        mutex_lock(&clocks_mutex);
 179        list_add_tail(&clk->node, &clocks);
 180        if (clk->parent)
 181                list_add_tail(&clk->childnode, &clk->parent->children);
 182        mutex_unlock(&clocks_mutex);
 183
 184        /* If rate is already set, use it */
 185        if (clk->rate)
 186                return 0;
 187
 188        /* Else, see if there is a way to calculate it */
 189        if (clk->recalc)
 190                clk->rate = clk->recalc(clk);
 191
 192        /* Otherwise, default to parent rate */
 193        else if (clk->parent)
 194                clk->rate = clk->parent->rate;
 195
 196        return 0;
 197}
 198EXPORT_SYMBOL(clk_register);
 199
 200void clk_unregister(struct clk *clk)
 201{
 202        if (clk == NULL || IS_ERR(clk))
 203                return;
 204
 205        mutex_lock(&clocks_mutex);
 206        list_del(&clk->node);
 207        list_del(&clk->childnode);
 208        mutex_unlock(&clocks_mutex);
 209}
 210EXPORT_SYMBOL(clk_unregister);
 211
 212#ifdef CONFIG_DAVINCI_RESET_CLOCKS
 213/*
 214 * Disable any unused clocks left on by the bootloader
 215 */
 216static int __init clk_disable_unused(void)
 217{
 218        struct clk *ck;
 219
 220        spin_lock_irq(&clockfw_lock);
 221        list_for_each_entry(ck, &clocks, node) {
 222                if (ck->usecount > 0)
 223                        continue;
 224                if (!(ck->flags & CLK_PSC))
 225                        continue;
 226
 227                /* ignore if in Disabled or SwRstDisable states */
 228                if (!davinci_psc_is_clk_active(ck->gpsc, ck->lpsc))
 229                        continue;
 230
 231                pr_debug("Clocks: disable unused %s\n", ck->name);
 232
 233                davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
 234                                false, ck->flags);
 235        }
 236        spin_unlock_irq(&clockfw_lock);
 237
 238        return 0;
 239}
 240late_initcall(clk_disable_unused);
 241#endif
 242
 243static unsigned long clk_sysclk_recalc(struct clk *clk)
 244{
 245        u32 v, plldiv;
 246        struct pll_data *pll;
 247        unsigned long rate = clk->rate;
 248
 249        /* If this is the PLL base clock, no more calculations needed */
 250        if (clk->pll_data)
 251                return rate;
 252
 253        if (WARN_ON(!clk->parent))
 254                return rate;
 255
 256        rate = clk->parent->rate;
 257
 258        /* Otherwise, the parent must be a PLL */
 259        if (WARN_ON(!clk->parent->pll_data))
 260                return rate;
 261
 262        pll = clk->parent->pll_data;
 263
 264        /* If pre-PLL, source clock is before the multiplier and divider(s) */
 265        if (clk->flags & PRE_PLL)
 266                rate = pll->input_rate;
 267
 268        if (!clk->div_reg)
 269                return rate;
 270
 271        v = __raw_readl(pll->base + clk->div_reg);
 272        if (v & PLLDIV_EN) {
 273                plldiv = (v & pll->div_ratio_mask) + 1;
 274                if (plldiv)
 275                        rate /= plldiv;
 276        }
 277
 278        return rate;
 279}
 280
 281int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
 282{
 283        unsigned v;
 284        struct pll_data *pll;
 285        unsigned long input;
 286        unsigned ratio = 0;
 287
 288        /* If this is the PLL base clock, wrong function to call */
 289        if (clk->pll_data)
 290                return -EINVAL;
 291
 292        /* There must be a parent... */
 293        if (WARN_ON(!clk->parent))
 294                return -EINVAL;
 295
 296        /* ... the parent must be a PLL... */
 297        if (WARN_ON(!clk->parent->pll_data))
 298                return -EINVAL;
 299
 300        /* ... and this clock must have a divider. */
 301        if (WARN_ON(!clk->div_reg))
 302                return -EINVAL;
 303
 304        pll = clk->parent->pll_data;
 305
 306        input = clk->parent->rate;
 307
 308        /* If pre-PLL, source clock is before the multiplier and divider(s) */
 309        if (clk->flags & PRE_PLL)
 310                input = pll->input_rate;
 311
 312        if (input > rate) {
 313                /*
 314                 * Can afford to provide an output little higher than requested
 315                 * only if maximum rate supported by hardware on this sysclk
 316                 * is known.
 317                 */
 318                if (clk->maxrate) {
 319                        ratio = DIV_ROUND_CLOSEST(input, rate);
 320                        if (input / ratio > clk->maxrate)
 321                                ratio = 0;
 322                }
 323
 324                if (ratio == 0)
 325                        ratio = DIV_ROUND_UP(input, rate);
 326
 327                ratio--;
 328        }
 329
 330        if (ratio > pll->div_ratio_mask)
 331                return -EINVAL;
 332
 333        do {
 334                v = __raw_readl(pll->base + PLLSTAT);
 335        } while (v & PLLSTAT_GOSTAT);
 336
 337        v = __raw_readl(pll->base + clk->div_reg);
 338        v &= ~pll->div_ratio_mask;
 339        v |= ratio | PLLDIV_EN;
 340        __raw_writel(v, pll->base + clk->div_reg);
 341
 342        v = __raw_readl(pll->base + PLLCMD);
 343        v |= PLLCMD_GOSET;
 344        __raw_writel(v, pll->base + PLLCMD);
 345
 346        do {
 347                v = __raw_readl(pll->base + PLLSTAT);
 348        } while (v & PLLSTAT_GOSTAT);
 349
 350        return 0;
 351}
 352EXPORT_SYMBOL(davinci_set_sysclk_rate);
 353
 354static unsigned long clk_leafclk_recalc(struct clk *clk)
 355{
 356        if (WARN_ON(!clk->parent))
 357                return clk->rate;
 358
 359        return clk->parent->rate;
 360}
 361
 362int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
 363{
 364        clk->rate = rate;
 365        return 0;
 366}
 367
 368static unsigned long clk_pllclk_recalc(struct clk *clk)
 369{
 370        u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
 371        u8 bypass;
 372        struct pll_data *pll = clk->pll_data;
 373        unsigned long rate = clk->rate;
 374
 375        ctrl = __raw_readl(pll->base + PLLCTL);
 376        rate = pll->input_rate = clk->parent->rate;
 377
 378        if (ctrl & PLLCTL_PLLEN) {
 379                bypass = 0;
 380                mult = __raw_readl(pll->base + PLLM);
 381                if (cpu_is_davinci_dm365())
 382                        mult = 2 * (mult & PLLM_PLLM_MASK);
 383                else
 384                        mult = (mult & PLLM_PLLM_MASK) + 1;
 385        } else
 386                bypass = 1;
 387
 388        if (pll->flags & PLL_HAS_PREDIV) {
 389                prediv = __raw_readl(pll->base + PREDIV);
 390                if (prediv & PLLDIV_EN)
 391                        prediv = (prediv & pll->div_ratio_mask) + 1;
 392                else
 393                        prediv = 1;
 394        }
 395
 396        /* pre-divider is fixed, but (some?) chips won't report that */
 397        if (cpu_is_davinci_dm355() && pll->num == 1)
 398                prediv = 8;
 399
 400        if (pll->flags & PLL_HAS_POSTDIV) {
 401                postdiv = __raw_readl(pll->base + POSTDIV);
 402                if (postdiv & PLLDIV_EN)
 403                        postdiv = (postdiv & pll->div_ratio_mask) + 1;
 404                else
 405                        postdiv = 1;
 406        }
 407
 408        if (!bypass) {
 409                rate /= prediv;
 410                rate *= mult;
 411                rate /= postdiv;
 412        }
 413
 414        pr_debug("PLL%d: input = %lu MHz [ ",
 415                 pll->num, clk->parent->rate / 1000000);
 416        if (bypass)
 417                pr_debug("bypass ");
 418        if (prediv > 1)
 419                pr_debug("/ %d ", prediv);
 420        if (mult > 1)
 421                pr_debug("* %d ", mult);
 422        if (postdiv > 1)
 423                pr_debug("/ %d ", postdiv);
 424        pr_debug("] --> %lu MHz output.\n", rate / 1000000);
 425
 426        return rate;
 427}
 428
 429/**
 430 * davinci_set_pllrate - set the output rate of a given PLL.
 431 *
 432 * Note: Currently tested to work with OMAP-L138 only.
 433 *
 434 * @pll: pll whose rate needs to be changed.
 435 * @prediv: The pre divider value. Passing 0 disables the pre-divider.
 436 * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
 437 * @postdiv: The post divider value. Passing 0 disables the post-divider.
 438 */
 439int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 440                                        unsigned int mult, unsigned int postdiv)
 441{
 442        u32 ctrl;
 443        unsigned int locktime;
 444        unsigned long flags;
 445
 446        if (pll->base == NULL)
 447                return -EINVAL;
 448
 449        /*
 450         *  PLL lock time required per OMAP-L138 datasheet is
 451         * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
 452         * as 4 and OSCIN cycle as 25 MHz.
 453         */
 454        if (prediv) {
 455                locktime = ((2000 * prediv) / 100);
 456                prediv = (prediv - 1) | PLLDIV_EN;
 457        } else {
 458                locktime = PLL_LOCK_TIME;
 459        }
 460        if (postdiv)
 461                postdiv = (postdiv - 1) | PLLDIV_EN;
 462        if (mult)
 463                mult = mult - 1;
 464
 465        /* Protect against simultaneous calls to PLL setting seqeunce */
 466        spin_lock_irqsave(&clockfw_lock, flags);
 467
 468        ctrl = __raw_readl(pll->base + PLLCTL);
 469
 470        /* Switch the PLL to bypass mode */
 471        ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
 472        __raw_writel(ctrl, pll->base + PLLCTL);
 473
 474        udelay(PLL_BYPASS_TIME);
 475
 476        /* Reset and enable PLL */
 477        ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
 478        __raw_writel(ctrl, pll->base + PLLCTL);
 479
 480        if (pll->flags & PLL_HAS_PREDIV)
 481                __raw_writel(prediv, pll->base + PREDIV);
 482
 483        __raw_writel(mult, pll->base + PLLM);
 484
 485        if (pll->flags & PLL_HAS_POSTDIV)
 486                __raw_writel(postdiv, pll->base + POSTDIV);
 487
 488        udelay(PLL_RESET_TIME);
 489
 490        /* Bring PLL out of reset */
 491        ctrl |= PLLCTL_PLLRST;
 492        __raw_writel(ctrl, pll->base + PLLCTL);
 493
 494        udelay(locktime);
 495
 496        /* Remove PLL from bypass mode */
 497        ctrl |= PLLCTL_PLLEN;
 498        __raw_writel(ctrl, pll->base + PLLCTL);
 499
 500        spin_unlock_irqrestore(&clockfw_lock, flags);
 501
 502        return 0;
 503}
 504EXPORT_SYMBOL(davinci_set_pllrate);
 505
 506/**
 507 * davinci_set_refclk_rate() - Set the reference clock rate
 508 * @rate:       The new rate.
 509 *
 510 * Sets the reference clock rate to a given value. This will most likely
 511 * result in the entire clock tree getting updated.
 512 *
 513 * This is used to support boards which use a reference clock different
 514 * than that used by default in <soc>.c file. The reference clock rate
 515 * should be updated early in the boot process; ideally soon after the
 516 * clock tree has been initialized once with the default reference clock
 517 * rate (davinci_common_init()).
 518 *
 519 * Returns 0 on success, error otherwise.
 520 */
 521int davinci_set_refclk_rate(unsigned long rate)
 522{
 523        struct clk *refclk;
 524
 525        refclk = clk_get(NULL, "ref");
 526        if (IS_ERR(refclk)) {
 527                pr_err("%s: failed to get reference clock.\n", __func__);
 528                return PTR_ERR(refclk);
 529        }
 530
 531        clk_set_rate(refclk, rate);
 532
 533        clk_put(refclk);
 534
 535        return 0;
 536}
 537
 538int __init davinci_clk_init(struct clk_lookup *clocks)
 539  {
 540        struct clk_lookup *c;
 541        struct clk *clk;
 542        size_t num_clocks = 0;
 543
 544        for (c = clocks; c->clk; c++) {
 545                clk = c->clk;
 546
 547                if (!clk->recalc) {
 548
 549                        /* Check if clock is a PLL */
 550                        if (clk->pll_data)
 551                                clk->recalc = clk_pllclk_recalc;
 552
 553                        /* Else, if it is a PLL-derived clock */
 554                        else if (clk->flags & CLK_PLL)
 555                                clk->recalc = clk_sysclk_recalc;
 556
 557                        /* Otherwise, it is a leaf clock (PSC clock) */
 558                        else if (clk->parent)
 559                                clk->recalc = clk_leafclk_recalc;
 560                }
 561
 562                if (clk->pll_data) {
 563                        struct pll_data *pll = clk->pll_data;
 564
 565                        if (!pll->div_ratio_mask)
 566                                pll->div_ratio_mask = PLLDIV_RATIO_MASK;
 567
 568                        if (pll->phys_base && !pll->base) {
 569                                pll->base = ioremap(pll->phys_base, SZ_4K);
 570                                WARN_ON(!pll->base);
 571                        }
 572                }
 573
 574                if (clk->recalc)
 575                        clk->rate = clk->recalc(clk);
 576
 577                if (clk->lpsc)
 578                        clk->flags |= CLK_PSC;
 579
 580                clk_register(clk);
 581                num_clocks++;
 582
 583                /* Turn on clocks that Linux doesn't otherwise manage */
 584                if (clk->flags & ALWAYS_ENABLED)
 585                        clk_enable(clk);
 586        }
 587
 588        clkdev_add_table(clocks, num_clocks);
 589
 590        return 0;
 591}
 592
 593#ifdef CONFIG_DEBUG_FS
 594
 595#include <linux/debugfs.h>
 596#include <linux/seq_file.h>
 597
 598#define CLKNAME_MAX     10              /* longest clock name */
 599#define NEST_DELTA      2
 600#define NEST_MAX        4
 601
 602static void
 603dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
 604{
 605        char            *state;
 606        char            buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
 607        struct clk      *clk;
 608        unsigned        i;
 609
 610        if (parent->flags & CLK_PLL)
 611                state = "pll";
 612        else if (parent->flags & CLK_PSC)
 613                state = "psc";
 614        else
 615                state = "";
 616
 617        /* <nest spaces> name <pad to end> */
 618        memset(buf, ' ', sizeof(buf) - 1);
 619        buf[sizeof(buf) - 1] = 0;
 620        i = strlen(parent->name);
 621        memcpy(buf + nest, parent->name,
 622                        min(i, (unsigned)(sizeof(buf) - 1 - nest)));
 623
 624        seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
 625                   buf, parent->usecount, state, clk_get_rate(parent));
 626        /* REVISIT show device associations too */
 627
 628        /* cost is now small, but not linear... */
 629        list_for_each_entry(clk, &parent->children, childnode) {
 630                dump_clock(s, nest + NEST_DELTA, clk);
 631        }
 632}
 633
 634static int davinci_ck_show(struct seq_file *m, void *v)
 635{
 636        struct clk *clk;
 637
 638        /*
 639         * Show clock tree; We trust nonzero usecounts equate to PSC enables...
 640         */
 641        mutex_lock(&clocks_mutex);
 642        list_for_each_entry(clk, &clocks, node)
 643                if (!clk->parent)
 644                        dump_clock(m, 0, clk);
 645        mutex_unlock(&clocks_mutex);
 646
 647        return 0;
 648}
 649
 650static int davinci_ck_open(struct inode *inode, struct file *file)
 651{
 652        return single_open(file, davinci_ck_show, NULL);
 653}
 654
 655static const struct file_operations davinci_ck_operations = {
 656        .open           = davinci_ck_open,
 657        .read           = seq_read,
 658        .llseek         = seq_lseek,
 659        .release        = single_release,
 660};
 661
 662static int __init davinci_clk_debugfs_init(void)
 663{
 664        debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
 665                                                &davinci_ck_operations);
 666        return 0;
 667
 668}
 669device_initcall(davinci_clk_debugfs_init);
 670#endif /* CONFIG_DEBUG_FS */
 671