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11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <video/vga.h>
14#include <asm/mach/pci.h>
15#include <asm/mach/arch.h>
16#include <asm/setup.h>
17#include <asm/delay.h>
18#include <plat/pcie.h>
19#include <mach/irqs.h>
20#include <mach/bridge-regs.h>
21#include <plat/addr-map.h>
22#include "common.h"
23
24struct pcie_port {
25 u8 index;
26 u8 root_bus_nr;
27 void __iomem *base;
28 spinlock_t conf_lock;
29 char io_space_name[16];
30 char mem_space_name[16];
31 struct resource res[2];
32};
33
34static struct pcie_port pcie_port[2];
35static int num_pcie_ports;
36
37
38static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
39{
40 struct pcie_port *pp;
41
42 if (nr >= num_pcie_ports)
43 return 0;
44
45 pp = &pcie_port[nr];
46 pp->root_bus_nr = sys->busnr;
47
48
49
50
51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
52
53 orion_pcie_setup(pp->base);
54
55
56
57
58 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
59 "PCIe %d I/O", pp->index);
60 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
61 pp->res[0].name = pp->io_space_name;
62 if (pp->index == 0) {
63 pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
64 pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
65 } else {
66 pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
67 pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
68 }
69 pp->res[0].flags = IORESOURCE_IO;
70 if (request_resource(&ioport_resource, &pp->res[0]))
71 panic("Request PCIe IO resource failed\n");
72 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
73
74
75
76
77 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
78 "PCIe %d MEM", pp->index);
79 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
80 pp->res[1].name = pp->mem_space_name;
81 if (pp->index == 0) {
82 pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
83 pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
84 } else {
85 pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
86 pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
87 }
88 pp->res[1].flags = IORESOURCE_MEM;
89 if (request_resource(&iomem_resource, &pp->res[1]))
90 panic("Request PCIe Memory resource failed\n");
91 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
92
93 return 1;
94}
95
96static struct pcie_port *bus_to_port(int bus)
97{
98 int i;
99
100 for (i = num_pcie_ports - 1; i >= 0; i--) {
101 int rbus = pcie_port[i].root_bus_nr;
102 if (rbus != -1 && rbus <= bus)
103 break;
104 }
105
106 return i >= 0 ? pcie_port + i : NULL;
107}
108
109static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
110{
111
112
113
114
115 if (bus == pp->root_bus_nr && dev > 1)
116 return 0;
117
118 return 1;
119}
120
121static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
122 int size, u32 *val)
123{
124 struct pcie_port *pp = bus_to_port(bus->number);
125 unsigned long flags;
126 int ret;
127
128 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
129 *val = 0xffffffff;
130 return PCIBIOS_DEVICE_NOT_FOUND;
131 }
132
133 spin_lock_irqsave(&pp->conf_lock, flags);
134 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
135 spin_unlock_irqrestore(&pp->conf_lock, flags);
136
137 return ret;
138}
139
140static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
141 int where, int size, u32 val)
142{
143 struct pcie_port *pp = bus_to_port(bus->number);
144 unsigned long flags;
145 int ret;
146
147 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
148 return PCIBIOS_DEVICE_NOT_FOUND;
149
150 spin_lock_irqsave(&pp->conf_lock, flags);
151 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
152 spin_unlock_irqrestore(&pp->conf_lock, flags);
153
154 return ret;
155}
156
157static struct pci_ops pcie_ops = {
158 .read = pcie_rd_conf,
159 .write = pcie_wr_conf,
160};
161
162static void __devinit rc_pci_fixup(struct pci_dev *dev)
163{
164
165
166
167 if (dev->bus->parent == NULL && dev->devfn == 0) {
168 int i;
169
170 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
171 dev->resource[i].start = 0;
172 dev->resource[i].end = 0;
173 dev->resource[i].flags = 0;
174 }
175 }
176}
177DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
178
179static struct pci_bus __init *
180dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
181{
182 struct pci_bus *bus;
183
184 if (nr < num_pcie_ports) {
185 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
186 &sys->resources);
187 } else {
188 bus = NULL;
189 BUG();
190 }
191
192 return bus;
193}
194
195static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
196{
197 struct pcie_port *pp = bus_to_port(dev->bus->number);
198
199 return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
200}
201
202static struct hw_pci dove_pci __initdata = {
203 .nr_controllers = 2,
204 .swizzle = pci_std_swizzle,
205 .setup = dove_pcie_setup,
206 .scan = dove_pcie_scan_bus,
207 .map_irq = dove_pcie_map_irq,
208};
209
210static void __init add_pcie_port(int index, unsigned long base)
211{
212 printk(KERN_INFO "Dove PCIe port %d: ", index);
213
214 if (orion_pcie_link_up((void __iomem *)base)) {
215 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
216
217 printk(KERN_INFO "link up\n");
218
219 pp->index = index;
220 pp->root_bus_nr = -1;
221 pp->base = (void __iomem *)base;
222 spin_lock_init(&pp->conf_lock);
223 memset(pp->res, 0, sizeof(pp->res));
224 } else {
225 printk(KERN_INFO "link down, ignoring\n");
226 }
227}
228
229void __init dove_pcie_init(int init_port0, int init_port1)
230{
231 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
232
233 if (init_port0)
234 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
235
236 if (init_port1)
237 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
238
239 pci_common_init(&dove_pci);
240}
241
