LXR linux/arch/arm/mach-orion5x/addr-map.c

   1/*
   2 * arch/arm/mach-orion5x/addr-map.c
   3 *
   4 * Address map functions for Marvell Orion 5x SoCs
   5 *
   6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7 *
   8 * This file is licensed under the terms of the GNU General Public
   9 * License version 2.  This program is licensed "as is" without any
  10 * warranty of any kind, whether express or implied.
  11 */
  12
  13#include <linux/kernel.h>
  14#include <linux/init.h>
  15#include <linux/mbus.h>
  16#include <linux/io.h>
  17#include <mach/hardware.h>
  18#include <plat/addr-map.h>
  19#include "common.h"
  20
  21/*
  22 * The Orion has fully programmable address map. There's a separate address
  23 * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
  24 * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
  25 * address decode windows that allow it to access any of the Orion resources.
  26 *
  27 * CPU address decoding --
  28 * Linux assumes that it is the boot loader that already setup the access to
  29 * DDR and internal registers.
  30 * Setup access to PCI and PCIe IO/MEM space is issued by this file.
  31 * Setup access to various devices located on the device bus interface (e.g.
  32 * flashes, RTC, etc) should be issued by machine-setup.c according to
  33 * specific board population (by using orion5x_setup_*_win()).
  34 *
  35 * Non-CPU Masters address decoding --
  36 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
  37 * banks only (the typical use case).
  38 * Setup access for each master to DDR is issued by platform device setup.
  39 */
  40
  41/*
  42 * Generic Address Decode Windows bit settings
  43 */
  44#define TARGET_DEV_BUS          1
  45#define TARGET_PCI              3
  46#define TARGET_PCIE             4
  47#define TARGET_SRAM             9
  48#define ATTR_PCIE_MEM           0x59
  49#define ATTR_PCIE_IO            0x51
  50#define ATTR_PCIE_WA            0x79
  51#define ATTR_PCI_MEM            0x59
  52#define ATTR_PCI_IO             0x51
  53#define ATTR_DEV_CS0            0x1e
  54#define ATTR_DEV_CS1            0x1d
  55#define ATTR_DEV_CS2            0x1b
  56#define ATTR_DEV_BOOT           0xf
  57#define ATTR_SRAM               0x0
  58
  59static int __initdata win_alloc_count;
  60
  61static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
  62                  const int win)
  63{
  64        u32 dev, rev;
  65
  66        orion5x_pcie_id(&dev, &rev);
  67        if ((dev == MV88F5281_DEV_ID && win < 4)
  68            || (dev == MV88F5182_DEV_ID && win < 2)
  69            || (dev == MV88F5181_DEV_ID && win < 2)
  70            || (dev == MV88F6183_DEV_ID && win < 4))
  71                return 1;
  72
  73        return 0;
  74}
  75
  76/*
  77 * Description of the windows needed by the platform code
  78 */
  79static struct __initdata orion_addr_map_cfg addr_map_cfg = {
  80        .num_wins = 8,
  81        .cpu_win_can_remap = cpu_win_can_remap,
  82        .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
  83};
  84
  85static const struct __initdata orion_addr_map_info addr_map_info[] = {
  86        /*
  87         * Setup windows for PCI+PCIe IO+MEM space.
  88         */
  89        { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
  90          TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
  91        },
  92        { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
  93          TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
  94        },
  95        { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
  96          TARGET_PCIE, ATTR_PCIE_MEM, -1
  97        },
  98        { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
  99          TARGET_PCI, ATTR_PCI_MEM, -1
 100        },
 101        /* End marker */
 102        { -1, 0, 0, 0, 0, 0 }
 103};
 104
 105void __init orion5x_setup_cpu_mbus_bridge(void)
 106{
 107        /*
 108         * Disable, clear and configure windows.
 109         */
 110        orion_config_wins(&addr_map_cfg, addr_map_info);
 111        win_alloc_count = 4;
 112
 113        /*
 114         * Setup MBUS dram target info.
 115         */
 116        orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
 117}
 118
 119void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 120{
 121        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
 122                            TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 123}
 124
 125void __init orion5x_setup_dev0_win(u32 base, u32 size)
 126{
 127        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
 128                            TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 129}
 130
 131void __init orion5x_setup_dev1_win(u32 base, u32 size)
 132{
 133        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
 134                            TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 135}
 136
 137void __init orion5x_setup_dev2_win(u32 base, u32 size)
 138{
 139        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
 140                            TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 141}
 142
 143void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 144{
 145        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
 146                            TARGET_PCIE, ATTR_PCIE_WA, -1);
 147}
 148
 149void __init orion5x_setup_sram_win(void)
 150{
 151        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
 152                            ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
 153                            TARGET_SRAM, ATTR_SRAM, -1);
 154}
 155