1
2
3
4
5
6
7
8
9
10
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14
15#define GPMC_CS_NUM 8
16
17#define GPMC_CS_CONFIG1 0x00
18#define GPMC_CS_CONFIG2 0x04
19#define GPMC_CS_CONFIG3 0x08
20#define GPMC_CS_CONFIG4 0x0c
21#define GPMC_CS_CONFIG5 0x10
22#define GPMC_CS_CONFIG6 0x14
23#define GPMC_CS_CONFIG7 0x18
24#define GPMC_CS_NAND_COMMAND 0x1c
25#define GPMC_CS_NAND_ADDRESS 0x20
26#define GPMC_CS_NAND_DATA 0x24
27
28
29#define GPMC_CONFIG_RDY_BSY 0x00000001
30#define GPMC_CONFIG_DEV_SIZE 0x00000002
31#define GPMC_CONFIG_DEV_TYPE 0x00000003
32#define GPMC_SET_IRQ_STATUS 0x00000004
33#define GPMC_CONFIG_WP 0x00000005
34
35#define GPMC_GET_IRQ_STATUS 0x00000006
36#define GPMC_PREFETCH_FIFO_CNT 0x00000007
37#define GPMC_PREFETCH_COUNT 0x00000008
38#define GPMC_STATUS_BUFFER 0x00000009
39
40#define GPMC_NAND_COMMAND 0x0000000a
41#define GPMC_NAND_ADDRESS 0x0000000b
42#define GPMC_NAND_DATA 0x0000000c
43
44#define GPMC_ENABLE_IRQ 0x0000000d
45
46
47#define GPMC_ECC_READ 0
48#define GPMC_ECC_WRITE 1
49#define GPMC_ECC_READSYN 2
50
51#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
52#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
53#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
54#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
55#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
56#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
57#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
58#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
59#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
60#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
61#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
62#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
63#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
64#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
65#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
66#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
67#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
68#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
69#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
70#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
71#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
72#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
73#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
74#define GPMC_CONFIG7_CSVALID (1 << 6)
75
76#define GPMC_DEVICETYPE_NOR 0
77#define GPMC_DEVICETYPE_NAND 2
78#define GPMC_CONFIG_WRITEPROTECT 0x00000010
79#define GPMC_STATUS_BUFF_EMPTY 0x00000001
80#define WR_RD_PIN_MONITORING 0x00600000
81#define GPMC_PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
82#define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
83#define GPMC_IRQ_FIFOEVENTENABLE 0x01
84#define GPMC_IRQ_COUNT_EVENT 0x02
85
86#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
87#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
88
89enum omap_ecc {
90
91 OMAP_ECC_HAMMING_CODE_DEFAULT = 0,
92 OMAP_ECC_HAMMING_CODE_HW,
93
94 OMAP_ECC_HAMMING_CODE_HW_ROMCODE,
95};
96
97
98
99
100
101struct gpmc_timings {
102
103 u32 sync_clk;
104
105
106 u16 cs_on;
107 u16 cs_rd_off;
108 u16 cs_wr_off;
109
110
111 u16 adv_on;
112 u16 adv_rd_off;
113 u16 adv_wr_off;
114
115
116 u16 we_on;
117 u16 we_off;
118
119
120 u16 oe_on;
121 u16 oe_off;
122
123
124 u16 page_burst_access;
125 u16 access;
126 u16 rd_cycle;
127 u16 wr_cycle;
128
129
130 u16 wr_access;
131 u16 wr_data_mux_bus;
132};
133
134extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
135extern unsigned int gpmc_ps_to_ticks(unsigned int time_ps);
136extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
137extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
138extern unsigned long gpmc_get_fclk_period(void);
139
140extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
141extern u32 gpmc_cs_read_reg(int cs, int idx);
142extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
143extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
144extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
145extern void gpmc_cs_free(int cs);
146extern int gpmc_cs_set_reserved(int cs, int reserved);
147extern int gpmc_cs_reserved(int cs);
148extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
149 unsigned int u32_count, int is_write);
150extern int gpmc_prefetch_reset(int cs);
151extern void omap3_gpmc_save_context(void);
152extern void omap3_gpmc_restore_context(void);
153extern int gpmc_read_status(int cmd);
154extern int gpmc_cs_configure(int cs, int cmd, int wval);
155extern int gpmc_nand_read(int cs, int cmd);
156extern int gpmc_nand_write(int cs, int cmd, int wval);
157
158int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size);
159int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code);
160#endif
161