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9#include <linux/debugfs.h>
10#include <linux/fs.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13
14#include <asm/blackfin.h>
15#include <asm/gpio.h>
16#include <asm/gptimers.h>
17#include <asm/bfin_can.h>
18#include <asm/bfin_dma.h>
19#include <asm/bfin_ppi.h>
20#include <asm/bfin_serial.h>
21#include <asm/bfin5xx_spi.h>
22#include <asm/bfin_twi.h>
23
24
25#ifdef BFIN_PORT_MUX
26#undef PORT_MUX
27#define PORT_MUX BFIN_PORT_MUX
28#endif
29
30#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)(addr))
31#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
32#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
33#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
34
35#define D_RO(name, bits) d_RO(#name, bits, name)
36#define D_WO(name, bits) d_WO(#name, bits, name)
37#define D32(name) d(#name, 32, name)
38#define D16(name) d(#name, 16, name)
39
40#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
41#define __REGS(peri, sname, rname) \
42 do { \
43 struct bfin_##peri##_regs r; \
44 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
45 strcpy(_buf, sname); \
46 if (sizeof(r.rname) == 2) \
47 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
48 else \
49 debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
50 } while (0)
51#define REGS_STR_PFX(buf, pfx, num) \
52 ({ \
53 buf + (num >= 0 ? \
54 sprintf(buf, #pfx "%i_", num) : \
55 sprintf(buf, #pfx "_")); \
56 })
57#define REGS_STR_PFX_C(buf, pfx, num) \
58 ({ \
59 buf + (num >= 0 ? \
60 sprintf(buf, #pfx "%c_", 'A' + num) : \
61 sprintf(buf, #pfx "_")); \
62 })
63
64
65
66
67extern u32 last_seqstat;
68
69static int debug_cclk_get(void *data, u64 *val)
70{
71 *val = get_cclk();
72 return 0;
73}
74DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
75
76static int debug_sclk_get(void *data, u64 *val)
77{
78 *val = get_sclk();
79 return 0;
80}
81DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
82
83#define DEFINE_SYSREG(sr, pre, post) \
84static int sysreg_##sr##_get(void *data, u64 *val) \
85{ \
86 unsigned long tmp; \
87 pre; \
88 __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
89 *val = tmp; \
90 return 0; \
91} \
92static int sysreg_##sr##_set(void *data, u64 val) \
93{ \
94 unsigned long tmp = val; \
95 __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
96 post; \
97 return 0; \
98} \
99DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
100
101DEFINE_SYSREG(cycles, , );
102DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
103DEFINE_SYSREG(emudat, , );
104DEFINE_SYSREG(seqstat, , );
105DEFINE_SYSREG(syscfg, , CSYNC());
106#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
107
108
109
110
111#define CAN_OFF(mmr) REGS_OFF(can, mmr)
112#define __CAN(uname, lname) __REGS(can, #uname, lname)
113static void __init __maybe_unused
114bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
115{
116 static struct dentry *am, *mb;
117 int i, j;
118 char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
119
120 if (!am) {
121 am = debugfs_create_dir("am", parent);
122 mb = debugfs_create_dir("mb", parent);
123 }
124
125 __CAN(MC1, mc1);
126 __CAN(MD1, md1);
127 __CAN(TRS1, trs1);
128 __CAN(TRR1, trr1);
129 __CAN(TA1, ta1);
130 __CAN(AA1, aa1);
131 __CAN(RMP1, rmp1);
132 __CAN(RML1, rml1);
133 __CAN(MBTIF1, mbtif1);
134 __CAN(MBRIF1, mbrif1);
135 __CAN(MBIM1, mbim1);
136 __CAN(RFH1, rfh1);
137 __CAN(OPSS1, opss1);
138
139 __CAN(MC2, mc2);
140 __CAN(MD2, md2);
141 __CAN(TRS2, trs2);
142 __CAN(TRR2, trr2);
143 __CAN(TA2, ta2);
144 __CAN(AA2, aa2);
145 __CAN(RMP2, rmp2);
146 __CAN(RML2, rml2);
147 __CAN(MBTIF2, mbtif2);
148 __CAN(MBRIF2, mbrif2);
149 __CAN(MBIM2, mbim2);
150 __CAN(RFH2, rfh2);
151 __CAN(OPSS2, opss2);
152
153 __CAN(CLOCK, clock);
154 __CAN(TIMING, timing);
155 __CAN(DEBUG, debug);
156 __CAN(STATUS, status);
157 __CAN(CEC, cec);
158 __CAN(GIS, gis);
159 __CAN(GIM, gim);
160 __CAN(GIF, gif);
161 __CAN(CONTROL, control);
162 __CAN(INTR, intr);
163 __CAN(VERSION, version);
164 __CAN(MBTD, mbtd);
165 __CAN(EWR, ewr);
166 __CAN(ESR, esr);
167
168 __CAN(UCCNT, uccnt);
169 __CAN(UCRC, ucrc);
170 __CAN(UCCNF, uccnf);
171 __CAN(VERSION2, version2);
172
173 for (i = 0; i < 32; ++i) {
174 sprintf(_buf, "AM%02iL", i);
175 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
176 (u16 *)(base + CAN_OFF(msk[i].aml)));
177 sprintf(_buf, "AM%02iH", i);
178 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
179 (u16 *)(base + CAN_OFF(msk[i].amh)));
180
181 for (j = 0; j < 3; ++j) {
182 sprintf(_buf, "MB%02i_DATA%i", i, j);
183 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
184 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
185 }
186 sprintf(_buf, "MB%02i_LENGTH", i);
187 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
188 (u16 *)(base + CAN_OFF(chl[i].dlc)));
189 sprintf(_buf, "MB%02i_TIMESTAMP", i);
190 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
191 (u16 *)(base + CAN_OFF(chl[i].tsv)));
192 sprintf(_buf, "MB%02i_ID0", i);
193 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
194 (u16 *)(base + CAN_OFF(chl[i].id0)));
195 sprintf(_buf, "MB%02i_ID1", i);
196 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
197 (u16 *)(base + CAN_OFF(chl[i].id1)));
198 }
199}
200#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
201
202
203
204
205#define __DMA(uname, lname) __REGS(dma, #uname, lname)
206static void __init __maybe_unused
207bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
208{
209 char buf[32], *_buf;
210
211 if (mdma)
212 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
213 else
214 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
215
216 __DMA(NEXT_DESC_PTR, next_desc_ptr);
217 __DMA(START_ADDR, start_addr);
218 __DMA(CONFIG, config);
219 __DMA(X_COUNT, x_count);
220 __DMA(X_MODIFY, x_modify);
221 __DMA(Y_COUNT, y_count);
222 __DMA(Y_MODIFY, y_modify);
223 __DMA(CURR_DESC_PTR, curr_desc_ptr);
224 __DMA(CURR_ADDR, curr_addr);
225 __DMA(IRQ_STATUS, irq_status);
226 if (strcmp(pfx, "IMDMA") != 0)
227 __DMA(PERIPHERAL_MAP, peripheral_map);
228 __DMA(CURR_X_COUNT, curr_x_count);
229 __DMA(CURR_Y_COUNT, curr_y_count);
230}
231#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
232#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
233#define _MDMA(num, x) \
234 do { \
235 _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
236 _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
237 } while (0)
238#define MDMA(num) _MDMA(num, M)
239#define IMDMA(num) _MDMA(num, IM)
240
241
242
243
244#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
245static void __init __maybe_unused
246bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
247{
248 char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
249 __EPPI(STATUS, status);
250 __EPPI(HCOUNT, hcount);
251 __EPPI(HDELAY, hdelay);
252 __EPPI(VCOUNT, vcount);
253 __EPPI(VDELAY, vdelay);
254 __EPPI(FRAME, frame);
255 __EPPI(LINE, line);
256 __EPPI(CLKDIV, clkdiv);
257 __EPPI(CONTROL, control);
258 __EPPI(FS1W_HBL, fs1w_hbl);
259 __EPPI(FS1P_AVPL, fs1p_avpl);
260 __EPPI(FS2W_LVB, fs2w_lvb);
261 __EPPI(FS2P_LAVF, fs2p_lavf);
262 __EPPI(CLIP, clip);
263}
264#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
265
266
267
268
269#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
270static void __init __maybe_unused
271bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
272{
273 char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
274 __GPTIMER(CONFIG, config);
275 __GPTIMER(COUNTER, counter);
276 __GPTIMER(PERIOD, period);
277 __GPTIMER(WIDTH, width);
278}
279#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
280
281#define GPTIMER_GROUP_OFF(mmr) REGS_OFF(gptimer_group, mmr)
282#define __GPTIMER_GROUP(uname, lname) __REGS(gptimer_group, #uname, lname)
283static void __init __maybe_unused
284bfin_debug_mmrs_gptimer_group(struct dentry *parent, unsigned long base, int num)
285{
286 char buf[32], *_buf;
287
288 if (num == -1) {
289 _buf = buf + sprintf(buf, "TIMER_");
290 __GPTIMER_GROUP(ENABLE, enable);
291 __GPTIMER_GROUP(DISABLE, disable);
292 __GPTIMER_GROUP(STATUS, status);
293 } else {
294
295 _buf = buf + sprintf(buf, "TIMER_ENABLE%i", num);
296 d(buf, 16, base + GPTIMER_GROUP_OFF(enable));
297
298 _buf = buf + sprintf(buf, "TIMER_DISABLE%i", num);
299 d(buf, 16, base + GPTIMER_GROUP_OFF(disable));
300
301 _buf = buf + sprintf(buf, "TIMER_STATUS%i", num);
302 d(buf, 32, base + GPTIMER_GROUP_OFF(status));
303 }
304}
305#define GPTIMER_GROUP(mmr, num) bfin_debug_mmrs_gptimer_group(parent, mmr, num)
306
307
308
309
310#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
311static void __init __maybe_unused
312bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
313{
314 char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
315 __HMDMA(CONTROL, control);
316 __HMDMA(ECINIT, ecinit);
317 __HMDMA(BCINIT, bcinit);
318 __HMDMA(ECURGENT, ecurgent);
319 __HMDMA(ECOVERFLOW, ecoverflow);
320 __HMDMA(ECOUNT, ecount);
321 __HMDMA(BCOUNT, bcount);
322}
323#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
324
325
326
327
328#ifdef PINT0_MASK_SET
329#define __PINT(uname, lname) __REGS(pint, #uname, lname)
330static void __init __maybe_unused
331bfin_debug_mmrs_pint(struct dentry *parent, unsigned long base, int num)
332{
333 char buf[32], *_buf = REGS_STR_PFX(buf, PINT, num);
334 __PINT(MASK_SET, mask_set);
335 __PINT(MASK_CLEAR, mask_clear);
336 __PINT(REQUEST, request);
337 __PINT(ASSIGN, assign);
338 __PINT(EDGE_SET, edge_set);
339 __PINT(EDGE_CLEAR, edge_clear);
340 __PINT(INVERT_SET, invert_set);
341 __PINT(INVERT_CLEAR, invert_clear);
342 __PINT(PINSTATE, pinstate);
343 __PINT(LATCH, latch);
344}
345#define PINT(num) bfin_debug_mmrs_pint(parent, PINT##num##_MASK_SET, num)
346#endif
347
348
349
350
351#define bfin_gpio_regs gpio_port_t
352#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
353static void __init __maybe_unused
354bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
355{
356 char buf[32], *_buf;
357#ifdef __ADSPBF54x__
358 _buf = REGS_STR_PFX_C(buf, PORT, num);
359 __PORT(FER, port_fer);
360 __PORT(SET, data_set);
361 __PORT(CLEAR, data_clear);
362 __PORT(DIR_SET, dir_set);
363 __PORT(DIR_CLEAR, dir_clear);
364 __PORT(INEN, inen);
365 __PORT(MUX, port_mux);
366#else
367 _buf = buf + sprintf(buf, "PORT%cIO_", num);
368 __PORT(CLEAR, data_clear);
369 __PORT(SET, data_set);
370 __PORT(TOGGLE, toggle);
371 __PORT(MASKA, maska);
372 __PORT(MASKA_CLEAR, maska_clear);
373 __PORT(MASKA_SET, maska_set);
374 __PORT(MASKA_TOGGLE, maska_toggle);
375 __PORT(MASKB, maskb);
376 __PORT(MASKB_CLEAR, maskb_clear);
377 __PORT(MASKB_SET, maskb_set);
378 __PORT(MASKB_TOGGLE, maskb_toggle);
379 __PORT(DIR, dir);
380 __PORT(POLAR, polar);
381 __PORT(EDGE, edge);
382 __PORT(BOTH, both);
383 __PORT(INEN, inen);
384#endif
385 _buf[-1] = '\0';
386 d(buf, 16, base + REGS_OFF(gpio, data));
387}
388#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
389
390
391
392
393#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
394static void __init __maybe_unused
395bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
396{
397 char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
398 __PPI(CONTROL, control);
399 __PPI(STATUS, status);
400 __PPI(COUNT, count);
401 __PPI(DELAY, delay);
402 __PPI(FRAME, frame);
403}
404#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
405
406
407
408
409#define __SPI(uname, lname) __REGS(spi, #uname, lname)
410static void __init __maybe_unused
411bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
412{
413 char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
414 __SPI(CTL, ctl);
415 __SPI(FLG, flg);
416 __SPI(STAT, stat);
417 __SPI(TDBR, tdbr);
418 __SPI(RDBR, rdbr);
419 __SPI(BAUD, baud);
420 __SPI(SHADOW, shadow);
421}
422#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
423
424
425
426
427static inline int sport_width(void *mmr)
428{
429 unsigned long lmmr = (unsigned long)mmr;
430 if ((lmmr & 0xff) == 0x10)
431
432 lmmr -= 0xc;
433 else
434
435 lmmr += 0xc;
436
437 return (bfin_read16(lmmr) & 0x1f) + 1;
438}
439static int sport_set(void *mmr, u64 val)
440{
441 unsigned long flags;
442 local_irq_save(flags);
443 if (sport_width(mmr) <= 16)
444 bfin_write16(mmr, val);
445 else
446 bfin_write32(mmr, val);
447 local_irq_restore(flags);
448 return 0;
449}
450static int sport_get(void *mmr, u64 *val)
451{
452 unsigned long flags;
453 local_irq_save(flags);
454 if (sport_width(mmr) <= 16)
455 *val = bfin_read16(mmr);
456 else
457 *val = bfin_read32(mmr);
458 local_irq_restore(flags);
459 return 0;
460}
461DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
462
463DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
464#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
465#define _D_SPORT(name, perms, fops) \
466 do { \
467 strcpy(_buf, #name); \
468 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
469 } while (0)
470#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
471#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
472#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
473#define __SPORT(name, bits) \
474 do { \
475 strcpy(_buf, #name); \
476 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
477 } while (0)
478static void __init __maybe_unused
479bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
480{
481 char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
482 __SPORT(CHNL, 16);
483 __SPORT(MCMC1, 16);
484 __SPORT(MCMC2, 16);
485 __SPORT(MRCS0, 32);
486 __SPORT(MRCS1, 32);
487 __SPORT(MRCS2, 32);
488 __SPORT(MRCS3, 32);
489 __SPORT(MTCS0, 32);
490 __SPORT(MTCS1, 32);
491 __SPORT(MTCS2, 32);
492 __SPORT(MTCS3, 32);
493 __SPORT(RCLKDIV, 16);
494 __SPORT(RCR1, 16);
495 __SPORT(RCR2, 16);
496 __SPORT(RFSDIV, 16);
497 __SPORT_RW(RX);
498 __SPORT(STAT, 16);
499 __SPORT(TCLKDIV, 16);
500 __SPORT(TCR1, 16);
501 __SPORT(TCR2, 16);
502 __SPORT(TFSDIV, 16);
503 __SPORT_WO(TX);
504}
505#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
506
507
508
509
510#define __TWI(uname, lname) __REGS(twi, #uname, lname)
511static void __init __maybe_unused
512bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
513{
514 char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
515 __TWI(CLKDIV, clkdiv);
516 __TWI(CONTROL, control);
517 __TWI(SLAVE_CTL, slave_ctl);
518 __TWI(SLAVE_STAT, slave_stat);
519 __TWI(SLAVE_ADDR, slave_addr);
520 __TWI(MASTER_CTL, master_ctl);
521 __TWI(MASTER_STAT, master_stat);
522 __TWI(MASTER_ADDR, master_addr);
523 __TWI(INT_STAT, int_stat);
524 __TWI(INT_MASK, int_mask);
525 __TWI(FIFO_CTL, fifo_ctl);
526 __TWI(FIFO_STAT, fifo_stat);
527 __TWI(XMT_DATA8, xmt_data8);
528 __TWI(XMT_DATA16, xmt_data16);
529 __TWI(RCV_DATA8, rcv_data8);
530 __TWI(RCV_DATA16, rcv_data16);
531}
532#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
533
534
535
536
537#define __UART(uname, lname) __REGS(uart, #uname, lname)
538static void __init __maybe_unused
539bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
540{
541 char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
542#ifdef BFIN_UART_BF54X_STYLE
543 __UART(DLL, dll);
544 __UART(DLH, dlh);
545 __UART(GCTL, gctl);
546 __UART(LCR, lcr);
547 __UART(MCR, mcr);
548 __UART(LSR, lsr);
549 __UART(MSR, msr);
550 __UART(SCR, scr);
551 __UART(IER_SET, ier_set);
552 __UART(IER_CLEAR, ier_clear);
553 __UART(THR, thr);
554 __UART(RBR, rbr);
555#else
556 __UART(DLL, dll);
557 __UART(THR, thr);
558 __UART(RBR, rbr);
559 __UART(DLH, dlh);
560 __UART(IER, ier);
561 __UART(IIR, iir);
562 __UART(LCR, lcr);
563 __UART(MCR, mcr);
564 __UART(LSR, lsr);
565 __UART(MSR, msr);
566 __UART(SCR, scr);
567 __UART(GCTL, gctl);
568#endif
569}
570#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
571
572
573
574
575static struct dentry *debug_mmrs_dentry;
576
577static int __init bfin_debug_mmrs_init(void)
578{
579 struct dentry *top, *parent;
580
581 pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
582
583 top = debugfs_create_dir("blackfin", NULL);
584 if (top == NULL)
585 return -1;
586
587 parent = debugfs_create_dir("core_regs", top);
588 debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
589 debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
590 debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
591 D_SYSREG(cycles);
592 D_SYSREG(cycles2);
593 D_SYSREG(emudat);
594 D_SYSREG(seqstat);
595 D_SYSREG(syscfg);
596
597
598 parent = debugfs_create_dir("ctimer", top);
599 D32(TCNTL);
600 D32(TCOUNT);
601 D32(TPERIOD);
602 D32(TSCALE);
603
604 parent = debugfs_create_dir("cec", top);
605 D32(EVT0);
606 D32(EVT1);
607 D32(EVT2);
608 D32(EVT3);
609 D32(EVT4);
610 D32(EVT5);
611 D32(EVT6);
612 D32(EVT7);
613 D32(EVT8);
614 D32(EVT9);
615 D32(EVT10);
616 D32(EVT11);
617 D32(EVT12);
618 D32(EVT13);
619 D32(EVT14);
620 D32(EVT15);
621 D32(EVT_OVERRIDE);
622 D32(IMASK);
623 D32(IPEND);
624 D32(ILAT);
625 D32(IPRIO);
626
627 parent = debugfs_create_dir("debug", top);
628 D32(DBGSTAT);
629 D32(DSPID);
630
631 parent = debugfs_create_dir("mmu", top);
632 D32(SRAM_BASE_ADDRESS);
633 D32(DCPLB_ADDR0);
634 D32(DCPLB_ADDR10);
635 D32(DCPLB_ADDR11);
636 D32(DCPLB_ADDR12);
637 D32(DCPLB_ADDR13);
638 D32(DCPLB_ADDR14);
639 D32(DCPLB_ADDR15);
640 D32(DCPLB_ADDR1);
641 D32(DCPLB_ADDR2);
642 D32(DCPLB_ADDR3);
643 D32(DCPLB_ADDR4);
644 D32(DCPLB_ADDR5);
645 D32(DCPLB_ADDR6);
646 D32(DCPLB_ADDR7);
647 D32(DCPLB_ADDR8);
648 D32(DCPLB_ADDR9);
649 D32(DCPLB_DATA0);
650 D32(DCPLB_DATA10);
651 D32(DCPLB_DATA11);
652 D32(DCPLB_DATA12);
653 D32(DCPLB_DATA13);
654 D32(DCPLB_DATA14);
655 D32(DCPLB_DATA15);
656 D32(DCPLB_DATA1);
657 D32(DCPLB_DATA2);
658 D32(DCPLB_DATA3);
659 D32(DCPLB_DATA4);
660 D32(DCPLB_DATA5);
661 D32(DCPLB_DATA6);
662 D32(DCPLB_DATA7);
663 D32(DCPLB_DATA8);
664 D32(DCPLB_DATA9);
665 D32(DCPLB_FAULT_ADDR);
666 D32(DCPLB_STATUS);
667 D32(DMEM_CONTROL);
668 D32(DTEST_COMMAND);
669 D32(DTEST_DATA0);
670 D32(DTEST_DATA1);
671
672 D32(ICPLB_ADDR0);
673 D32(ICPLB_ADDR1);
674 D32(ICPLB_ADDR2);
675 D32(ICPLB_ADDR3);
676 D32(ICPLB_ADDR4);
677 D32(ICPLB_ADDR5);
678 D32(ICPLB_ADDR6);
679 D32(ICPLB_ADDR7);
680 D32(ICPLB_ADDR8);
681 D32(ICPLB_ADDR9);
682 D32(ICPLB_ADDR10);
683 D32(ICPLB_ADDR11);
684 D32(ICPLB_ADDR12);
685 D32(ICPLB_ADDR13);
686 D32(ICPLB_ADDR14);
687 D32(ICPLB_ADDR15);
688 D32(ICPLB_DATA0);
689 D32(ICPLB_DATA1);
690 D32(ICPLB_DATA2);
691 D32(ICPLB_DATA3);
692 D32(ICPLB_DATA4);
693 D32(ICPLB_DATA5);
694 D32(ICPLB_DATA6);
695 D32(ICPLB_DATA7);
696 D32(ICPLB_DATA8);
697 D32(ICPLB_DATA9);
698 D32(ICPLB_DATA10);
699 D32(ICPLB_DATA11);
700 D32(ICPLB_DATA12);
701 D32(ICPLB_DATA13);
702 D32(ICPLB_DATA14);
703 D32(ICPLB_DATA15);
704 D32(ICPLB_FAULT_ADDR);
705 D32(ICPLB_STATUS);
706 D32(IMEM_CONTROL);
707 if (!ANOMALY_05000481) {
708 D32(ITEST_COMMAND);
709 D32(ITEST_DATA0);
710 D32(ITEST_DATA1);
711 }
712
713 parent = debugfs_create_dir("perf", top);
714 D32(PFCNTR0);
715 D32(PFCNTR1);
716 D32(PFCTL);
717
718 parent = debugfs_create_dir("trace", top);
719 D32(TBUF);
720 D32(TBUFCTL);
721 D32(TBUFSTAT);
722
723 parent = debugfs_create_dir("watchpoint", top);
724 D32(WPIACTL);
725 D32(WPIA0);
726 D32(WPIA1);
727 D32(WPIA2);
728 D32(WPIA3);
729 D32(WPIA4);
730 D32(WPIA5);
731 D32(WPIACNT0);
732 D32(WPIACNT1);
733 D32(WPIACNT2);
734 D32(WPIACNT3);
735 D32(WPIACNT4);
736 D32(WPIACNT5);
737 D32(WPDACTL);
738 D32(WPDA0);
739 D32(WPDA1);
740 D32(WPDACNT0);
741 D32(WPDACNT1);
742 D32(WPSTAT);
743
744
745#ifdef ATAPI_CONTROL
746 parent = debugfs_create_dir("atapi", top);
747 D16(ATAPI_CONTROL);
748 D16(ATAPI_DEV_ADDR);
749 D16(ATAPI_DEV_RXBUF);
750 D16(ATAPI_DEV_TXBUF);
751 D16(ATAPI_DMA_TFRCNT);
752 D16(ATAPI_INT_MASK);
753 D16(ATAPI_INT_STATUS);
754 D16(ATAPI_LINE_STATUS);
755 D16(ATAPI_MULTI_TIM_0);
756 D16(ATAPI_MULTI_TIM_1);
757 D16(ATAPI_MULTI_TIM_2);
758 D16(ATAPI_PIO_TFRCNT);
759 D16(ATAPI_PIO_TIM_0);
760 D16(ATAPI_PIO_TIM_1);
761 D16(ATAPI_REG_TIM_0);
762 D16(ATAPI_SM_STATE);
763 D16(ATAPI_STATUS);
764 D16(ATAPI_TERMINATE);
765 D16(ATAPI_UDMAOUT_TFRCNT);
766 D16(ATAPI_ULTRA_TIM_0);
767 D16(ATAPI_ULTRA_TIM_1);
768 D16(ATAPI_ULTRA_TIM_2);
769 D16(ATAPI_ULTRA_TIM_3);
770 D16(ATAPI_UMAIN_TFRCNT);
771 D16(ATAPI_XFER_LEN);
772#endif
773
774#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
775 parent = debugfs_create_dir("can", top);
776# ifdef CAN_MC1
777 bfin_debug_mmrs_can(parent, CAN_MC1, -1);
778# endif
779# ifdef CAN0_MC1
780 CAN(0);
781# endif
782# ifdef CAN1_MC1
783 CAN(1);
784# endif
785#endif
786
787#ifdef CNT_COMMAND
788 parent = debugfs_create_dir("counter", top);
789 D16(CNT_COMMAND);
790 D16(CNT_CONFIG);
791 D32(CNT_COUNTER);
792 D16(CNT_DEBOUNCE);
793 D16(CNT_IMASK);
794 D32(CNT_MAX);
795 D32(CNT_MIN);
796 D16(CNT_STATUS);
797#endif
798
799 parent = debugfs_create_dir("dmac", top);
800#ifdef DMAC_TC_CNT
801 D16(DMAC_TC_CNT);
802 D16(DMAC_TC_PER);
803#endif
804#ifdef DMAC0_TC_CNT
805 D16(DMAC0_TC_CNT);
806 D16(DMAC0_TC_PER);
807#endif
808#ifdef DMAC1_TC_CNT
809 D16(DMAC1_TC_CNT);
810 D16(DMAC1_TC_PER);
811#endif
812#ifdef DMAC1_PERIMUX
813 D16(DMAC1_PERIMUX);
814#endif
815
816#ifdef __ADSPBF561__
817
818# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
819# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
820# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
821# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
822# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
823# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
824# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
825# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
826# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
827# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
828# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
829# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
830# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
831# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
832# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
833# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
834# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
835# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
836# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
837# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
838# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
839# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
840# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
841# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
842#endif
843 parent = debugfs_create_dir("dma", top);
844 DMA(0);
845 DMA(1);
846 DMA(1);
847 DMA(2);
848 DMA(3);
849 DMA(4);
850 DMA(5);
851 DMA(6);
852 DMA(7);
853#ifdef DMA8_NEXT_DESC_PTR
854 DMA(8);
855 DMA(9);
856 DMA(10);
857 DMA(11);
858#endif
859#ifdef DMA12_NEXT_DESC_PTR
860 DMA(12);
861 DMA(13);
862 DMA(14);
863 DMA(15);
864 DMA(16);
865 DMA(17);
866 DMA(18);
867 DMA(19);
868#endif
869#ifdef DMA20_NEXT_DESC_PTR
870 DMA(20);
871 DMA(21);
872 DMA(22);
873 DMA(23);
874#endif
875
876 parent = debugfs_create_dir("ebiu_amc", top);
877 D32(EBIU_AMBCTL0);
878 D32(EBIU_AMBCTL1);
879 D16(EBIU_AMGCTL);
880#ifdef EBIU_MBSCTL
881 D16(EBIU_MBSCTL);
882 D32(EBIU_ARBSTAT);
883 D32(EBIU_MODE);
884 D16(EBIU_FCTL);
885#endif
886
887#ifdef EBIU_SDGCTL
888 parent = debugfs_create_dir("ebiu_sdram", top);
889# ifdef __ADSPBF561__
890 D32(EBIU_SDBCTL);
891# else
892 D16(EBIU_SDBCTL);
893# endif
894 D32(EBIU_SDGCTL);
895 D16(EBIU_SDRRC);
896 D16(EBIU_SDSTAT);
897#endif
898
899#ifdef EBIU_DDRACCT
900 parent = debugfs_create_dir("ebiu_ddr", top);
901 D32(EBIU_DDRACCT);
902 D32(EBIU_DDRARCT);
903 D32(EBIU_DDRBRC0);
904 D32(EBIU_DDRBRC1);
905 D32(EBIU_DDRBRC2);
906 D32(EBIU_DDRBRC3);
907 D32(EBIU_DDRBRC4);
908 D32(EBIU_DDRBRC5);
909 D32(EBIU_DDRBRC6);
910 D32(EBIU_DDRBRC7);
911 D32(EBIU_DDRBWC0);
912 D32(EBIU_DDRBWC1);
913 D32(EBIU_DDRBWC2);
914 D32(EBIU_DDRBWC3);
915 D32(EBIU_DDRBWC4);
916 D32(EBIU_DDRBWC5);
917 D32(EBIU_DDRBWC6);
918 D32(EBIU_DDRBWC7);
919 D32(EBIU_DDRCTL0);
920 D32(EBIU_DDRCTL1);
921 D32(EBIU_DDRCTL2);
922 D32(EBIU_DDRCTL3);
923 D32(EBIU_DDRGC0);
924 D32(EBIU_DDRGC1);
925 D32(EBIU_DDRGC2);
926 D32(EBIU_DDRGC3);
927 D32(EBIU_DDRMCCL);
928 D32(EBIU_DDRMCEN);
929 D32(EBIU_DDRQUE);
930 D32(EBIU_DDRTACT);
931 D32(EBIU_ERRADD);
932 D16(EBIU_ERRMST);
933 D16(EBIU_RSTCTL);
934#endif
935
936#ifdef EMAC_ADDRHI
937 parent = debugfs_create_dir("emac", top);
938 D32(EMAC_ADDRHI);
939 D32(EMAC_ADDRLO);
940 D32(EMAC_FLC);
941 D32(EMAC_HASHHI);
942 D32(EMAC_HASHLO);
943 D32(EMAC_MMC_CTL);
944 D32(EMAC_MMC_RIRQE);
945 D32(EMAC_MMC_RIRQS);
946 D32(EMAC_MMC_TIRQE);
947 D32(EMAC_MMC_TIRQS);
948 D32(EMAC_OPMODE);
949 D32(EMAC_RXC_ALIGN);
950 D32(EMAC_RXC_ALLFRM);
951 D32(EMAC_RXC_ALLOCT);
952 D32(EMAC_RXC_BROAD);
953 D32(EMAC_RXC_DMAOVF);
954 D32(EMAC_RXC_EQ64);
955 D32(EMAC_RXC_FCS);
956 D32(EMAC_RXC_GE1024);
957 D32(EMAC_RXC_LNERRI);
958 D32(EMAC_RXC_LNERRO);
959 D32(EMAC_RXC_LONG);
960 D32(EMAC_RXC_LT1024);
961 D32(EMAC_RXC_LT128);
962 D32(EMAC_RXC_LT256);
963 D32(EMAC_RXC_LT512);
964 D32(EMAC_RXC_MACCTL);
965 D32(EMAC_RXC_MULTI);
966 D32(EMAC_RXC_OCTET);
967 D32(EMAC_RXC_OK);
968 D32(EMAC_RXC_OPCODE);
969 D32(EMAC_RXC_PAUSE);
970 D32(EMAC_RXC_SHORT);
971 D32(EMAC_RXC_TYPED);
972 D32(EMAC_RXC_UNICST);
973 D32(EMAC_RX_IRQE);
974 D32(EMAC_RX_STAT);
975 D32(EMAC_RX_STKY);
976 D32(EMAC_STAADD);
977 D32(EMAC_STADAT);
978 D32(EMAC_SYSCTL);
979 D32(EMAC_SYSTAT);
980 D32(EMAC_TXC_1COL);
981 D32(EMAC_TXC_ABORT);
982 D32(EMAC_TXC_ALLFRM);
983 D32(EMAC_TXC_ALLOCT);
984 D32(EMAC_TXC_BROAD);
985 D32(EMAC_TXC_CRSERR);
986 D32(EMAC_TXC_DEFER);
987 D32(EMAC_TXC_DMAUND);
988 D32(EMAC_TXC_EQ64);
989 D32(EMAC_TXC_GE1024);
990 D32(EMAC_TXC_GT1COL);
991 D32(EMAC_TXC_LATECL);
992 D32(EMAC_TXC_LT1024);
993 D32(EMAC_TXC_LT128);
994 D32(EMAC_TXC_LT256);
995 D32(EMAC_TXC_LT512);
996 D32(EMAC_TXC_MACCTL);
997 D32(EMAC_TXC_MULTI);
998 D32(EMAC_TXC_OCTET);
999 D32(EMAC_TXC_OK);
1000 D32(EMAC_TXC_UNICST);
1001 D32(EMAC_TXC_XS_COL);
1002 D32(EMAC_TXC_XS_DFR);
1003 D32(EMAC_TX_IRQE);
1004 D32(EMAC_TX_STAT);
1005 D32(EMAC_TX_STKY);
1006 D32(EMAC_VLAN1);
1007 D32(EMAC_VLAN2);
1008 D32(EMAC_WKUP_CTL);
1009 D32(EMAC_WKUP_FFCMD);
1010 D32(EMAC_WKUP_FFCRC0);
1011 D32(EMAC_WKUP_FFCRC1);
1012 D32(EMAC_WKUP_FFMSK0);
1013 D32(EMAC_WKUP_FFMSK1);
1014 D32(EMAC_WKUP_FFMSK2);
1015 D32(EMAC_WKUP_FFMSK3);
1016 D32(EMAC_WKUP_FFOFF);
1017# ifdef EMAC_PTP_ACCR
1018 D32(EMAC_PTP_ACCR);
1019 D32(EMAC_PTP_ADDEND);
1020 D32(EMAC_PTP_ALARMHI);
1021 D32(EMAC_PTP_ALARMLO);
1022 D16(EMAC_PTP_CTL);
1023 D32(EMAC_PTP_FOFF);
1024 D32(EMAC_PTP_FV1);
1025 D32(EMAC_PTP_FV2);
1026 D32(EMAC_PTP_FV3);
1027 D16(EMAC_PTP_ID_OFF);
1028 D32(EMAC_PTP_ID_SNAP);
1029 D16(EMAC_PTP_IE);
1030 D16(EMAC_PTP_ISTAT);
1031 D32(EMAC_PTP_OFFSET);
1032 D32(EMAC_PTP_PPS_PERIOD);
1033 D32(EMAC_PTP_PPS_STARTHI);
1034 D32(EMAC_PTP_PPS_STARTLO);
1035 D32(EMAC_PTP_RXSNAPHI);
1036 D32(EMAC_PTP_RXSNAPLO);
1037 D32(EMAC_PTP_TIMEHI);
1038 D32(EMAC_PTP_TIMELO);
1039 D32(EMAC_PTP_TXSNAPHI);
1040 D32(EMAC_PTP_TXSNAPLO);
1041# endif
1042#endif
1043
1044#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
1045 parent = debugfs_create_dir("eppi", top);
1046# ifdef EPPI0_STATUS
1047 EPPI(0);
1048# endif
1049# ifdef EPPI1_STATUS
1050 EPPI(1);
1051# endif
1052# ifdef EPPI2_STATUS
1053 EPPI(2);
1054# endif
1055#endif
1056
1057 parent = debugfs_create_dir("gptimer", top);
1058#ifdef TIMER_ENABLE
1059 GPTIMER_GROUP(TIMER_ENABLE, -1);
1060#endif
1061#ifdef TIMER_ENABLE0
1062 GPTIMER_GROUP(TIMER_ENABLE0, 0);
1063#endif
1064#ifdef TIMER_ENABLE1
1065 GPTIMER_GROUP(TIMER_ENABLE1, 1);
1066#endif
1067
1068#ifdef TMRS4_DISABLE
1069 GPTIMER_GROUP(TMRS4_ENABLE, 0);
1070 GPTIMER_GROUP(TMRS8_ENABLE, 1);
1071#endif
1072 GPTIMER(0);
1073 GPTIMER(1);
1074 GPTIMER(2);
1075#ifdef TIMER3_CONFIG
1076 GPTIMER(3);
1077 GPTIMER(4);
1078 GPTIMER(5);
1079 GPTIMER(6);
1080 GPTIMER(7);
1081#endif
1082#ifdef TIMER8_CONFIG
1083 GPTIMER(8);
1084 GPTIMER(9);
1085 GPTIMER(10);
1086#endif
1087#ifdef TIMER11_CONFIG
1088 GPTIMER(11);
1089#endif
1090
1091#ifdef HMDMA0_CONTROL
1092 parent = debugfs_create_dir("hmdma", top);
1093 HMDMA(0);
1094 HMDMA(1);
1095#endif
1096
1097#ifdef HOST_CONTROL
1098 parent = debugfs_create_dir("hostdp", top);
1099 D16(HOST_CONTROL);
1100 D16(HOST_STATUS);
1101 D16(HOST_TIMEOUT);
1102#endif
1103
1104#ifdef IMDMA_S0_CONFIG
1105 parent = debugfs_create_dir("imdma", top);
1106 IMDMA(0);
1107 IMDMA(1);
1108#endif
1109
1110#ifdef KPAD_CTL
1111 parent = debugfs_create_dir("keypad", top);
1112 D16(KPAD_CTL);
1113 D16(KPAD_PRESCALE);
1114 D16(KPAD_MSEL);
1115 D16(KPAD_ROWCOL);
1116 D16(KPAD_STAT);
1117 D16(KPAD_SOFTEVAL);
1118#endif
1119
1120 parent = debugfs_create_dir("mdma", top);
1121 MDMA(0);
1122 MDMA(1);
1123#ifdef MDMA_D2_CONFIG
1124 MDMA(2);
1125 MDMA(3);
1126#endif
1127
1128#ifdef MXVR_CONFIG
1129 parent = debugfs_create_dir("mxvr", top);
1130 D16(MXVR_CONFIG);
1131# ifdef MXVR_PLL_CTL_0
1132 D32(MXVR_PLL_CTL_0);
1133# endif
1134 D32(MXVR_STATE_0);
1135 D32(MXVR_STATE_1);
1136 D32(MXVR_INT_STAT_0);
1137 D32(MXVR_INT_STAT_1);
1138 D32(MXVR_INT_EN_0);
1139 D32(MXVR_INT_EN_1);
1140 D16(MXVR_POSITION);
1141 D16(MXVR_MAX_POSITION);
1142 D16(MXVR_DELAY);
1143 D16(MXVR_MAX_DELAY);
1144 D32(MXVR_LADDR);
1145 D16(MXVR_GADDR);
1146 D32(MXVR_AADDR);
1147 D32(MXVR_ALLOC_0);
1148 D32(MXVR_ALLOC_1);
1149 D32(MXVR_ALLOC_2);
1150 D32(MXVR_ALLOC_3);
1151 D32(MXVR_ALLOC_4);
1152 D32(MXVR_ALLOC_5);
1153 D32(MXVR_ALLOC_6);
1154 D32(MXVR_ALLOC_7);
1155 D32(MXVR_ALLOC_8);
1156 D32(MXVR_ALLOC_9);
1157 D32(MXVR_ALLOC_10);
1158 D32(MXVR_ALLOC_11);
1159 D32(MXVR_ALLOC_12);
1160 D32(MXVR_ALLOC_13);
1161 D32(MXVR_ALLOC_14);
1162 D32(MXVR_SYNC_LCHAN_0);
1163 D32(MXVR_SYNC_LCHAN_1);
1164 D32(MXVR_SYNC_LCHAN_2);
1165 D32(MXVR_SYNC_LCHAN_3);
1166 D32(MXVR_SYNC_LCHAN_4);
1167 D32(MXVR_SYNC_LCHAN_5);
1168 D32(MXVR_SYNC_LCHAN_6);
1169 D32(MXVR_SYNC_LCHAN_7);
1170 D32(MXVR_DMA0_CONFIG);
1171 D32(MXVR_DMA0_START_ADDR);
1172 D16(MXVR_DMA0_COUNT);
1173 D32(MXVR_DMA0_CURR_ADDR);
1174 D16(MXVR_DMA0_CURR_COUNT);
1175 D32(MXVR_DMA1_CONFIG);
1176 D32(MXVR_DMA1_START_ADDR);
1177 D16(MXVR_DMA1_COUNT);
1178 D32(MXVR_DMA1_CURR_ADDR);
1179 D16(MXVR_DMA1_CURR_COUNT);
1180 D32(MXVR_DMA2_CONFIG);
1181 D32(MXVR_DMA2_START_ADDR);
1182 D16(MXVR_DMA2_COUNT);
1183 D32(MXVR_DMA2_CURR_ADDR);
1184 D16(MXVR_DMA2_CURR_COUNT);
1185 D32(MXVR_DMA3_CONFIG);
1186 D32(MXVR_DMA3_START_ADDR);
1187 D16(MXVR_DMA3_COUNT);
1188 D32(MXVR_DMA3_CURR_ADDR);
1189 D16(MXVR_DMA3_CURR_COUNT);
1190 D32(MXVR_DMA4_CONFIG);
1191 D32(MXVR_DMA4_START_ADDR);
1192 D16(MXVR_DMA4_COUNT);
1193 D32(MXVR_DMA4_CURR_ADDR);
1194 D16(MXVR_DMA4_CURR_COUNT);
1195 D32(MXVR_DMA5_CONFIG);
1196 D32(MXVR_DMA5_START_ADDR);
1197 D16(MXVR_DMA5_COUNT);
1198 D32(MXVR_DMA5_CURR_ADDR);
1199 D16(MXVR_DMA5_CURR_COUNT);
1200 D32(MXVR_DMA6_CONFIG);
1201 D32(MXVR_DMA6_START_ADDR);
1202 D16(MXVR_DMA6_COUNT);
1203 D32(MXVR_DMA6_CURR_ADDR);
1204 D16(MXVR_DMA6_CURR_COUNT);
1205 D32(MXVR_DMA7_CONFIG);
1206 D32(MXVR_DMA7_START_ADDR);
1207 D16(MXVR_DMA7_COUNT);
1208 D32(MXVR_DMA7_CURR_ADDR);
1209 D16(MXVR_DMA7_CURR_COUNT);
1210 D16(MXVR_AP_CTL);
1211 D32(MXVR_APRB_START_ADDR);
1212 D32(MXVR_APRB_CURR_ADDR);
1213 D32(MXVR_APTB_START_ADDR);
1214 D32(MXVR_APTB_CURR_ADDR);
1215 D32(MXVR_CM_CTL);
1216 D32(MXVR_CMRB_START_ADDR);
1217 D32(MXVR_CMRB_CURR_ADDR);
1218 D32(MXVR_CMTB_START_ADDR);
1219 D32(MXVR_CMTB_CURR_ADDR);
1220 D32(MXVR_RRDB_START_ADDR);
1221 D32(MXVR_RRDB_CURR_ADDR);
1222 D32(MXVR_PAT_DATA_0);
1223 D32(MXVR_PAT_EN_0);
1224 D32(MXVR_PAT_DATA_1);
1225 D32(MXVR_PAT_EN_1);
1226 D16(MXVR_FRAME_CNT_0);
1227 D16(MXVR_FRAME_CNT_1);
1228 D32(MXVR_ROUTING_0);
1229 D32(MXVR_ROUTING_1);
1230 D32(MXVR_ROUTING_2);
1231 D32(MXVR_ROUTING_3);
1232 D32(MXVR_ROUTING_4);
1233 D32(MXVR_ROUTING_5);
1234 D32(MXVR_ROUTING_6);
1235 D32(MXVR_ROUTING_7);
1236 D32(MXVR_ROUTING_8);
1237 D32(MXVR_ROUTING_9);
1238 D32(MXVR_ROUTING_10);
1239 D32(MXVR_ROUTING_11);
1240 D32(MXVR_ROUTING_12);
1241 D32(MXVR_ROUTING_13);
1242 D32(MXVR_ROUTING_14);
1243# ifdef MXVR_PLL_CTL_1
1244 D32(MXVR_PLL_CTL_1);
1245# endif
1246 D16(MXVR_BLOCK_CNT);
1247# ifdef MXVR_CLK_CTL
1248 D32(MXVR_CLK_CTL);
1249# endif
1250# ifdef MXVR_CDRPLL_CTL
1251 D32(MXVR_CDRPLL_CTL);
1252# endif
1253# ifdef MXVR_FMPLL_CTL
1254 D32(MXVR_FMPLL_CTL);
1255# endif
1256# ifdef MXVR_PIN_CTL
1257 D16(MXVR_PIN_CTL);
1258# endif
1259# ifdef MXVR_SCLK_CNT
1260 D16(MXVR_SCLK_CNT);
1261# endif
1262#endif
1263
1264#ifdef NFC_ADDR
1265 parent = debugfs_create_dir("nfc", top);
1266 D_WO(NFC_ADDR, 16);
1267 D_WO(NFC_CMD, 16);
1268 D_RO(NFC_COUNT, 16);
1269 D16(NFC_CTL);
1270 D_WO(NFC_DATA_RD, 16);
1271 D_WO(NFC_DATA_WR, 16);
1272 D_RO(NFC_ECC0, 16);
1273 D_RO(NFC_ECC1, 16);
1274 D_RO(NFC_ECC2, 16);
1275 D_RO(NFC_ECC3, 16);
1276 D16(NFC_IRQMASK);
1277 D16(NFC_IRQSTAT);
1278 D_WO(NFC_PGCTL, 16);
1279 D_RO(NFC_READ, 16);
1280 D16(NFC_RST);
1281 D_RO(NFC_STAT, 16);
1282#endif
1283
1284#ifdef OTP_CONTROL
1285 parent = debugfs_create_dir("otp", top);
1286 D16(OTP_CONTROL);
1287 D16(OTP_BEN);
1288 D16(OTP_STATUS);
1289 D32(OTP_TIMING);
1290 D32(OTP_DATA0);
1291 D32(OTP_DATA1);
1292 D32(OTP_DATA2);
1293 D32(OTP_DATA3);
1294#endif
1295
1296#ifdef PINT0_MASK_SET
1297 parent = debugfs_create_dir("pint", top);
1298 PINT(0);
1299 PINT(1);
1300 PINT(2);
1301 PINT(3);
1302#endif
1303
1304#ifdef PIXC_CTL
1305 parent = debugfs_create_dir("pixc", top);
1306 D16(PIXC_CTL);
1307 D16(PIXC_PPL);
1308 D16(PIXC_LPF);
1309 D16(PIXC_AHSTART);
1310 D16(PIXC_AHEND);
1311 D16(PIXC_AVSTART);
1312 D16(PIXC_AVEND);
1313 D16(PIXC_ATRANSP);
1314 D16(PIXC_BHSTART);
1315 D16(PIXC_BHEND);
1316 D16(PIXC_BVSTART);
1317 D16(PIXC_BVEND);
1318 D16(PIXC_BTRANSP);
1319 D16(PIXC_INTRSTAT);
1320 D32(PIXC_RYCON);
1321 D32(PIXC_GUCON);
1322 D32(PIXC_BVCON);
1323 D32(PIXC_CCBIAS);
1324 D32(PIXC_TC);
1325#endif
1326
1327 parent = debugfs_create_dir("pll", top);
1328 D16(PLL_CTL);
1329 D16(PLL_DIV);
1330 D16(PLL_LOCKCNT);
1331 D16(PLL_STAT);
1332 D16(VR_CTL);
1333 D32(CHIPID);
1334
1335#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1336 parent = debugfs_create_dir("ppi", top);
1337# ifdef PPI_CONTROL
1338 bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
1339# endif
1340# ifdef PPI0_CONTROL
1341 PPI(0);
1342# endif
1343# ifdef PPI1_CONTROL
1344 PPI(1);
1345# endif
1346#endif
1347
1348#ifdef PWM_CTRL
1349 parent = debugfs_create_dir("pwm", top);
1350 D16(PWM_CTRL);
1351 D16(PWM_STAT);
1352 D16(PWM_TM);
1353 D16(PWM_DT);
1354 D16(PWM_GATE);
1355 D16(PWM_CHA);
1356 D16(PWM_CHB);
1357 D16(PWM_CHC);
1358 D16(PWM_SEG);
1359 D16(PWM_SYNCWT);
1360 D16(PWM_CHAL);
1361 D16(PWM_CHBL);
1362 D16(PWM_CHCL);
1363 D16(PWM_LSI);
1364 D16(PWM_STAT2);
1365#endif
1366
1367#ifdef RSI_CONFIG
1368 parent = debugfs_create_dir("rsi", top);
1369 D32(RSI_ARGUMENT);
1370 D16(RSI_CEATA_CONTROL);
1371 D16(RSI_CLK_CONTROL);
1372 D16(RSI_COMMAND);
1373 D16(RSI_CONFIG);
1374 D16(RSI_DATA_CNT);
1375 D16(RSI_DATA_CONTROL);
1376 D16(RSI_DATA_LGTH);
1377 D32(RSI_DATA_TIMER);
1378 D16(RSI_EMASK);
1379 D16(RSI_ESTAT);
1380 D32(RSI_FIFO);
1381 D16(RSI_FIFO_CNT);
1382 D32(RSI_MASK0);
1383 D32(RSI_MASK1);
1384 D16(RSI_PID0);
1385 D16(RSI_PID1);
1386 D16(RSI_PID2);
1387 D16(RSI_PID3);
1388 D16(RSI_PID4);
1389 D16(RSI_PID5);
1390 D16(RSI_PID6);
1391 D16(RSI_PID7);
1392 D16(RSI_PWR_CONTROL);
1393 D16(RSI_RD_WAIT_EN);
1394 D32(RSI_RESPONSE0);
1395 D32(RSI_RESPONSE1);
1396 D32(RSI_RESPONSE2);
1397 D32(RSI_RESPONSE3);
1398 D16(RSI_RESP_CMD);
1399 D32(RSI_STATUS);
1400 D_WO(RSI_STATUSCL, 16);
1401#endif
1402
1403#ifdef RTC_ALARM
1404 parent = debugfs_create_dir("rtc", top);
1405 D32(RTC_ALARM);
1406 D16(RTC_ICTL);
1407 D16(RTC_ISTAT);
1408 D16(RTC_PREN);
1409 D32(RTC_STAT);
1410 D16(RTC_SWCNT);
1411#endif
1412
1413#ifdef SDH_CFG
1414 parent = debugfs_create_dir("sdh", top);
1415 D32(SDH_ARGUMENT);
1416 D16(SDH_CFG);
1417 D16(SDH_CLK_CTL);
1418 D16(SDH_COMMAND);
1419 D_RO(SDH_DATA_CNT, 16);
1420 D16(SDH_DATA_CTL);
1421 D16(SDH_DATA_LGTH);
1422 D32(SDH_DATA_TIMER);
1423 D16(SDH_E_MASK);
1424 D16(SDH_E_STATUS);
1425 D32(SDH_FIFO);
1426 D_RO(SDH_FIFO_CNT, 16);
1427 D32(SDH_MASK0);
1428 D32(SDH_MASK1);
1429 D_RO(SDH_PID0, 16);
1430 D_RO(SDH_PID1, 16);
1431 D_RO(SDH_PID2, 16);
1432 D_RO(SDH_PID3, 16);
1433 D_RO(SDH_PID4, 16);
1434 D_RO(SDH_PID5, 16);
1435 D_RO(SDH_PID6, 16);
1436 D_RO(SDH_PID7, 16);
1437 D16(SDH_PWR_CTL);
1438 D16(SDH_RD_WAIT_EN);
1439 D_RO(SDH_RESPONSE0, 32);
1440 D_RO(SDH_RESPONSE1, 32);
1441 D_RO(SDH_RESPONSE2, 32);
1442 D_RO(SDH_RESPONSE3, 32);
1443 D_RO(SDH_RESP_CMD, 16);
1444 D_RO(SDH_STATUS, 32);
1445 D_WO(SDH_STATUS_CLR, 16);
1446#endif
1447
1448#ifdef SECURE_CONTROL
1449 parent = debugfs_create_dir("security", top);
1450 D16(SECURE_CONTROL);
1451 D16(SECURE_STATUS);
1452 D32(SECURE_SYSSWT);
1453#endif
1454
1455 parent = debugfs_create_dir("sic", top);
1456 D16(SWRST);
1457 D16(SYSCR);
1458 D16(SIC_RVECT);
1459 D32(SIC_IAR0);
1460 D32(SIC_IAR1);
1461 D32(SIC_IAR2);
1462#ifdef SIC_IAR3
1463 D32(SIC_IAR3);
1464#endif
1465#ifdef SIC_IAR4
1466 D32(SIC_IAR4);
1467 D32(SIC_IAR5);
1468 D32(SIC_IAR6);
1469#endif
1470#ifdef SIC_IAR7
1471 D32(SIC_IAR7);
1472#endif
1473#ifdef SIC_IAR8
1474 D32(SIC_IAR8);
1475 D32(SIC_IAR9);
1476 D32(SIC_IAR10);
1477 D32(SIC_IAR11);
1478#endif
1479#ifdef SIC_IMASK
1480 D32(SIC_IMASK);
1481 D32(SIC_ISR);
1482 D32(SIC_IWR);
1483#endif
1484#ifdef SIC_IMASK0
1485 D32(SIC_IMASK0);
1486 D32(SIC_IMASK1);
1487 D32(SIC_ISR0);
1488 D32(SIC_ISR1);
1489 D32(SIC_IWR0);
1490 D32(SIC_IWR1);
1491#endif
1492#ifdef SIC_IMASK2
1493 D32(SIC_IMASK2);
1494 D32(SIC_ISR2);
1495 D32(SIC_IWR2);
1496#endif
1497#ifdef SICB_RVECT
1498 D16(SICB_SWRST);
1499 D16(SICB_SYSCR);
1500 D16(SICB_RVECT);
1501 D32(SICB_IAR0);
1502 D32(SICB_IAR1);
1503 D32(SICB_IAR2);
1504 D32(SICB_IAR3);
1505 D32(SICB_IAR4);
1506 D32(SICB_IAR5);
1507 D32(SICB_IAR6);
1508 D32(SICB_IAR7);
1509 D32(SICB_IMASK0);
1510 D32(SICB_IMASK1);
1511 D32(SICB_ISR0);
1512 D32(SICB_ISR1);
1513 D32(SICB_IWR0);
1514 D32(SICB_IWR1);
1515#endif
1516
1517 parent = debugfs_create_dir("spi", top);
1518#ifdef SPI0_REGBASE
1519 SPI(0);
1520#endif
1521#ifdef SPI1_REGBASE
1522 SPI(1);
1523#endif
1524#ifdef SPI2_REGBASE
1525 SPI(2);
1526#endif
1527
1528 parent = debugfs_create_dir("sport", top);
1529#ifdef SPORT0_STAT
1530 SPORT(0);
1531#endif
1532#ifdef SPORT1_STAT
1533 SPORT(1);
1534#endif
1535#ifdef SPORT2_STAT
1536 SPORT(2);
1537#endif
1538#ifdef SPORT3_STAT
1539 SPORT(3);
1540#endif
1541
1542#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1543 parent = debugfs_create_dir("twi", top);
1544# ifdef TWI_CLKDIV
1545 bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1546# endif
1547# ifdef TWI0_CLKDIV
1548 TWI(0);
1549# endif
1550# ifdef TWI1_CLKDIV
1551 TWI(1);
1552# endif
1553#endif
1554
1555 parent = debugfs_create_dir("uart", top);
1556#ifdef BFIN_UART_DLL
1557 bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1558#endif
1559#ifdef UART0_DLL
1560 UART(0);
1561#endif
1562#ifdef UART1_DLL
1563 UART(1);
1564#endif
1565#ifdef UART2_DLL
1566 UART(2);
1567#endif
1568#ifdef UART3_DLL
1569 UART(3);
1570#endif
1571
1572#ifdef USB_FADDR
1573 parent = debugfs_create_dir("usb", top);
1574 D16(USB_FADDR);
1575 D16(USB_POWER);
1576 D16(USB_INTRTX);
1577 D16(USB_INTRRX);
1578 D16(USB_INTRTXE);
1579 D16(USB_INTRRXE);
1580 D16(USB_INTRUSB);
1581 D16(USB_INTRUSBE);
1582 D16(USB_FRAME);
1583 D16(USB_INDEX);
1584 D16(USB_TESTMODE);
1585 D16(USB_GLOBINTR);
1586 D16(USB_GLOBAL_CTL);
1587 D16(USB_TX_MAX_PACKET);
1588 D16(USB_CSR0);
1589 D16(USB_TXCSR);
1590 D16(USB_RX_MAX_PACKET);
1591 D16(USB_RXCSR);
1592 D16(USB_COUNT0);
1593 D16(USB_RXCOUNT);
1594 D16(USB_TXTYPE);
1595 D16(USB_NAKLIMIT0);
1596 D16(USB_TXINTERVAL);
1597 D16(USB_RXTYPE);
1598 D16(USB_RXINTERVAL);
1599 D16(USB_TXCOUNT);
1600 D16(USB_EP0_FIFO);
1601 D16(USB_EP1_FIFO);
1602 D16(USB_EP2_FIFO);
1603 D16(USB_EP3_FIFO);
1604 D16(USB_EP4_FIFO);
1605 D16(USB_EP5_FIFO);
1606 D16(USB_EP6_FIFO);
1607 D16(USB_EP7_FIFO);
1608 D16(USB_OTG_DEV_CTL);
1609 D16(USB_OTG_VBUS_IRQ);
1610 D16(USB_OTG_VBUS_MASK);
1611 D16(USB_LINKINFO);
1612 D16(USB_VPLEN);
1613 D16(USB_HS_EOF1);
1614 D16(USB_FS_EOF1);
1615 D16(USB_LS_EOF1);
1616 D16(USB_APHY_CNTRL);
1617 D16(USB_APHY_CALIB);
1618 D16(USB_APHY_CNTRL2);
1619 D16(USB_PHY_TEST);
1620 D16(USB_PLLOSC_CTRL);
1621 D16(USB_SRP_CLKDIV);
1622 D16(USB_EP_NI0_TXMAXP);
1623 D16(USB_EP_NI0_TXCSR);
1624 D16(USB_EP_NI0_RXMAXP);
1625 D16(USB_EP_NI0_RXCSR);
1626 D16(USB_EP_NI0_RXCOUNT);
1627 D16(USB_EP_NI0_TXTYPE);
1628 D16(USB_EP_NI0_TXINTERVAL);
1629 D16(USB_EP_NI0_RXTYPE);
1630 D16(USB_EP_NI0_RXINTERVAL);
1631 D16(USB_EP_NI0_TXCOUNT);
1632 D16(USB_EP_NI1_TXMAXP);
1633 D16(USB_EP_NI1_TXCSR);
1634 D16(USB_EP_NI1_RXMAXP);
1635 D16(USB_EP_NI1_RXCSR);
1636 D16(USB_EP_NI1_RXCOUNT);
1637 D16(USB_EP_NI1_TXTYPE);
1638 D16(USB_EP_NI1_TXINTERVAL);
1639 D16(USB_EP_NI1_RXTYPE);
1640 D16(USB_EP_NI1_RXINTERVAL);
1641 D16(USB_EP_NI1_TXCOUNT);
1642 D16(USB_EP_NI2_TXMAXP);
1643 D16(USB_EP_NI2_TXCSR);
1644 D16(USB_EP_NI2_RXMAXP);
1645 D16(USB_EP_NI2_RXCSR);
1646 D16(USB_EP_NI2_RXCOUNT);
1647 D16(USB_EP_NI2_TXTYPE);
1648 D16(USB_EP_NI2_TXINTERVAL);
1649 D16(USB_EP_NI2_RXTYPE);
1650 D16(USB_EP_NI2_RXINTERVAL);
1651 D16(USB_EP_NI2_TXCOUNT);
1652 D16(USB_EP_NI3_TXMAXP);
1653 D16(USB_EP_NI3_TXCSR);
1654 D16(USB_EP_NI3_RXMAXP);
1655 D16(USB_EP_NI3_RXCSR);
1656 D16(USB_EP_NI3_RXCOUNT);
1657 D16(USB_EP_NI3_TXTYPE);
1658 D16(USB_EP_NI3_TXINTERVAL);
1659 D16(USB_EP_NI3_RXTYPE);
1660 D16(USB_EP_NI3_RXINTERVAL);
1661 D16(USB_EP_NI3_TXCOUNT);
1662 D16(USB_EP_NI4_TXMAXP);
1663 D16(USB_EP_NI4_TXCSR);
1664 D16(USB_EP_NI4_RXMAXP);
1665 D16(USB_EP_NI4_RXCSR);
1666 D16(USB_EP_NI4_RXCOUNT);
1667 D16(USB_EP_NI4_TXTYPE);
1668 D16(USB_EP_NI4_TXINTERVAL);
1669 D16(USB_EP_NI4_RXTYPE);
1670 D16(USB_EP_NI4_RXINTERVAL);
1671 D16(USB_EP_NI4_TXCOUNT);
1672 D16(USB_EP_NI5_TXMAXP);
1673 D16(USB_EP_NI5_TXCSR);
1674 D16(USB_EP_NI5_RXMAXP);
1675 D16(USB_EP_NI5_RXCSR);
1676 D16(USB_EP_NI5_RXCOUNT);
1677 D16(USB_EP_NI5_TXTYPE);
1678 D16(USB_EP_NI5_TXINTERVAL);
1679 D16(USB_EP_NI5_RXTYPE);
1680 D16(USB_EP_NI5_RXINTERVAL);
1681 D16(USB_EP_NI5_TXCOUNT);
1682 D16(USB_EP_NI6_TXMAXP);
1683 D16(USB_EP_NI6_TXCSR);
1684 D16(USB_EP_NI6_RXMAXP);
1685 D16(USB_EP_NI6_RXCSR);
1686 D16(USB_EP_NI6_RXCOUNT);
1687 D16(USB_EP_NI6_TXTYPE);
1688 D16(USB_EP_NI6_TXINTERVAL);
1689 D16(USB_EP_NI6_RXTYPE);
1690 D16(USB_EP_NI6_RXINTERVAL);
1691 D16(USB_EP_NI6_TXCOUNT);
1692 D16(USB_EP_NI7_TXMAXP);
1693 D16(USB_EP_NI7_TXCSR);
1694 D16(USB_EP_NI7_RXMAXP);
1695 D16(USB_EP_NI7_RXCSR);
1696 D16(USB_EP_NI7_RXCOUNT);
1697 D16(USB_EP_NI7_TXTYPE);
1698 D16(USB_EP_NI7_TXINTERVAL);
1699 D16(USB_EP_NI7_RXTYPE);
1700 D16(USB_EP_NI7_RXINTERVAL);
1701 D16(USB_EP_NI7_TXCOUNT);
1702 D16(USB_DMA_INTERRUPT);
1703 D16(USB_DMA0CONTROL);
1704 D16(USB_DMA0ADDRLOW);
1705 D16(USB_DMA0ADDRHIGH);
1706 D16(USB_DMA0COUNTLOW);
1707 D16(USB_DMA0COUNTHIGH);
1708 D16(USB_DMA1CONTROL);
1709 D16(USB_DMA1ADDRLOW);
1710 D16(USB_DMA1ADDRHIGH);
1711 D16(USB_DMA1COUNTLOW);
1712 D16(USB_DMA1COUNTHIGH);
1713 D16(USB_DMA2CONTROL);
1714 D16(USB_DMA2ADDRLOW);
1715 D16(USB_DMA2ADDRHIGH);
1716 D16(USB_DMA2COUNTLOW);
1717 D16(USB_DMA2COUNTHIGH);
1718 D16(USB_DMA3CONTROL);
1719 D16(USB_DMA3ADDRLOW);
1720 D16(USB_DMA3ADDRHIGH);
1721 D16(USB_DMA3COUNTLOW);
1722 D16(USB_DMA3COUNTHIGH);
1723 D16(USB_DMA4CONTROL);
1724 D16(USB_DMA4ADDRLOW);
1725 D16(USB_DMA4ADDRHIGH);
1726 D16(USB_DMA4COUNTLOW);
1727 D16(USB_DMA4COUNTHIGH);
1728 D16(USB_DMA5CONTROL);
1729 D16(USB_DMA5ADDRLOW);
1730 D16(USB_DMA5ADDRHIGH);
1731 D16(USB_DMA5COUNTLOW);
1732 D16(USB_DMA5COUNTHIGH);
1733 D16(USB_DMA6CONTROL);
1734 D16(USB_DMA6ADDRLOW);
1735 D16(USB_DMA6ADDRHIGH);
1736 D16(USB_DMA6COUNTLOW);
1737 D16(USB_DMA6COUNTHIGH);
1738 D16(USB_DMA7CONTROL);
1739 D16(USB_DMA7ADDRLOW);
1740 D16(USB_DMA7ADDRHIGH);
1741 D16(USB_DMA7COUNTLOW);
1742 D16(USB_DMA7COUNTHIGH);
1743#endif
1744
1745#ifdef WDOG_CNT
1746 parent = debugfs_create_dir("watchdog", top);
1747 D32(WDOG_CNT);
1748 D16(WDOG_CTL);
1749 D32(WDOG_STAT);
1750#endif
1751#ifdef WDOGA_CNT
1752 parent = debugfs_create_dir("watchdog", top);
1753 D32(WDOGA_CNT);
1754 D16(WDOGA_CTL);
1755 D32(WDOGA_STAT);
1756 D32(WDOGB_CNT);
1757 D16(WDOGB_CTL);
1758 D32(WDOGB_STAT);
1759#endif
1760
1761
1762#ifdef FIO_FLAG_D
1763#define PORTFIO FIO_FLAG_D
1764#endif
1765
1766#ifdef FIO0_FLAG_D
1767#define PORTFIO FIO0_FLAG_D
1768#endif
1769#ifdef FIO1_FLAG_D
1770#define PORTGIO FIO1_FLAG_D
1771#endif
1772#ifdef FIO2_FLAG_D
1773#define PORTHIO FIO2_FLAG_D
1774#endif
1775 parent = debugfs_create_dir("port", top);
1776#ifdef PORTFIO
1777 PORT(PORTFIO, 'F');
1778#endif
1779#ifdef PORTGIO
1780 PORT(PORTGIO, 'G');
1781#endif
1782#ifdef PORTHIO
1783 PORT(PORTHIO, 'H');
1784#endif
1785
1786#ifdef __ADSPBF51x__
1787 D16(PORTF_FER);
1788 D16(PORTF_DRIVE);
1789 D16(PORTF_HYSTERESIS);
1790 D16(PORTF_MUX);
1791
1792 D16(PORTG_FER);
1793 D16(PORTG_DRIVE);
1794 D16(PORTG_HYSTERESIS);
1795 D16(PORTG_MUX);
1796
1797 D16(PORTH_FER);
1798 D16(PORTH_DRIVE);
1799 D16(PORTH_HYSTERESIS);
1800 D16(PORTH_MUX);
1801
1802 D16(MISCPORT_DRIVE);
1803 D16(MISCPORT_HYSTERESIS);
1804#endif
1805
1806#ifdef __ADSPBF52x__
1807 D16(PORTF_FER);
1808 D16(PORTF_DRIVE);
1809 D16(PORTF_HYSTERESIS);
1810 D16(PORTF_MUX);
1811 D16(PORTF_SLEW);
1812
1813 D16(PORTG_FER);
1814 D16(PORTG_DRIVE);
1815 D16(PORTG_HYSTERESIS);
1816 D16(PORTG_MUX);
1817 D16(PORTG_SLEW);
1818
1819 D16(PORTH_FER);
1820 D16(PORTH_DRIVE);
1821 D16(PORTH_HYSTERESIS);
1822 D16(PORTH_MUX);
1823 D16(PORTH_SLEW);
1824
1825 D16(MISCPORT_DRIVE);
1826 D16(MISCPORT_HYSTERESIS);
1827 D16(MISCPORT_SLEW);
1828#endif
1829
1830#ifdef BF537_FAMILY
1831 D16(PORTF_FER);
1832 D16(PORTG_FER);
1833 D16(PORTH_FER);
1834 D16(PORT_MUX);
1835#endif
1836
1837#ifdef BF538_FAMILY
1838 D16(PORTCIO_FER);
1839 D16(PORTCIO);
1840 D16(PORTCIO_CLEAR);
1841 D16(PORTCIO_SET);
1842 D16(PORTCIO_TOGGLE);
1843 D16(PORTCIO_DIR);
1844 D16(PORTCIO_INEN);
1845
1846 D16(PORTDIO);
1847 D16(PORTDIO_CLEAR);
1848 D16(PORTDIO_DIR);
1849 D16(PORTDIO_FER);
1850 D16(PORTDIO_INEN);
1851 D16(PORTDIO_SET);
1852 D16(PORTDIO_TOGGLE);
1853
1854 D16(PORTEIO);
1855 D16(PORTEIO_CLEAR);
1856 D16(PORTEIO_DIR);
1857 D16(PORTEIO_FER);
1858 D16(PORTEIO_INEN);
1859 D16(PORTEIO_SET);
1860 D16(PORTEIO_TOGGLE);
1861#endif
1862
1863#ifdef __ADSPBF54x__
1864 {
1865 int num;
1866 unsigned long base;
1867
1868 base = PORTA_FER;
1869 for (num = 0; num < 10; ++num) {
1870 PORT(base, num);
1871 base += sizeof(struct bfin_gpio_regs);
1872 }
1873
1874 }
1875#endif
1876
1877 debug_mmrs_dentry = top;
1878
1879 return 0;
1880}
1881module_init(bfin_debug_mmrs_init);
1882
1883static void __exit bfin_debug_mmrs_exit(void)
1884{
1885 debugfs_remove_recursive(debug_mmrs_dentry);
1886}
1887module_exit(bfin_debug_mmrs_exit);
1888
1889MODULE_LICENSE("GPL");
1890
