LXR linux/arch/mips/include/asm/pci.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 */
   6#ifndef _ASM_PCI_H
   7#define _ASM_PCI_H
   8
   9#include <linux/mm.h>
  10
  11#ifdef __KERNEL__
  12
  13/*
  14 * This file essentially defines the interface between board
  15 * specific PCI code and MIPS common PCI code.  Should potentially put
  16 * into include/asm/pci.h file.
  17 */
  18
  19#include <linux/ioport.h>
  20
  21/*
  22 * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
  23 * multiple PCI channels may have multiple PCI host controllers or a
  24 * single controller supporting multiple channels.
  25 */
  26struct pci_controller {
  27        struct pci_controller *next;
  28        struct pci_bus *bus;
  29
  30        struct pci_ops *pci_ops;
  31        struct resource *mem_resource;
  32        unsigned long mem_offset;
  33        struct resource *io_resource;
  34        unsigned long io_offset;
  35        unsigned long io_map_base;
  36
  37        unsigned int index;
  38        /* For compatibility with current (as of July 2003) pciutils
  39           and XFree86. Eventually will be removed. */
  40        unsigned int need_domain_info;
  41
  42        int iommu;
  43
  44        /* Optional access methods for reading/writing the bus number
  45           of the PCI controller */
  46        int (*get_busno)(void);
  47        void (*set_busno)(int busno);
  48};
  49
  50/*
  51 * Used by boards to register their PCI busses before the actual scanning.
  52 */
  53extern struct pci_controller * alloc_pci_controller(void);
  54extern void register_pci_controller(struct pci_controller *hose);
  55
  56/*
  57 * board supplied pci irq fixup routine
  58 */
  59extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
  60
  61
  62/* Can be used to override the logic in pci_scan_bus for skipping
  63   already-configured bus numbers - to be used for buggy BIOSes
  64   or architectures with incomplete PCI setup by the loader */
  65
  66extern unsigned int pcibios_assign_all_busses(void);
  67
  68extern unsigned long PCIBIOS_MIN_IO;
  69extern unsigned long PCIBIOS_MIN_MEM;
  70
  71#define PCIBIOS_MIN_CARDBUS_IO  0x4000
  72
  73extern void pcibios_set_master(struct pci_dev *dev);
  74
  75static inline void pcibios_penalize_isa_irq(int irq, int active)
  76{
  77        /* We don't do dynamic PCI IRQ allocation */
  78}
  79
  80#define HAVE_PCI_MMAP
  81
  82extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  83        enum pci_mmap_state mmap_state, int write_combine);
  84
  85/*
  86 * Dynamic DMA mapping stuff.
  87 * MIPS has everything mapped statically.
  88 */
  89
  90#include <linux/types.h>
  91#include <linux/slab.h>
  92#include <asm/scatterlist.h>
  93#include <linux/string.h>
  94#include <asm/io.h>
  95#include <asm-generic/pci-bridge.h>
  96
  97struct pci_dev;
  98
  99/*
 100 * The PCI address space does equal the physical memory address space.  The
 101 * networking and block device layers use this boolean for bounce buffer
 102 * decisions.  This is set if any hose does not have an IOMMU.
 103 */
 104extern unsigned int PCI_DMA_BUS_IS_PHYS;
 105
 106#ifdef CONFIG_PCI
 107static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 108                                        enum pci_dma_burst_strategy *strat,
 109                                        unsigned long *strategy_parameter)
 110{
 111        *strat = PCI_DMA_BURST_INFINITY;
 112        *strategy_parameter = ~0UL;
 113}
 114#endif
 115
 116#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
 117
 118static inline int pci_proc_domain(struct pci_bus *bus)
 119{
 120        struct pci_controller *hose = bus->sysdata;
 121        return hose->need_domain_info;
 122}
 123
 124#endif /* __KERNEL__ */
 125
 126/* implement the pci_ DMA API in terms of the generic device dma_ one */
 127#include <asm-generic/pci-dma-compat.h>
 128
 129/* Do platform specific device initialization at pci_enable_device() time */
 130extern int pcibios_plat_dev_init(struct pci_dev *dev);
 131
 132/* Chances are this interrupt is wired PC-style ...  */
 133static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 134{
 135        return channel ? 15 : 14;
 136}
 137
 138#ifdef CONFIG_CPU_CAVIUM_OCTEON
 139/* MSI arch hook for OCTEON */
 140#define arch_setup_msi_irqs arch_setup_msi_irqs
 141#endif
 142
 143extern char * (*pcibios_plat_setup)(char *str);
 144
 145#endif /* _ASM_PCI_H */
 146