1
2
3
4
5
6
7
8
9
10
11
12#ifndef _ASM_BUSCTL_REGS_H
13#define _ASM_BUSCTL_REGS_H
14
15#include <asm/cpu-regs.h>
16
17#ifdef __KERNEL__
18
19
20#define BCCR __SYSREG(0xc0002000, u32)
21#define BCCR_B0AD 0x00000003
22#define BCCR_B1AD 0x0000000c
23#define BCCR_B2AD 0x00000030
24#define BCCR_B3AD 0x000000c0
25#define BCCR_B4AD 0x00000300
26#define BCCR_B5AD 0x00000c00
27#define BCCR_B6AD 0x00003000
28#define BCCR_B7AD 0x0000c000
29#define BCCR_BxAD_EXBUS 0x0
30#define BCCR_BxAD_OPEXBUS 0x1
31#define BCCR_BxAD_OCMBUS 0x2
32#define BCCR_API 0x00070000
33#define BCCR_API_DMACICD 0x00000000
34#define BCCR_API_DMACDCI 0x00010000
35#define BCCR_API_CICDDMA 0x00020000
36#define BCCR_API_CDCIDMA 0x00030000
37#define BCCR_API_ROUNDROBIN 0x00040000
38#define BCCR_BEPRI_DMACICD 0x00c00000
39#define BCCR_BEPRI_DMACDCI 0x00000000
40#define BCCR_BEPRI_CICDDMA 0x00400000
41#define BCCR_BEPRI_CDCIDMA 0x00800000
42#define BCCR_BEPRI 0x00c00000
43#define BCCR_TMON 0x03000000
44#define BCCR_TMON_16IOCLK 0x00000000
45#define BCCR_TMON_256IOCLK 0x01000000
46#define BCCR_TMON_4096IOCLK 0x02000000
47#define BCCR_TMON_65536IOCLK 0x03000000
48#define BCCR_TMOE 0x10000000
49
50#define BCBERR __SYSREG(0xc0002010, u32)
51#define BCBERR_BESB 0x0000001f
52#define BCBERR_BESB_MON 0x00000001
53#define BCBERR_BESB_IO 0x00000002
54#define BCBERR_BESB_EX 0x00000004
55#define BCBERR_BESB_OPEX 0x00000008
56#define BCBERR_BESB_OCM 0x00000010
57#define BCBERR_BERW 0x00000100
58#define BCBERR_BERW_WRITE 0x00000000
59#define BCBERR_BERW_READ 0x00000100
60#define BCBERR_BESD 0x00000200
61#define BCBERR_BESD_BCU 0x00000000
62#define BCBERR_BESD_SLAVE_BUS 0x00000200
63#define BCBERR_BEBST 0x00000400
64#define BCBERR_BEBST_SINGLE 0x00000000
65#define BCBERR_BEBST_BURST 0x00000400
66#define BCBERR_BEME 0x00000800
67#define BCBERR_BEMR 0x00007000
68#define BCBERR_BEMR_NOERROR 0x00000000
69#define BCBERR_BEMR_CI 0x00001000
70#define BCBERR_BEMR_CD 0x00002000
71#define BCBERR_BEMR_DMA 0x00004000
72
73#define BCBEAR __SYSREGC(0xc0002020, u32)
74
75
76#define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32)
77#define SBBASE_BE 0x00000001
78#define SBBASE_BAM 0x0000fffe
79#define SBBASE_BBA 0xfffe0000
80
81#define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32)
82#define SBCNTRL0_WEH 0x00000f00
83#define SBCNTRL0_REH 0x0000f000
84#define SBCNTRL0_RWH 0x000f0000
85#define SBCNTRL0_CSH 0x00f00000
86#define SBCNTRL0_DAH 0x0f000000
87#define SBCNTRL0_ADH 0xf0000000
88
89#define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32)
90#define SBCNTRL1_WED 0x00000f00
91#define SBCNTRL1_RED 0x0000f000
92#define SBCNTRL1_RWD 0x000f0000
93#define SBCNTRL1_ASW 0x00f00000
94#define SBCNTRL1_CSD 0x0f000000
95#define SBCNTRL1_ASD 0xf0000000
96
97#define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32)
98#define SBCNTRL2_WC 0x000000ff
99#define SBCNTRL2_BWC 0x00000f00
100#define SBCNTRL2_WM 0x01000000
101#define SBCNTRL2_WM_FIXEDWAIT 0x00000000
102#define SBCNTRL2_WM_HANDSHAKE 0x01000000
103#define SBCNTRL2_BM 0x02000000
104#define SBCNTRL2_BM_SYNC 0x00000000
105#define SBCNTRL2_BM_ASYNC 0x02000000
106#define SBCNTRL2_BW 0x04000000
107#define SBCNTRL2_BW_32 0x00000000
108#define SBCNTRL2_BW_16 0x04000000
109#define SBCNTRL2_RWINV 0x08000000
110#define SBCNTRL2_RWINV_NORM 0x00000000
111#define SBCNTRL2_RWINV_INV 0x08000000
112#define SBCNTRL2_BT 0x70000000
113#define SBCNTRL2_BT_SRAM 0x00000000
114#define SBCNTRL2_BT_ADMUX 0x00000000
115#define SBCNTRL2_BT_BROM 0x00000000
116#define SBCNTRL2_BTSE 0x80000000
117
118
119#define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32)
120#define SDBASE_CE 0x00000001
121#define SDBASE_CBAM 0x0000fff0
122#define SDBASE_CBAM_SHIFT 16
123#define SDBASE_CBA 0xfff00000
124
125#define SDRAMBUS __SYSREG(0xda000000, u32)
126#define SDRAMBUS_REFEN 0x00000004
127#define SDRAMBUS_TRC 0x00000018
128#define SDRAMBUS_BSTPT 0x00000020
129#define SDRAMBUS_PONSEQ 0x00000040
130#define SDRAMBUS_SELFREQ 0x00000080
131#define SDRAMBUS_SELFON 0x00000100
132#define SDRAMBUS_SIZE 0x00030000
133#define SDRAMBUS_SIZE_64Mbit 0x00010000
134#define SDRAMBUS_SIZE_128Mbit 0x00020000
135#define SDRAMBUS_SIZE_256Mbit 0x00030000
136#define SDRAMBUS_TRASWAIT 0x000c0000
137#define SDRAMBUS_REFNUM 0x00300000
138#define SDRAMBUS_BSTWAIT 0x00c00000
139#define SDRAMBUS_SETWAIT 0x03000000
140#define SDRAMBUS_PREWAIT 0x0c000000
141#define SDRAMBUS_RASLATE 0x30000000
142#define SDRAMBUS_CASLATE 0xc0000000
143
144#define SDREFCNT __SYSREG(0xda000004, u32)
145#define SDREFCNT_PERI 0x00000fff
146
147#define SDSHDW __SYSREG(0xda000010, u32)
148
149#endif
150
151#endif
152