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14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/delay.h>
17#include <linux/string.h>
18#include <linux/init.h>
19#include <linux/bootmem.h>
20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/msi.h>
23
24#include <asm/sections.h>
25#include <asm/io.h>
26#include <asm/prom.h>
27#include <asm/pci-bridge.h>
28#include <asm/machdep.h>
29#include <asm/ppc-pci.h>
30#include <asm/opal.h>
31#include <asm/iommu.h>
32#include <asm/tce.h>
33#include <asm/abs_addr.h>
34
35#include "powernv.h"
36#include "pci.h"
37
38
39
40
41#define P5IOC2_TCE_MEMORY 0x01000000
42
43#ifdef CONFIG_PCI_MSI
44static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
45 unsigned int hwirq, unsigned int is_64,
46 struct msi_msg *msg)
47{
48 if (WARN_ON(!is_64))
49 return -ENXIO;
50 msg->data = hwirq - phb->msi_base;
51 msg->address_hi = 0x10000000;
52 msg->address_lo = 0;
53
54 return 0;
55}
56
57static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
58{
59 unsigned int bmap_size;
60 const __be32 *prop = of_get_property(phb->hose->dn,
61 "ibm,opal-msi-ranges", NULL);
62 if (!prop)
63 return;
64
65
66
67
68 if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix"))
69 return;
70 phb->msi_base = be32_to_cpup(prop);
71 phb->msi_count = be32_to_cpup(prop + 1);
72 bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
73 phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
74 if (!phb->msi_map) {
75 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
76 phb->hose->global_number);
77 return;
78 }
79 phb->msi_setup = pnv_pci_p5ioc2_msi_setup;
80 phb->msi32_support = 0;
81 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
82 phb->msi_count, phb->msi_base);
83}
84#else
85static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
86#endif
87
88static void __devinit pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
89 struct pci_dev *pdev)
90{
91 if (phb->p5ioc2.iommu_table.it_map == NULL)
92 iommu_init_table(&phb->p5ioc2.iommu_table, phb->hose->node);
93
94 set_iommu_table_base(&pdev->dev, &phb->p5ioc2.iommu_table);
95}
96
97static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
98 void *tce_mem, u64 tce_size)
99{
100 struct pnv_phb *phb;
101 const u64 *prop64;
102 u64 phb_id;
103 int64_t rc;
104 static int primary = 1;
105
106 pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name);
107
108 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
109 if (!prop64) {
110 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
111 return;
112 }
113 phb_id = be64_to_cpup(prop64);
114 pr_devel(" PHB-ID : 0x%016llx\n", phb_id);
115 pr_devel(" TCE AT : 0x%016lx\n", __pa(tce_mem));
116 pr_devel(" TCE SZ : 0x%016llx\n", tce_size);
117
118 rc = opal_pci_set_phb_tce_memory(phb_id, __pa(tce_mem), tce_size);
119 if (rc != OPAL_SUCCESS) {
120 pr_err(" Failed to set TCE memory, OPAL error %lld\n", rc);
121 return;
122 }
123
124 phb = alloc_bootmem(sizeof(struct pnv_phb));
125 if (phb) {
126 memset(phb, 0, sizeof(struct pnv_phb));
127 phb->hose = pcibios_alloc_controller(np);
128 }
129 if (!phb || !phb->hose) {
130 pr_err(" Failed to allocate PCI controller\n");
131 return;
132 }
133
134 spin_lock_init(&phb->lock);
135 phb->hose->first_busno = 0;
136 phb->hose->last_busno = 0xff;
137 phb->hose->private_data = phb;
138 phb->opal_id = phb_id;
139 phb->type = PNV_PHB_P5IOC2;
140 phb->model = PNV_PHB_MODEL_P5IOC2;
141
142 phb->regs = of_iomap(np, 0);
143
144 if (phb->regs == NULL)
145 pr_err(" Failed to map registers !\n");
146 else {
147 pr_devel(" P_BUID = 0x%08x\n", in_be32(phb->regs + 0x100));
148 pr_devel(" P_IOSZ = 0x%08x\n", in_be32(phb->regs + 0x1b0));
149 pr_devel(" P_IO_ST = 0x%08x\n", in_be32(phb->regs + 0x1e0));
150 pr_devel(" P_MEM1_H = 0x%08x\n", in_be32(phb->regs + 0x1a0));
151 pr_devel(" P_MEM1_L = 0x%08x\n", in_be32(phb->regs + 0x190));
152 pr_devel(" P_MSZ1_L = 0x%08x\n", in_be32(phb->regs + 0x1c0));
153 pr_devel(" P_MEM_ST = 0x%08x\n", in_be32(phb->regs + 0x1d0));
154 pr_devel(" P_MEM2_H = 0x%08x\n", in_be32(phb->regs + 0x2c0));
155 pr_devel(" P_MEM2_L = 0x%08x\n", in_be32(phb->regs + 0x2b0));
156 pr_devel(" P_MSZ2_H = 0x%08x\n", in_be32(phb->regs + 0x2d0));
157 pr_devel(" P_MSZ2_L = 0x%08x\n", in_be32(phb->regs + 0x2e0));
158 }
159
160
161
162 pci_process_bridge_OF_ranges(phb->hose, np, primary);
163 primary = 0;
164
165 phb->hose->ops = &pnv_pci_ops;
166
167
168 pnv_pci_init_p5ioc2_msis(phb);
169
170
171 phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
172 pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table,
173 tce_mem, tce_size, 0);
174}
175
176void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
177{
178 struct device_node *phbn;
179 const u64 *prop64;
180 u64 hub_id;
181 void *tce_mem;
182 uint64_t tce_per_phb;
183 int64_t rc;
184 int phb_count = 0;
185
186 pr_info("Probing p5ioc2 IO-Hub %s\n", np->full_name);
187
188 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
189 if (!prop64) {
190 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
191 return;
192 }
193 hub_id = be64_to_cpup(prop64);
194 pr_info(" HUB-ID : 0x%016llx\n", hub_id);
195
196
197
198
199
200 tce_mem = __alloc_bootmem(P5IOC2_TCE_MEMORY, P5IOC2_TCE_MEMORY,
201 __pa(MAX_DMA_ADDRESS));
202 if (!tce_mem) {
203 pr_err(" Failed to allocate TCE Memory !\n");
204 return;
205 }
206 pr_debug(" TCE : 0x%016lx..0x%016lx\n",
207 __pa(tce_mem), __pa(tce_mem) + P5IOC2_TCE_MEMORY - 1);
208 rc = opal_pci_set_hub_tce_memory(hub_id, __pa(tce_mem),
209 P5IOC2_TCE_MEMORY);
210 if (rc != OPAL_SUCCESS) {
211 pr_err(" Failed to allocate TCE memory, OPAL error %lld\n", rc);
212 return;
213 }
214
215
216 for_each_child_of_node(np, phbn) {
217 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
218 of_device_is_compatible(phbn, "ibm,p5ioc2-pciex"))
219 phb_count++;
220 }
221
222
223 tce_per_phb = __rounddown_pow_of_two(P5IOC2_TCE_MEMORY / phb_count);
224 pr_info(" Allocating %lld MB of TCE memory per PHB\n",
225 tce_per_phb >> 20);
226
227
228 for_each_child_of_node(np, phbn) {
229 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
230 of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) {
231 pnv_pci_init_p5ioc2_phb(phbn, tce_mem, tce_per_phb);
232 tce_mem += tce_per_phb;
233 }
234 }
235}
236
