LXR linux/arch/x86/include/asm/mce.h

   1#ifndef _ASM_X86_MCE_H
   2#define _ASM_X86_MCE_H
   3
   4#include <linux/types.h>
   5#include <asm/ioctls.h>
   6
   7/*
   8 * Machine Check support for x86
   9 */
  10
  11/* MCG_CAP register defines */
  12#define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  13#define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  14#define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  15#define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  16#define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  17#define MCG_EXT_CNT_SHIFT       16
  18#define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  19#define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  20
  21/* MCG_STATUS register defines */
  22#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  23#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  24#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  25
  26/* MCi_STATUS register defines */
  27#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  28#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  29#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  30#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  31#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  32#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  33#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  34#define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  35#define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  36
  37/* MCi_MISC register defines */
  38#define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  39#define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  40#define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  41#define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  42#define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  43#define  MCI_MISC_ADDR_MEM      3       /* memory address */
  44#define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  45
  46/* CTL2 register defines */
  47#define MCI_CTL2_CMCI_EN                (1ULL << 30)
  48#define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  49
  50#define MCJ_CTX_MASK            3
  51#define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  52#define MCJ_CTX_RANDOM          0    /* inject context: random */
  53#define MCJ_CTX_PROCESS         0x1  /* inject context: process */
  54#define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
  55#define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
  56#define MCJ_EXCEPTION           0x8  /* raise as exception */
  57#define MCJ_IRQ_BRAODCAST       0x10 /* do IRQ broadcasting */
  58
  59/* Fields are zero when not available */
  60struct mce {
  61        __u64 status;
  62        __u64 misc;
  63        __u64 addr;
  64        __u64 mcgstatus;
  65        __u64 ip;
  66        __u64 tsc;      /* cpu time stamp counter */
  67        __u64 time;     /* wall time_t when error was detected */
  68        __u8  cpuvendor;        /* cpu vendor as encoded in system.h */
  69        __u8  inject_flags;     /* software inject flags */
  70        __u16  pad;
  71        __u32 cpuid;    /* CPUID 1 EAX */
  72        __u8  cs;               /* code segment */
  73        __u8  bank;     /* machine check bank */
  74        __u8  cpu;      /* cpu number; obsolete; use extcpu now */
  75        __u8  finished;   /* entry is valid */
  76        __u32 extcpu;   /* linux cpu number that detected the error */
  77        __u32 socketid; /* CPU socket ID */
  78        __u32 apicid;   /* CPU initial apic ID */
  79        __u64 mcgcap;   /* MCGCAP MSR: machine check capabilities of CPU */
  80};
  81
  82/*
  83 * This structure contains all data related to the MCE log.  Also
  84 * carries a signature to make it easier to find from external
  85 * debugging tools.  Each entry is only valid when its finished flag
  86 * is set.
  87 */
  88
  89#define MCE_LOG_LEN 32
  90
  91struct mce_log {
  92        char signature[12]; /* "MACHINECHECK" */
  93        unsigned len;       /* = MCE_LOG_LEN */
  94        unsigned next;
  95        unsigned flags;
  96        unsigned recordlen;     /* length of struct mce */
  97        struct mce entry[MCE_LOG_LEN];
  98};
  99
 100#define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
 101
 102#define MCE_LOG_SIGNATURE       "MACHINECHECK"
 103
 104#define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
 105#define MCE_GET_LOG_LEN      _IOR('M', 2, int)
 106#define MCE_GETCLEAR_FLAGS   _IOR('M', 3, int)
 107
 108/* Software defined banks */
 109#define MCE_EXTENDED_BANK       128
 110#define MCE_THERMAL_BANK        MCE_EXTENDED_BANK + 0
 111
 112#define K8_MCE_THRESHOLD_BASE      (MCE_EXTENDED_BANK + 1)      /* MCE_AMD */
 113#define K8_MCE_THRESHOLD_BANK_0    (MCE_THRESHOLD_BASE + 0 * 9)
 114#define K8_MCE_THRESHOLD_BANK_1    (MCE_THRESHOLD_BASE + 1 * 9)
 115#define K8_MCE_THRESHOLD_BANK_2    (MCE_THRESHOLD_BASE + 2 * 9)
 116#define K8_MCE_THRESHOLD_BANK_3    (MCE_THRESHOLD_BASE + 3 * 9)
 117#define K8_MCE_THRESHOLD_BANK_4    (MCE_THRESHOLD_BASE + 4 * 9)
 118#define K8_MCE_THRESHOLD_BANK_5    (MCE_THRESHOLD_BASE + 5 * 9)
 119#define K8_MCE_THRESHOLD_DRAM_ECC  (MCE_THRESHOLD_BANK_4 + 0)
 120
 121
 122#ifdef __KERNEL__
 123
 124extern void mce_register_decode_chain(struct notifier_block *nb);
 125extern void mce_unregister_decode_chain(struct notifier_block *nb);
 126
 127#include <linux/percpu.h>
 128#include <linux/init.h>
 129#include <linux/atomic.h>
 130
 131extern int mce_disabled;
 132extern int mce_p5_enabled;
 133
 134#ifdef CONFIG_X86_MCE
 135int mcheck_init(void);
 136void mcheck_cpu_init(struct cpuinfo_x86 *c);
 137#else
 138static inline int mcheck_init(void) { return 0; }
 139static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 140#endif
 141
 142#ifdef CONFIG_X86_ANCIENT_MCE
 143void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 144void winchip_mcheck_init(struct cpuinfo_x86 *c);
 145static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 146#else
 147static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 148static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 149static inline void enable_p5_mce(void) {}
 150#endif
 151
 152void mce_setup(struct mce *m);
 153void mce_log(struct mce *m);
 154DECLARE_PER_CPU(struct device *, mce_device);
 155
 156/*
 157 * Maximum banks number.
 158 * This is the limit of the current register layout on
 159 * Intel CPUs.
 160 */
 161#define MAX_NR_BANKS 32
 162
 163#ifdef CONFIG_X86_MCE_INTEL
 164extern int mce_cmci_disabled;
 165extern int mce_ignore_ce;
 166void mce_intel_feature_init(struct cpuinfo_x86 *c);
 167void cmci_clear(void);
 168void cmci_reenable(void);
 169void cmci_rediscover(int dying);
 170void cmci_recheck(void);
 171#else
 172static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 173static inline void cmci_clear(void) {}
 174static inline void cmci_reenable(void) {}
 175static inline void cmci_rediscover(int dying) {}
 176static inline void cmci_recheck(void) {}
 177#endif
 178
 179#ifdef CONFIG_X86_MCE_AMD
 180void mce_amd_feature_init(struct cpuinfo_x86 *c);
 181#else
 182static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 183#endif
 184
 185int mce_available(struct cpuinfo_x86 *c);
 186
 187DECLARE_PER_CPU(unsigned, mce_exception_count);
 188DECLARE_PER_CPU(unsigned, mce_poll_count);
 189
 190extern atomic_t mce_entry;
 191
 192typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 193DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 194
 195enum mcp_flags {
 196        MCP_TIMESTAMP = (1 << 0),       /* log time stamp */
 197        MCP_UC = (1 << 1),              /* log uncorrected errors */
 198        MCP_DONTLOG = (1 << 2),         /* only clear, don't log */
 199};
 200void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 201
 202int mce_notify_irq(void);
 203void mce_notify_process(void);
 204
 205DECLARE_PER_CPU(struct mce, injectm);
 206
 207extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
 208                                    const char __user *ubuf,
 209                                    size_t usize, loff_t *off));
 210
 211/*
 212 * Exception handler
 213 */
 214
 215/* Call the installed machine check handler for this CPU setup. */
 216extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 217void do_machine_check(struct pt_regs *, long);
 218
 219/*
 220 * Threshold handler
 221 */
 222
 223extern void (*mce_threshold_vector)(void);
 224extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 225
 226/*
 227 * Thermal handler
 228 */
 229
 230void intel_init_thermal(struct cpuinfo_x86 *c);
 231
 232void mce_log_therm_throt_event(__u64 status);
 233
 234/* Interrupt Handler for core thermal thresholds */
 235extern int (*platform_thermal_notify)(__u64 msr_val);
 236
 237#ifdef CONFIG_X86_THERMAL_VECTOR
 238extern void mcheck_intel_therm_init(void);
 239#else
 240static inline void mcheck_intel_therm_init(void) { }
 241#endif
 242
 243/*
 244 * Used by APEI to report memory error via /dev/mcelog
 245 */
 246
 247struct cper_sec_mem_err;
 248extern void apei_mce_report_mem_error(int corrected,
 249                                      struct cper_sec_mem_err *mem_err);
 250
 251#endif /* __KERNEL__ */
 252#endif /* _ASM_X86_MCE_H */
 253