1
2
3
4
5
6
7
8
9
10
11#ifndef _ASM_X86_UV_UV_BAU_H
12#define _ASM_X86_UV_UV_BAU_H
13
14#include <linux/bitmap.h>
15#define BITSPERBYTE 8
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36#define MAX_CPUS_PER_UVHUB 64
37#define MAX_CPUS_PER_SOCKET 32
38#define ADP_SZ 64
39#define UV_CPUS_PER_AS 32
40#define ITEMS_PER_DESC 8
41
42#define MAX_BAU_CONCURRENT 3
43#define UV_ACT_STATUS_MASK 0x3
44#define UV_ACT_STATUS_SIZE 2
45#define UV_DISTRIBUTION_SIZE 256
46#define UV_SW_ACK_NPENDING 8
47#define UV1_NET_ENDPOINT_INTD 0x38
48#define UV2_NET_ENDPOINT_INTD 0x28
49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51#define UV_DESC_PSHIFT 49
52#define UV_PAYLOADQ_PNODE_SHIFT 49
53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55#define UV_BAU_TUNABLES_DIR "sgi_uv"
56#define UV_BAU_TUNABLES_FILE "bau_tunables"
57#define WHITESPACE " \t\n"
58#define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60#define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
62
63
64
65
66
67
68
69
70#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77#define BAU_MISC_CONTROL_MULT_MASK 3
78
79#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
80
81#define BAU_URGENCY_7_SHIFT 28
82#define BAU_URGENCY_7_MASK 7
83
84#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
85
86#define BAU_TRANS_SHIFT 40
87#define BAU_TRANS_MASK 0x3f
88
89
90
91
92#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
93#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
94#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
95#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
96#define write_gmmr uv_write_global_mmr64
97#define write_lmmr uv_write_local_mmr
98#define read_lmmr uv_read_local_mmr
99#define read_gmmr uv_read_global_mmr64
100
101
102
103
104#define DS_IDLE 0
105#define DS_ACTIVE 1
106#define DS_DESTINATION_TIMEOUT 2
107#define DS_SOURCE_TIMEOUT 3
108
109
110
111
112
113
114
115
116
117
118
119
120#define UV2H_DESC_IDLE 0
121#define UV2H_DESC_BUSY 2
122#define UV2H_DESC_DEST_TIMEOUT 4
123#define UV2H_DESC_DEST_STRONG_NACK 5
124#define UV2H_DESC_SOURCE_TIMEOUT 6
125#define UV2H_DESC_DEST_PUT_ERR 7
126
127
128
129
130#define PLUGGED_DELAY 10
131
132
133
134
135
136#define PLUGSB4RESET 100
137
138#define TIMEOUTSB4RESET 1
139
140#define IPI_RESET_LIMIT 1
141
142#define COMPLETE_THRESHOLD 5
143
144#define UV_LB_SUBNODEID 0x10
145
146
147#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
148#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
149
150#define UV2_ACK_MASK 0x7UL
151#define UV2_ACK_UNITS_SHFT 3
152#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
153#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
154
155
156
157
158#define DEST_Q_SIZE 20
159
160
161
162#define DEST_NUM_RESOURCES 8
163
164
165
166#define FLUSH_RETRY_PLUGGED 1
167#define FLUSH_RETRY_TIMEOUT 2
168#define FLUSH_GIVEUP 3
169#define FLUSH_COMPLETE 4
170#define FLUSH_RETRY_BUSYBUG 5
171
172
173
174
175#define CONGESTED_RESPONSE_US 1000
176
177#define CONGESTED_REPS 10
178
179#define CONGESTED_PERIOD 30
180
181
182#define MSG_NOOP 0
183#define MSG_REGULAR 1
184#define MSG_RETRY 2
185
186
187
188
189
190
191
192
193
194
195
196struct pnmask {
197 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
198};
199
200
201
202
203
204
205struct bau_local_cpumask {
206 unsigned long bits;
207};
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226struct bau_msg_payload {
227 unsigned long address;
228
229
230 unsigned short sending_cpu;
231
232 unsigned short acknowledge_count;
233
234 unsigned int reserved1:32;
235};
236
237
238
239
240
241
242struct uv1_bau_msg_header {
243 unsigned int dest_subnodeid:6;
244
245 unsigned int base_dest_nasid:15;
246
247 unsigned int command:8;
248
249
250 unsigned int rsvd_1:3;
251
252
253 unsigned int rsvd_2:9;
254
255
256 unsigned int sequence:16;
257
258
259
260
261
262
263 unsigned int rsvd_3:1;
264
265
266
267
268 unsigned int replied_to:1;
269
270
271 unsigned int msg_type:3;
272
273
274 unsigned int canceled:1;
275
276
277 unsigned int payload_1a:1;
278
279 unsigned int payload_1b:2;
280
281
282
283 unsigned int payload_1ca:6;
284
285 unsigned int payload_1c:2;
286
287
288
289 unsigned int payload_1d:6;
290
291 unsigned int payload_1e:2;
292
293
294 unsigned int rsvd_4:7;
295
296 unsigned int swack_flag:1;
297
298
299
300
301 unsigned int rsvd_5:6;
302
303 unsigned int rsvd_6:5;
304
305 unsigned int int_both:1;
306
307
308 unsigned int fairness:3;
309
310 unsigned int multilevel:1;
311
312
313
314 unsigned int chaining:1;
315
316
317 unsigned int rsvd_7:21;
318
319};
320
321
322
323
324
325struct uv2_bau_msg_header {
326 unsigned int base_dest_nasid:15;
327
328 unsigned int dest_subnodeid:5;
329
330 unsigned int rsvd_1:1;
331
332
333
334
335
336 unsigned int replied_to:1;
337
338
339 unsigned int msg_type:3;
340
341
342 unsigned int canceled:1;
343
344
345 unsigned int payload_1:3;
346
347
348
349 unsigned int payload_2a:3;
350 unsigned int payload_2b:5;
351
352
353
354 unsigned int payload_3:8;
355
356
357 unsigned int rsvd_2:7;
358
359 unsigned int swack_flag:1;
360
361 unsigned int rsvd_3a:3;
362 unsigned int rsvd_3b:8;
363 unsigned int rsvd_3c:8;
364 unsigned int rsvd_3d:3;
365
366 unsigned int fairness:3;
367
368
369 unsigned int sequence:16;
370
371 unsigned int chaining:1;
372
373
374 unsigned int multilevel:1;
375
376
377 unsigned int rsvd_4:24;
378
379
380
381 unsigned int command:8;
382
383};
384
385
386
387
388
389
390struct bau_desc {
391 struct pnmask distribution;
392
393
394
395 union bau_msg_header {
396 struct uv1_bau_msg_header uv1_hdr;
397 struct uv2_bau_msg_header uv2_hdr;
398 } header;
399
400 struct bau_msg_payload payload;
401};
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434struct bau_pq_entry {
435 unsigned long address;
436
437
438 unsigned short sending_cpu;
439
440 unsigned short acknowledge_count;
441
442
443 unsigned short replied_to:1;
444 unsigned short msg_type:3;
445 unsigned short canceled:1;
446 unsigned short unused1:3;
447
448 unsigned char unused2a;
449
450 unsigned char unused2;
451
452 unsigned char swack_vec;
453
454 unsigned short sequence;
455
456 unsigned char unused4[2];
457
458 int number_of_cpus;
459
460 unsigned char unused5[8];
461
462};
463
464struct msg_desc {
465 struct bau_pq_entry *msg;
466 int msg_slot;
467 struct bau_pq_entry *queue_first;
468 struct bau_pq_entry *queue_last;
469};
470
471struct reset_args {
472 int sender;
473};
474
475
476
477
478struct ptc_stats {
479
480 unsigned long s_giveup;
481
482 unsigned long s_requestor;
483
484 unsigned long s_stimeout;
485 unsigned long s_dtimeout;
486 unsigned long s_strongnacks;
487 unsigned long s_time;
488 unsigned long s_retriesok;
489 unsigned long s_ntargcpu;
490
491 unsigned long s_ntargself;
492
493 unsigned long s_ntarglocals;
494
495 unsigned long s_ntargremotes;
496
497 unsigned long s_ntarglocaluvhub;
498 unsigned long s_ntargremoteuvhub;
499 unsigned long s_ntarguvhub;
500
501 unsigned long s_ntarguvhub16;
502
503 unsigned long s_ntarguvhub8;
504
505 unsigned long s_ntarguvhub4;
506
507 unsigned long s_ntarguvhub2;
508
509 unsigned long s_ntarguvhub1;
510
511 unsigned long s_resets_plug;
512
513 unsigned long s_resets_timeout;
514
515 unsigned long s_busy;
516
517 unsigned long s_throttles;
518 unsigned long s_retry_messages;
519 unsigned long s_bau_reenabled;
520 unsigned long s_bau_disabled;
521 unsigned long s_uv2_wars;
522 unsigned long s_uv2_wars_hw;
523 unsigned long s_uv2_war_waits;
524
525 unsigned long d_alltlb;
526
527 unsigned long d_onetlb;
528
529 unsigned long d_multmsg;
530
531 unsigned long d_nomsg;
532 unsigned long d_time;
533
534 unsigned long d_requestee;
535
536 unsigned long d_retries;
537
538 unsigned long d_canceled;
539
540 unsigned long d_nocanceled;
541
542 unsigned long d_resets;
543
544 unsigned long d_rcanceled;
545
546};
547
548struct tunables {
549 int *tunp;
550 int deflt;
551};
552
553struct hub_and_pnode {
554 short uvhub;
555 short pnode;
556};
557
558struct socket_desc {
559 short num_cpus;
560 short cpu_number[MAX_CPUS_PER_SOCKET];
561};
562
563struct uvhub_desc {
564 unsigned short socket_mask;
565 short num_cpus;
566 short uvhub;
567 short pnode;
568 struct socket_desc socket[2];
569};
570
571
572
573
574struct bau_control {
575 struct bau_desc *descriptor_base;
576 struct bau_pq_entry *queue_first;
577 struct bau_pq_entry *queue_last;
578 struct bau_pq_entry *bau_msg_head;
579 struct bau_control *uvhub_master;
580 struct bau_control *socket_master;
581 struct ptc_stats *statp;
582 cpumask_t *cpumask;
583 unsigned long timeout_interval;
584 unsigned long set_bau_on_time;
585 atomic_t active_descriptor_count;
586 int plugged_tries;
587 int timeout_tries;
588 int ipi_attempts;
589 int conseccompletes;
590 int baudisabled;
591 int set_bau_off;
592 short cpu;
593 short osnode;
594 short uvhub_cpu;
595 short uvhub;
596 short uvhub_version;
597 short cpus_in_socket;
598 short cpus_in_uvhub;
599 short partition_base_pnode;
600 short using_desc;
601 unsigned int inuse_map;
602 unsigned short message_number;
603 unsigned short uvhub_quiesce;
604 short socket_acknowledge_count[DEST_Q_SIZE];
605 cycles_t send_message;
606 spinlock_t uvhub_lock;
607 spinlock_t queue_lock;
608
609 int max_concurr;
610 int max_concurr_const;
611 int plugged_delay;
612 int plugsb4reset;
613 int timeoutsb4reset;
614 int ipi_reset_limit;
615 int complete_threshold;
616 int cong_response_us;
617 int cong_reps;
618 int cong_period;
619 unsigned long clocks_per_100_usec;
620 cycles_t period_time;
621 long period_requests;
622 struct hub_and_pnode *thp;
623};
624
625static inline unsigned long read_mmr_uv2_status(void)
626{
627 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
628}
629
630static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
631{
632 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
633}
634
635static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
636{
637 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
638}
639
640static inline void write_mmr_activation(unsigned long index)
641{
642 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
643}
644
645static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
646{
647 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
648}
649
650static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
651{
652 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
653}
654
655static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
656{
657 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
658}
659
660static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
661{
662 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
663}
664
665static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
666{
667 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
668}
669
670static inline unsigned long read_mmr_misc_control(int pnode)
671{
672 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
673}
674
675static inline void write_mmr_sw_ack(unsigned long mr)
676{
677 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
678}
679
680static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
681{
682 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
683}
684
685static inline unsigned long read_mmr_sw_ack(void)
686{
687 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
688}
689
690static inline unsigned long read_gmmr_sw_ack(int pnode)
691{
692 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
693}
694
695static inline void write_mmr_data_config(int pnode, unsigned long mr)
696{
697 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
698}
699
700static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
701{
702 return constant_test_bit(uvhub, &dstp->bits[0]);
703}
704static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
705{
706 __set_bit(pnode, &dstp->bits[0]);
707}
708static inline void bau_uvhubs_clear(struct pnmask *dstp,
709 int nbits)
710{
711 bitmap_zero(&dstp->bits[0], nbits);
712}
713static inline int bau_uvhub_weight(struct pnmask *dstp)
714{
715 return bitmap_weight((unsigned long *)&dstp->bits[0],
716 UV_DISTRIBUTION_SIZE);
717}
718
719static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
720{
721 bitmap_zero(&dstp->bits, nbits);
722}
723
724extern void uv_bau_message_intr1(void);
725extern void uv_bau_timeout_intr1(void);
726
727struct atomic_short {
728 short counter;
729};
730
731
732
733
734
735
736
737static inline int atomic_read_short(const struct atomic_short *v)
738{
739 return v->counter;
740}
741
742
743
744
745
746
747
748
749static inline int atom_asr(short i, struct atomic_short *v)
750{
751 return i + xadd(&v->counter, i);
752}
753
754
755
756
757
758
759
760
761
762
763
764static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
765{
766 spin_lock(lock);
767 if (atomic_read(v) >= u) {
768 spin_unlock(lock);
769 return 0;
770 }
771 atomic_inc(v);
772 spin_unlock(lock);
773 return 1;
774}
775
776#endif
777