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35#ifndef _AHCI_H
36#define _AHCI_H
37
38#include <linux/libata.h>
39
40
41#define EM_CTRL_MSG_TYPE 0x000f0000
42
43
44#define EM_MSG_LED_HBA_PORT 0x0000000f
45#define EM_MSG_LED_PMP_SLOT 0x0000ff00
46#define EM_MSG_LED_VALUE 0xffff0000
47#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
48#define EM_MSG_LED_VALUE_OFF 0xfff80000
49#define EM_MSG_LED_VALUE_ON 0x00010000
50
51enum {
52 AHCI_MAX_PORTS = 32,
53 AHCI_MAX_SG = 168,
54 AHCI_DMA_BOUNDARY = 0xffffffff,
55 AHCI_MAX_CMDS = 32,
56 AHCI_CMD_SZ = 32,
57 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
58 AHCI_RX_FIS_SZ = 256,
59 AHCI_CMD_TBL_CDB = 0x40,
60 AHCI_CMD_TBL_HDR_SZ = 0x80,
61 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
62 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
64 AHCI_RX_FIS_SZ,
65 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
66 AHCI_CMD_TBL_AR_SZ +
67 (AHCI_RX_FIS_SZ * 16),
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
74
75 RX_FIS_PIO_SETUP = 0x20,
76 RX_FIS_D2H_REG = 0x40,
77 RX_FIS_SDB = 0x58,
78 RX_FIS_UNK = 0x60,
79
80
81 HOST_CAP = 0x00,
82 HOST_CTL = 0x04,
83 HOST_IRQ_STAT = 0x08,
84 HOST_PORTS_IMPL = 0x0c,
85 HOST_VERSION = 0x10,
86 HOST_EM_LOC = 0x1c,
87 HOST_EM_CTL = 0x20,
88 HOST_CAP2 = 0x24,
89
90
91 HOST_RESET = (1 << 0),
92 HOST_IRQ_EN = (1 << 1),
93 HOST_AHCI_EN = (1 << 31),
94
95
96 HOST_CAP_SXS = (1 << 5),
97 HOST_CAP_EMS = (1 << 6),
98 HOST_CAP_CCC = (1 << 7),
99 HOST_CAP_PART = (1 << 13),
100 HOST_CAP_SSC = (1 << 14),
101 HOST_CAP_PIO_MULTI = (1 << 15),
102 HOST_CAP_FBS = (1 << 16),
103 HOST_CAP_PMP = (1 << 17),
104 HOST_CAP_ONLY = (1 << 18),
105 HOST_CAP_CLO = (1 << 24),
106 HOST_CAP_LED = (1 << 25),
107 HOST_CAP_ALPM = (1 << 26),
108 HOST_CAP_SSS = (1 << 27),
109 HOST_CAP_MPS = (1 << 28),
110 HOST_CAP_SNTF = (1 << 29),
111 HOST_CAP_NCQ = (1 << 30),
112 HOST_CAP_64 = (1 << 31),
113
114
115 HOST_CAP2_BOH = (1 << 0),
116 HOST_CAP2_NVMHCI = (1 << 1),
117 HOST_CAP2_APST = (1 << 2),
118
119
120 PORT_LST_ADDR = 0x00,
121 PORT_LST_ADDR_HI = 0x04,
122 PORT_FIS_ADDR = 0x08,
123 PORT_FIS_ADDR_HI = 0x0c,
124 PORT_IRQ_STAT = 0x10,
125 PORT_IRQ_MASK = 0x14,
126 PORT_CMD = 0x18,
127 PORT_TFDATA = 0x20,
128 PORT_SIG = 0x24,
129 PORT_CMD_ISSUE = 0x38,
130 PORT_SCR_STAT = 0x28,
131 PORT_SCR_CTL = 0x2c,
132 PORT_SCR_ERR = 0x30,
133 PORT_SCR_ACT = 0x34,
134 PORT_SCR_NTF = 0x3c,
135 PORT_FBS = 0x40,
136
137
138 PORT_IRQ_COLD_PRES = (1 << 31),
139 PORT_IRQ_TF_ERR = (1 << 30),
140 PORT_IRQ_HBUS_ERR = (1 << 29),
141 PORT_IRQ_HBUS_DATA_ERR = (1 << 28),
142 PORT_IRQ_IF_ERR = (1 << 27),
143 PORT_IRQ_IF_NONFATAL = (1 << 26),
144 PORT_IRQ_OVERFLOW = (1 << 24),
145 PORT_IRQ_BAD_PMP = (1 << 23),
146
147 PORT_IRQ_PHYRDY = (1 << 22),
148 PORT_IRQ_DEV_ILCK = (1 << 7),
149 PORT_IRQ_CONNECT = (1 << 6),
150 PORT_IRQ_SG_DONE = (1 << 5),
151 PORT_IRQ_UNK_FIS = (1 << 4),
152 PORT_IRQ_SDB_FIS = (1 << 3),
153 PORT_IRQ_DMAS_FIS = (1 << 2),
154 PORT_IRQ_PIOS_FIS = (1 << 1),
155 PORT_IRQ_D2H_REG_FIS = (1 << 0),
156
157 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
158 PORT_IRQ_IF_ERR |
159 PORT_IRQ_CONNECT |
160 PORT_IRQ_PHYRDY |
161 PORT_IRQ_UNK_FIS |
162 PORT_IRQ_BAD_PMP,
163 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
164 PORT_IRQ_TF_ERR |
165 PORT_IRQ_HBUS_DATA_ERR,
166 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
167 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
168 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
169
170
171 PORT_CMD_ASP = (1 << 27),
172 PORT_CMD_ALPE = (1 << 26),
173 PORT_CMD_ATAPI = (1 << 24),
174 PORT_CMD_FBSCP = (1 << 22),
175 PORT_CMD_PMP = (1 << 17),
176 PORT_CMD_LIST_ON = (1 << 15),
177 PORT_CMD_FIS_ON = (1 << 14),
178 PORT_CMD_FIS_RX = (1 << 4),
179 PORT_CMD_CLO = (1 << 3),
180 PORT_CMD_POWER_ON = (1 << 2),
181 PORT_CMD_SPIN_UP = (1 << 1),
182 PORT_CMD_START = (1 << 0),
183
184 PORT_CMD_ICC_MASK = (0xf << 28),
185 PORT_CMD_ICC_ACTIVE = (0x1 << 28),
186 PORT_CMD_ICC_PARTIAL = (0x2 << 28),
187 PORT_CMD_ICC_SLUMBER = (0x6 << 28),
188
189 PORT_FBS_DWE_OFFSET = 16,
190 PORT_FBS_ADO_OFFSET = 12,
191 PORT_FBS_DEV_OFFSET = 8,
192 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET),
193 PORT_FBS_SDE = (1 << 2),
194 PORT_FBS_DEC = (1 << 1),
195 PORT_FBS_EN = (1 << 0),
196
197
198
199#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
200
201 AHCI_HFLAG_NO_NCQ = (1 << 0),
202 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1),
203 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2),
204 AHCI_HFLAG_32BIT_ONLY = (1 << 3),
205 AHCI_HFLAG_MV_PATA = (1 << 4),
206 AHCI_HFLAG_NO_MSI = (1 << 5),
207 AHCI_HFLAG_NO_PMP = (1 << 6),
208 AHCI_HFLAG_SECT255 = (1 << 8),
209 AHCI_HFLAG_YES_NCQ = (1 << 9),
210 AHCI_HFLAG_NO_SUSPEND = (1 << 10),
211 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11),
212
213 AHCI_HFLAG_NO_SNTF = (1 << 12),
214 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13),
215 AHCI_HFLAG_YES_FBS = (1 << 14),
216 AHCI_HFLAG_DELAY_ENGINE = (1 << 15),
217
218
219
220
221
222 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
223 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
224
225 ICH_MAP = 0x90,
226
227
228 EM_MAX_SLOTS = 8,
229 EM_MAX_RETRY = 5,
230
231
232 EM_CTL_RST = (1 << 9),
233 EM_CTL_TM = (1 << 8),
234 EM_CTL_MR = (1 << 0),
235 EM_CTL_ALHD = (1 << 26),
236 EM_CTL_XMT = (1 << 25),
237 EM_CTL_SMB = (1 << 24),
238 EM_CTL_SGPIO = (1 << 19),
239 EM_CTL_SES = (1 << 18),
240 EM_CTL_SAFTE = (1 << 17),
241 EM_CTL_LED = (1 << 16),
242
243
244 EM_MSG_TYPE_LED = (1 << 0),
245 EM_MSG_TYPE_SAFTE = (1 << 1),
246 EM_MSG_TYPE_SES2 = (1 << 2),
247 EM_MSG_TYPE_SGPIO = (1 << 3),
248};
249
250struct ahci_cmd_hdr {
251 __le32 opts;
252 __le32 status;
253 __le32 tbl_addr;
254 __le32 tbl_addr_hi;
255 __le32 reserved[4];
256};
257
258struct ahci_sg {
259 __le32 addr;
260 __le32 addr_hi;
261 __le32 reserved;
262 __le32 flags_size;
263};
264
265struct ahci_em_priv {
266 enum sw_activity blink_policy;
267 struct timer_list timer;
268 unsigned long saved_activity;
269 unsigned long activity;
270 unsigned long led_state;
271};
272
273struct ahci_port_priv {
274 struct ata_link *active_link;
275 struct ahci_cmd_hdr *cmd_slot;
276 dma_addr_t cmd_slot_dma;
277 void *cmd_tbl;
278 dma_addr_t cmd_tbl_dma;
279 void *rx_fis;
280 dma_addr_t rx_fis_dma;
281
282 unsigned int ncq_saw_d2h:1;
283 unsigned int ncq_saw_dmas:1;
284 unsigned int ncq_saw_sdb:1;
285 u32 intr_mask;
286 bool fbs_supported;
287 bool fbs_enabled;
288 int fbs_last_dev;
289
290 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
291};
292
293struct ahci_host_priv {
294 void __iomem * mmio;
295 unsigned int flags;
296 u32 cap;
297 u32 cap2;
298 u32 port_map;
299 u32 saved_cap;
300 u32 saved_cap2;
301 u32 saved_port_map;
302 u32 em_loc;
303 u32 em_buf_sz;
304 u32 em_msg_type;
305};
306
307extern int ahci_ignore_sss;
308
309extern struct device_attribute *ahci_shost_attrs[];
310extern struct device_attribute *ahci_sdev_attrs[];
311
312#define AHCI_SHT(drv_name) \
313 ATA_NCQ_SHT(drv_name), \
314 .can_queue = AHCI_MAX_CMDS - 1, \
315 .sg_tablesize = AHCI_MAX_SG, \
316 .dma_boundary = AHCI_DMA_BOUNDARY, \
317 .shost_attrs = ahci_shost_attrs, \
318 .sdev_attrs = ahci_sdev_attrs
319
320extern struct ata_port_operations ahci_ops;
321extern struct ata_port_operations ahci_pmp_retry_srst_ops;
322
323void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
324 u32 opts);
325void ahci_save_initial_config(struct device *dev,
326 struct ahci_host_priv *hpriv,
327 unsigned int force_port_map,
328 unsigned int mask_port_map);
329void ahci_init_controller(struct ata_host *host);
330int ahci_reset_controller(struct ata_host *host);
331
332int ahci_do_softreset(struct ata_link *link, unsigned int *class,
333 int pmp, unsigned long deadline,
334 int (*check_ready)(struct ata_link *link));
335
336int ahci_stop_engine(struct ata_port *ap);
337void ahci_start_engine(struct ata_port *ap);
338int ahci_check_ready(struct ata_link *link);
339int ahci_kick_engine(struct ata_port *ap);
340int ahci_port_resume(struct ata_port *ap);
341void ahci_set_em_messages(struct ahci_host_priv *hpriv,
342 struct ata_port_info *pi);
343int ahci_reset_em(struct ata_host *host);
344irqreturn_t ahci_interrupt(int irq, void *dev_instance);
345void ahci_print_info(struct ata_host *host, const char *scc_s);
346
347static inline void __iomem *__ahci_port_base(struct ata_host *host,
348 unsigned int port_no)
349{
350 struct ahci_host_priv *hpriv = host->private_data;
351 void __iomem *mmio = hpriv->mmio;
352
353 return mmio + 0x100 + (port_no * 0x80);
354}
355
356static inline void __iomem *ahci_port_base(struct ata_port *ap)
357{
358 return __ahci_port_base(ap->host, ap->port_no);
359}
360
361static inline int ahci_nr_ports(u32 cap)
362{
363 return (cap & 0x1f) + 1;
364}
365
366#endif
367