1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24#ifndef NI_H 25#define NI_H 26 27#define CAYMAN_MAX_SH_GPRS 256 28#define CAYMAN_MAX_TEMP_GPRS 16 29#define CAYMAN_MAX_SH_THREADS 256 30#define CAYMAN_MAX_SH_STACK_ENTRIES 4096 31#define CAYMAN_MAX_FRC_EOV_CNT 16384 32#define CAYMAN_MAX_BACKENDS 8 33#define CAYMAN_MAX_BACKENDS_MASK 0xFF 34#define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF 35#define CAYMAN_MAX_SIMDS 16 36#define CAYMAN_MAX_SIMDS_MASK 0xFFFF 37#define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF 38#define CAYMAN_MAX_PIPES 8 39#define CAYMAN_MAX_PIPES_MASK 0xFF 40#define CAYMAN_MAX_LDS_NUM 0xFFFF 41#define CAYMAN_MAX_TCC 16 42#define CAYMAN_MAX_TCC_MASK 0xFF 43 44#define DMIF_ADDR_CONFIG 0xBD4 45#define SRBM_GFX_CNTL 0x0E44 46#define RINGID(x) (((x) & 0x3) << 0) 47#define VMID(x) (((x) & 0x7) << 0) 48#define SRBM_STATUS 0x0E50 49 50#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 51#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 52#define RESPONSE_TYPE_MASK 0x000000F0 53#define RESPONSE_TYPE_SHIFT 4 54#define VM_L2_CNTL 0x1400 55#define ENABLE_L2_CACHE (1 << 0) 56#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 57#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 58#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 59#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) 60#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) 61/* CONTEXT1_IDENTITY_ACCESS_MODE 62 * 0 physical = logical 63 * 1 logical via context1 page table 64 * 2 inside identity aperture use translation, outside physical = logical 65 * 3 inside identity aperture physical = logical, outside use translation 66 */ 67#define VM_L2_CNTL2 0x1404 68#define INVALIDATE_ALL_L1_TLBS (1 << 0) 69#define INVALIDATE_L2_CACHE (1 << 1) 70#define VM_L2_CNTL3 0x1408 71#define BANK_SELECT(x) ((x) << 0) 72#define CACHE_UPDATE_MODE(x) ((x) << 6) 73#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 74#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 75#define VM_L2_STATUS 0x140C 76#define L2_BUSY (1 << 0) 77#define VM_CONTEXT0_CNTL 0x1410 78#define ENABLE_CONTEXT (1 << 0) 79#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 80#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 81#define VM_CONTEXT1_CNTL 0x1414 82#define VM_CONTEXT0_CNTL2 0x1430 83#define VM_CONTEXT1_CNTL2 0x1434 84#define VM_INVALIDATE_REQUEST 0x1478 85#define VM_INVALIDATE_RESPONSE 0x147c 86#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 87#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 88#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C 89#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C 90#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 91 92#define MC_SHARED_CHMAP 0x2004 93#define NOOFCHAN_SHIFT 12 94#define NOOFCHAN_MASK 0x00003000 95#define MC_SHARED_CHREMAP 0x2008 96 97#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 98#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 99#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 100#define MC_VM_MX_L1_TLB_CNTL 0x2064 101#define ENABLE_L1_TLB (1 << 0) 102#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 103#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 104#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 105#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 106#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 107#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 108#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 109#define FUS_MC_VM_FB_OFFSET 0x2068 110 111#define MC_SHARED_BLACKOUT_CNTL 0x20ac 112#define MC_ARB_RAMCFG 0x2760 113#define NOOFBANK_SHIFT 0 114#define NOOFBANK_MASK 0x00000003 115#define NOOFRANK_SHIFT 2 116#define NOOFRANK_MASK 0x00000004 117#define NOOFROWS_SHIFT 3 118#define NOOFROWS_MASK 0x00000038 119#define NOOFCOLS_SHIFT 6 120#define NOOFCOLS_MASK 0x000000C0 121#define CHANSIZE_SHIFT 8 122#define CHANSIZE_MASK 0x00000100 123#define BURSTLENGTH_SHIFT 9 124#define BURSTLENGTH_MASK 0x00000200 125#define CHANSIZE_OVERRIDE (1 << 11) 126#define MC_SEQ_SUP_CNTL 0x28c8 127#define RUN_MASK (1 << 0) 128#define MC_SEQ_SUP_PGM 0x28cc 129#define MC_IO_PAD_CNTL_D0 0x29d0 130#define MEM_FALL_OUT_CMD (1 << 8) 131#define MC_SEQ_MISC0 0x2a00 132#define MC_SEQ_MISC0_GDDR5_SHIFT 28 133#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 134#define MC_SEQ_MISC0_GDDR5_VALUE 5 135#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 136#define MC_SEQ_IO_DEBUG_DATA 0x2a48 137 138#define HDP_HOST_PATH_CNTL 0x2C00 139#define HDP_NONSURFACE_BASE 0x2C04 140#define HDP_NONSURFACE_INFO 0x2C08 141#define HDP_NONSURFACE_SIZE 0x2C0C 142#define HDP_ADDR_CONFIG 0x2F48 143#define HDP_MISC_CNTL 0x2F4C 144#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 145 146#define CC_SYS_RB_BACKEND_DISABLE 0x3F88 147#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C 148#define CGTS_SYS_TCC_DISABLE 0x3F90 149#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 150 151#define CONFIG_MEMSIZE 0x5428 152 153#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 154#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 155 156#define GRBM_CNTL 0x8000 157#define GRBM_READ_TIMEOUT(x) ((x) << 0) 158#define GRBM_STATUS 0x8010 159#define CMDFIFO_AVAIL_MASK 0x0000000F 160#define RING2_RQ_PENDING (1 << 4) 161#define SRBM_RQ_PENDING (1 << 5) 162#define RING1_RQ_PENDING (1 << 6) 163#define CF_RQ_PENDING (1 << 7) 164#define PF_RQ_PENDING (1 << 8) 165#define GDS_DMA_RQ_PENDING (1 << 9) 166#define GRBM_EE_BUSY (1 << 10) 167#define SX_CLEAN (1 << 11) 168#define DB_CLEAN (1 << 12) 169#define CB_CLEAN (1 << 13) 170#define TA_BUSY (1 << 14) 171#define GDS_BUSY (1 << 15) 172#define VGT_BUSY_NO_DMA (1 << 16) 173#define VGT_BUSY (1 << 17) 174#define IA_BUSY_NO_DMA (1 << 18) 175#define IA_BUSY (1 << 19) 176#define SX_BUSY (1 << 20) 177#define SH_BUSY (1 << 21) 178#define SPI_BUSY (1 << 22) 179#define SC_BUSY (1 << 24) 180#define PA_BUSY (1 << 25) 181#define DB_BUSY (1 << 26) 182#define CP_COHERENCY_BUSY (1 << 28) 183#define CP_BUSY (1 << 29) 184#define CB_BUSY (1 << 30) 185#define GUI_ACTIVE (1 << 31) 186#define GRBM_STATUS_SE0 0x8014 187#define GRBM_STATUS_SE1 0x8018 188#define SE_SX_CLEAN (1 << 0) 189#define SE_DB_CLEAN (1 << 1) 190#define SE_CB_CLEAN (1 << 2) 191#define SE_VGT_BUSY (1 << 23) 192#define SE_PA_BUSY (1 << 24) 193#define SE_TA_BUSY (1 << 25) 194#define SE_SX_BUSY (1 << 26) 195#define SE_SPI_BUSY (1 << 27) 196#define SE_SH_BUSY (1 << 28) 197#define SE_SC_BUSY (1 << 29) 198#define SE_DB_BUSY (1 << 30) 199#define SE_CB_BUSY (1 << 31) 200#define GRBM_SOFT_RESET 0x8020 201#define SOFT_RESET_CP (1 << 0) 202#define SOFT_RESET_CB (1 << 1) 203#define SOFT_RESET_DB (1 << 3) 204#define SOFT_RESET_GDS (1 << 4) 205#define SOFT_RESET_PA (1 << 5) 206#define SOFT_RESET_SC (1 << 6) 207#define SOFT_RESET_SPI (1 << 8) 208#define SOFT_RESET_SH (1 << 9) 209#define SOFT_RESET_SX (1 << 10) 210#define SOFT_RESET_TC (1 << 11) 211#define SOFT_RESET_TA (1 << 12) 212#define SOFT_RESET_VGT (1 << 14) 213#define SOFT_RESET_IA (1 << 15) 214 215#define SCRATCH_REG0 0x8500 216#define SCRATCH_REG1 0x8504 217#define SCRATCH_REG2 0x8508 218#define SCRATCH_REG3 0x850C 219#define SCRATCH_REG4 0x8510 220#define SCRATCH_REG5 0x8514 221#define SCRATCH_REG6 0x8518 222#define SCRATCH_REG7 0x851C 223#define SCRATCH_UMSK 0x8540 224#define SCRATCH_ADDR 0x8544 225#define CP_SEM_WAIT_TIMER 0x85BC 226#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 227#define CP_COHER_CNTL2 0x85E8 228#define CP_ME_CNTL 0x86D8 229#define CP_ME_HALT (1 << 28) 230#define CP_PFP_HALT (1 << 26) 231#define CP_RB2_RPTR 0x86f8 232#define CP_RB1_RPTR 0x86fc 233#define CP_RB0_RPTR 0x8700 234#define CP_RB_WPTR_DELAY 0x8704 235#define CP_MEQ_THRESHOLDS 0x8764 236#define MEQ1_START(x) ((x) << 0) 237#define MEQ2_START(x) ((x) << 8) 238#define CP_PERFMON_CNTL 0x87FC 239 240#define VGT_CACHE_INVALIDATION 0x88C4 241#define CACHE_INVALIDATION(x) ((x) << 0) 242#define VC_ONLY 0 243#define TC_ONLY 1 244#define VC_AND_TC 2 245#define AUTO_INVLD_EN(x) ((x) << 6) 246#define NO_AUTO 0 247#define ES_AUTO 1 248#define GS_AUTO 2 249#define ES_AND_GS_AUTO 3 250#define VGT_GS_VERTEX_REUSE 0x88D4 251 252#define CC_GC_SHADER_PIPE_CONFIG 0x8950 253#define GC_USER_SHADER_PIPE_CONFIG 0x8954 254#define INACTIVE_QD_PIPES(x) ((x) << 8) 255#define INACTIVE_QD_PIPES_MASK 0x0000FF00 256#define INACTIVE_QD_PIPES_SHIFT 8 257#define INACTIVE_SIMDS(x) ((x) << 16) 258#define INACTIVE_SIMDS_MASK 0xFFFF0000 259#define INACTIVE_SIMDS_SHIFT 16 260 261#define VGT_PRIMITIVE_TYPE 0x8958 262#define VGT_NUM_INSTANCES 0x8974 263#define VGT_TF_RING_SIZE 0x8988 264#define VGT_OFFCHIP_LDS_BASE 0x89b4 265 266#define PA_SC_LINE_STIPPLE_STATE 0x8B10 267#define PA_CL_ENHANCE 0x8A14 268#define CLIP_VTX_REORDER_ENA (1 << 0) 269#define NUM_CLIP_SEQ(x) ((x) << 1) 270#define PA_SC_FIFO_SIZE 0x8BCC 271#define SC_PRIM_FIFO_SIZE(x) ((x) << 0) 272#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 273#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 274#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 275#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 276#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 277 278#define SQ_CONFIG 0x8C00 279#define VC_ENABLE (1 << 0) 280#define EXPORT_SRC_C (1 << 1) 281#define GFX_PRIO(x) ((x) << 2) 282#define CS1_PRIO(x) ((x) << 4) 283#define CS2_PRIO(x) ((x) << 6) 284#define SQ_GPR_RESOURCE_MGMT_1 0x8C04 285#define NUM_PS_GPRS(x) ((x) << 0) 286#define NUM_VS_GPRS(x) ((x) << 16) 287#define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 288#define SQ_ESGS_RING_SIZE 0x8c44 289#define SQ_GSVS_RING_SIZE 0x8c4c 290#define SQ_ESTMP_RING_BASE 0x8c50 291#define SQ_ESTMP_RING_SIZE 0x8c54 292#define SQ_GSTMP_RING_BASE 0x8c58 293#define SQ_GSTMP_RING_SIZE 0x8c5c 294#define SQ_VSTMP_RING_BASE 0x8c60 295#define SQ_VSTMP_RING_SIZE 0x8c64 296#define SQ_PSTMP_RING_BASE 0x8c68 297#define SQ_PSTMP_RING_SIZE 0x8c6c 298#define SQ_MS_FIFO_SIZES 0x8CF0 299#define CACHE_FIFO_SIZE(x) ((x) << 0) 300#define FETCH_FIFO_HIWATER(x) ((x) << 8) 301#define DONE_FIFO_HIWATER(x) ((x) << 16) 302#define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 303#define SQ_LSTMP_RING_BASE 0x8e10 304#define SQ_LSTMP_RING_SIZE 0x8e14 305#define SQ_HSTMP_RING_BASE 0x8e18 306#define SQ_HSTMP_RING_SIZE 0x8e1c 307#define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C 308#define DYN_GPR_ENABLE (1 << 8) 309#define SQ_CONST_MEM_BASE 0x8df8 310 311#define SX_EXPORT_BUFFER_SIZES 0x900C 312#define COLOR_BUFFER_SIZE(x) ((x) << 0) 313#define POSITION_BUFFER_SIZE(x) ((x) << 8) 314#define SMX_BUFFER_SIZE(x) ((x) << 16) 315#define SX_DEBUG_1 0x9058 316#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 317 318#define SPI_CONFIG_CNTL 0x9100 319#define GPR_WRITE_PRIORITY(x) ((x) << 0) 320#define SPI_CONFIG_CNTL_1 0x913C 321#define VTX_DONE_DELAY(x) ((x) << 0) 322#define INTERP_ONE_PRIM_PER_ROW (1 << 4) 323#define CRC_SIMD_ID_WADDR_DISABLE (1 << 8) 324 325#define CGTS_TCC_DISABLE 0x9148 326#define CGTS_USER_TCC_DISABLE 0x914C 327#define TCC_DISABLE_MASK 0xFFFF0000 328#define TCC_DISABLE_SHIFT 16 329#define CGTS_SM_CTRL_REG 0x9150 330#define OVERRIDE (1 << 21) 331 332#define TA_CNTL_AUX 0x9508 333#define DISABLE_CUBE_WRAP (1 << 0) 334#define DISABLE_CUBE_ANISO (1 << 1) 335 336#define TCP_CHAN_STEER_LO 0x960c 337#define TCP_CHAN_STEER_HI 0x9610 338 339#define CC_RB_BACKEND_DISABLE 0x98F4 340#define BACKEND_DISABLE(x) ((x) << 16) 341#define GB_ADDR_CONFIG 0x98F8 342#define NUM_PIPES(x) ((x) << 0) 343#define NUM_PIPES_MASK 0x00000007 344#define NUM_PIPES_SHIFT 0 345#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 346#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 347#define PIPE_INTERLEAVE_SIZE_SHIFT 4 348#define BANK_INTERLEAVE_SIZE(x) ((x) << 8) 349#define NUM_SHADER_ENGINES(x) ((x) << 12) 350#define NUM_SHADER_ENGINES_MASK 0x00003000 351#define NUM_SHADER_ENGINES_SHIFT 12 352#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 353#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 354#define SHADER_ENGINE_TILE_SIZE_SHIFT 16 355#define NUM_GPUS(x) ((x) << 20) 356#define NUM_GPUS_MASK 0x00700000 357#define NUM_GPUS_SHIFT 20 358#define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 359#define MULTI_GPU_TILE_SIZE_MASK 0x03000000 360#define MULTI_GPU_TILE_SIZE_SHIFT 24 361#define ROW_SIZE(x) ((x) << 28) 362#define ROW_SIZE_MASK 0x30000000 363#define ROW_SIZE_SHIFT 28 364#define NUM_LOWER_PIPES(x) ((x) << 30) 365#define NUM_LOWER_PIPES_MASK 0x40000000 366#define NUM_LOWER_PIPES_SHIFT 30 367#define GB_BACKEND_MAP 0x98FC 368 369#define CB_PERF_CTR0_SEL_0 0x9A20 370#define CB_PERF_CTR0_SEL_1 0x9A24 371#define CB_PERF_CTR1_SEL_0 0x9A28 372#define CB_PERF_CTR1_SEL_1 0x9A2C 373#define CB_PERF_CTR2_SEL_0 0x9A30 374#define CB_PERF_CTR2_SEL_1 0x9A34 375#define CB_PERF_CTR3_SEL_0 0x9A38 376#define CB_PERF_CTR3_SEL_1 0x9A3C 377 378#define GC_USER_RB_BACKEND_DISABLE 0x9B7C 379#define BACKEND_DISABLE_MASK 0x00FF0000 380#define BACKEND_DISABLE_SHIFT 16 381 382#define SMX_DC_CTL0 0xA020 383#define USE_HASH_FUNCTION (1 << 0) 384#define NUMBER_OF_SETS(x) ((x) << 1) 385#define FLUSH_ALL_ON_EVENT (1 << 10) 386#define STALL_ON_EVENT (1 << 11) 387#define SMX_EVENT_CTL 0xA02C 388#define ES_FLUSH_CTL(x) ((x) << 0) 389#define GS_FLUSH_CTL(x) ((x) << 3) 390#define ACK_FLUSH_CTL(x) ((x) << 6) 391#define SYNC_FLUSH_CTL (1 << 8) 392 393#define CP_RB0_BASE 0xC100 394#define CP_RB0_CNTL 0xC104 395#define RB_BUFSZ(x) ((x) << 0) 396#define RB_BLKSZ(x) ((x) << 8) 397#define RB_NO_UPDATE (1 << 27) 398#define RB_RPTR_WR_ENA (1 << 31) 399#define BUF_SWAP_32BIT (2 << 16) 400#define CP_RB0_RPTR_ADDR 0xC10C 401#define CP_RB0_RPTR_ADDR_HI 0xC110 402#define CP_RB0_WPTR 0xC114 403 404#define CP_INT_CNTL 0xC124 405# define CNTX_BUSY_INT_ENABLE (1 << 19) 406# define CNTX_EMPTY_INT_ENABLE (1 << 20) 407# define TIME_STAMP_INT_ENABLE (1 << 26) 408 409#define CP_RB1_BASE 0xC180 410#define CP_RB1_CNTL 0xC184 411#define CP_RB1_RPTR_ADDR 0xC188 412#define CP_RB1_RPTR_ADDR_HI 0xC18C 413#define CP_RB1_WPTR 0xC190 414#define CP_RB2_BASE 0xC194 415#define CP_RB2_CNTL 0xC198 416#define CP_RB2_RPTR_ADDR 0xC19C 417#define CP_RB2_RPTR_ADDR_HI 0xC1A0 418#define CP_RB2_WPTR 0xC1A4 419#define CP_PFP_UCODE_ADDR 0xC150 420#define CP_PFP_UCODE_DATA 0xC154 421#define CP_ME_RAM_RADDR 0xC158 422#define CP_ME_RAM_WADDR 0xC15C 423#define CP_ME_RAM_DATA 0xC160 424#define CP_DEBUG 0xC1FC 425 426#define VGT_EVENT_INITIATOR 0x28a90 427# define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 428# define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 429 430/* 431 * PM4 432 */ 433#define PACKET_TYPE0 0 434#define PACKET_TYPE1 1 435#define PACKET_TYPE2 2 436#define PACKET_TYPE3 3 437 438#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 439#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 440#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 441#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 442#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 443 (((reg) >> 2) & 0xFFFF) | \ 444 ((n) & 0x3FFF) << 16) 445#define CP_PACKET2 0x80000000 446#define PACKET2_PAD_SHIFT 0 447#define PACKET2_PAD_MASK (0x3fffffff << 0) 448 449#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 450 451#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 452 (((op) & 0xFF) << 8) | \ 453 ((n) & 0x3FFF) << 16) 454 455/* Packet 3 types */ 456#define PACKET3_NOP 0x10 457#define PACKET3_SET_BASE 0x11 458#define PACKET3_CLEAR_STATE 0x12 459#define PACKET3_INDEX_BUFFER_SIZE 0x13 460#define PACKET3_DEALLOC_STATE 0x14 461#define PACKET3_DISPATCH_DIRECT 0x15 462#define PACKET3_DISPATCH_INDIRECT 0x16 463#define PACKET3_INDIRECT_BUFFER_END 0x17 464#define PACKET3_MODE_CONTROL 0x18 465#define PACKET3_SET_PREDICATION 0x20 466#define PACKET3_REG_RMW 0x21 467#define PACKET3_COND_EXEC 0x22 468#define PACKET3_PRED_EXEC 0x23 469#define PACKET3_DRAW_INDIRECT 0x24 470#define PACKET3_DRAW_INDEX_INDIRECT 0x25 471#define PACKET3_INDEX_BASE 0x26 472#define PACKET3_DRAW_INDEX_2 0x27 473#define PACKET3_CONTEXT_CONTROL 0x28 474#define PACKET3_DRAW_INDEX_OFFSET 0x29 475#define PACKET3_INDEX_TYPE 0x2A 476#define PACKET3_DRAW_INDEX 0x2B 477#define PACKET3_DRAW_INDEX_AUTO 0x2D 478#define PACKET3_DRAW_INDEX_IMMD 0x2E 479#define PACKET3_NUM_INSTANCES 0x2F 480#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 481#define PACKET3_INDIRECT_BUFFER 0x32 482#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 483#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 484#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 485#define PACKET3_WRITE_DATA 0x37 486#define PACKET3_MEM_SEMAPHORE 0x39 487#define PACKET3_MPEG_INDEX 0x3A 488#define PACKET3_WAIT_REG_MEM 0x3C 489#define PACKET3_MEM_WRITE 0x3D 490#define PACKET3_SURFACE_SYNC 0x43 491# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 492# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 493# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 494# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 495# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 496# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 497# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 498# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 499# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 500# define PACKET3_CB8_DEST_BASE_ENA (1 << 15) 501# define PACKET3_CB9_DEST_BASE_ENA (1 << 16) 502# define PACKET3_CB10_DEST_BASE_ENA (1 << 17) 503# define PACKET3_CB11_DEST_BASE_ENA (1 << 18) 504# define PACKET3_FULL_CACHE_ENA (1 << 20) 505# define PACKET3_TC_ACTION_ENA (1 << 23) 506# define PACKET3_CB_ACTION_ENA (1 << 25) 507# define PACKET3_DB_ACTION_ENA (1 << 26) 508# define PACKET3_SH_ACTION_ENA (1 << 27) 509# define PACKET3_SX_ACTION_ENA (1 << 28) 510#define PACKET3_ME_INITIALIZE 0x44 511#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 512#define PACKET3_COND_WRITE 0x45 513#define PACKET3_EVENT_WRITE 0x46 514#define EVENT_TYPE(x) ((x) << 0) 515#define EVENT_INDEX(x) ((x) << 8) 516 /* 0 - any non-TS event 517 * 1 - ZPASS_DONE 518 * 2 - SAMPLE_PIPELINESTAT 519 * 3 - SAMPLE_STREAMOUTSTAT* 520 * 4 - *S_PARTIAL_FLUSH 521 * 5 - TS events 522 */ 523#define PACKET3_EVENT_WRITE_EOP 0x47 524#define DATA_SEL(x) ((x) << 29) 525 /* 0 - discard 526 * 1 - send low 32bit data 527 * 2 - send 64bit data 528 * 3 - send 64bit counter value 529 */ 530#define INT_SEL(x) ((x) << 24) 531 /* 0 - none 532 * 1 - interrupt only (DATA_SEL = 0) 533 * 2 - interrupt when data write is confirmed 534 */ 535#define PACKET3_EVENT_WRITE_EOS 0x48 536#define PACKET3_PREAMBLE_CNTL 0x4A 537# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 538# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 539#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C 540#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D 541#define PACKET3_ALU_PS_CONST_UPDATE 0x4E 542#define PACKET3_ALU_VS_CONST_UPDATE 0x4F 543#define PACKET3_ONE_REG_WRITE 0x57 544#define PACKET3_SET_CONFIG_REG 0x68 545#define PACKET3_SET_CONFIG_REG_START 0x00008000 546#define PACKET3_SET_CONFIG_REG_END 0x0000ac00 547#define PACKET3_SET_CONTEXT_REG 0x69 548#define PACKET3_SET_CONTEXT_REG_START 0x00028000 549#define PACKET3_SET_CONTEXT_REG_END 0x00029000 550#define PACKET3_SET_ALU_CONST 0x6A 551/* alu const buffers only; no reg file */ 552#define PACKET3_SET_BOOL_CONST 0x6B 553#define PACKET3_SET_BOOL_CONST_START 0x0003a500 554#define PACKET3_SET_BOOL_CONST_END 0x0003a518 555#define PACKET3_SET_LOOP_CONST 0x6C 556#define PACKET3_SET_LOOP_CONST_START 0x0003a200 557#define PACKET3_SET_LOOP_CONST_END 0x0003a500 558#define PACKET3_SET_RESOURCE 0x6D 559#define PACKET3_SET_RESOURCE_START 0x00030000 560#define PACKET3_SET_RESOURCE_END 0x00038000 561#define PACKET3_SET_SAMPLER 0x6E 562#define PACKET3_SET_SAMPLER_START 0x0003c000 563#define PACKET3_SET_SAMPLER_END 0x0003c600 564#define PACKET3_SET_CTL_CONST 0x6F 565#define PACKET3_SET_CTL_CONST_START 0x0003cff0 566#define PACKET3_SET_CTL_CONST_END 0x0003ff0c 567#define PACKET3_SET_RESOURCE_OFFSET 0x70 568#define PACKET3_SET_ALU_CONST_VS 0x71 569#define PACKET3_SET_ALU_CONST_DI 0x72 570#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 571#define PACKET3_SET_RESOURCE_INDIRECT 0x74 572#define PACKET3_SET_APPEND_CNT 0x75 573 574#endif 575 576