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27#include <linux/module.h>
28
29#include "drmP.h"
30#include "vmwgfx_drv.h"
31#include "ttm/ttm_placement.h"
32#include "ttm/ttm_bo_driver.h"
33#include "ttm/ttm_object.h"
34#include "ttm/ttm_module.h"
35
36#define VMWGFX_DRIVER_NAME "vmwgfx"
37#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
38#define VMWGFX_CHIP_SVGAII 0
39#define VMW_FB_RESERVATION 0
40
41#define VMW_MIN_INITIAL_WIDTH 800
42#define VMW_MIN_INITIAL_HEIGHT 600
43
44
45
46
47
48
49#define DRM_IOCTL_VMW_GET_PARAM \
50 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
51 struct drm_vmw_getparam_arg)
52#define DRM_IOCTL_VMW_ALLOC_DMABUF \
53 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
54 union drm_vmw_alloc_dmabuf_arg)
55#define DRM_IOCTL_VMW_UNREF_DMABUF \
56 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
57 struct drm_vmw_unref_dmabuf_arg)
58#define DRM_IOCTL_VMW_CURSOR_BYPASS \
59 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
60 struct drm_vmw_cursor_bypass_arg)
61
62#define DRM_IOCTL_VMW_CONTROL_STREAM \
63 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
64 struct drm_vmw_control_stream_arg)
65#define DRM_IOCTL_VMW_CLAIM_STREAM \
66 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
67 struct drm_vmw_stream_arg)
68#define DRM_IOCTL_VMW_UNREF_STREAM \
69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
70 struct drm_vmw_stream_arg)
71
72#define DRM_IOCTL_VMW_CREATE_CONTEXT \
73 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
74 struct drm_vmw_context_arg)
75#define DRM_IOCTL_VMW_UNREF_CONTEXT \
76 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
77 struct drm_vmw_context_arg)
78#define DRM_IOCTL_VMW_CREATE_SURFACE \
79 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
80 union drm_vmw_surface_create_arg)
81#define DRM_IOCTL_VMW_UNREF_SURFACE \
82 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
83 struct drm_vmw_surface_arg)
84#define DRM_IOCTL_VMW_REF_SURFACE \
85 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
86 union drm_vmw_surface_reference_arg)
87#define DRM_IOCTL_VMW_EXECBUF \
88 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
89 struct drm_vmw_execbuf_arg)
90#define DRM_IOCTL_VMW_GET_3D_CAP \
91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
92 struct drm_vmw_get_3d_cap_arg)
93#define DRM_IOCTL_VMW_FENCE_WAIT \
94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
95 struct drm_vmw_fence_wait_arg)
96#define DRM_IOCTL_VMW_FENCE_SIGNALED \
97 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
98 struct drm_vmw_fence_signaled_arg)
99#define DRM_IOCTL_VMW_FENCE_UNREF \
100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
101 struct drm_vmw_fence_arg)
102#define DRM_IOCTL_VMW_FENCE_EVENT \
103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
104 struct drm_vmw_fence_event_arg)
105#define DRM_IOCTL_VMW_PRESENT \
106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
107 struct drm_vmw_present_arg)
108#define DRM_IOCTL_VMW_PRESENT_READBACK \
109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
110 struct drm_vmw_present_readback_arg)
111#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
113 struct drm_vmw_update_layout_arg)
114
115
116
117
118
119
120#define VMW_IOCTL_DEF(ioctl, func, flags) \
121 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
122
123
124
125
126
127static struct drm_ioctl_desc vmw_ioctls[] = {
128 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
129 DRM_AUTH | DRM_UNLOCKED),
130 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
131 DRM_AUTH | DRM_UNLOCKED),
132 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
133 DRM_AUTH | DRM_UNLOCKED),
134 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
135 vmw_kms_cursor_bypass_ioctl,
136 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
137
138 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
139 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
140 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
141 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
142 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
143 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
144
145 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
146 DRM_AUTH | DRM_UNLOCKED),
147 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
148 DRM_AUTH | DRM_UNLOCKED),
149 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
150 DRM_AUTH | DRM_UNLOCKED),
151 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
152 DRM_AUTH | DRM_UNLOCKED),
153 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
154 DRM_AUTH | DRM_UNLOCKED),
155 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
156 DRM_AUTH | DRM_UNLOCKED),
157 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
158 DRM_AUTH | DRM_UNLOCKED),
159 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
160 vmw_fence_obj_signaled_ioctl,
161 DRM_AUTH | DRM_UNLOCKED),
162 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
163 DRM_AUTH | DRM_UNLOCKED),
164 VMW_IOCTL_DEF(VMW_FENCE_EVENT,
165 vmw_fence_event_ioctl,
166 DRM_AUTH | DRM_UNLOCKED),
167 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
168 DRM_AUTH | DRM_UNLOCKED),
169
170
171 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
172 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
173 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
174 vmw_present_readback_ioctl,
175 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
176 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
177 vmw_kms_update_layout_ioctl,
178 DRM_MASTER | DRM_UNLOCKED),
179};
180
181static struct pci_device_id vmw_pci_id_list[] = {
182 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
183 {0, 0, 0}
184};
185
186static int enable_fbdev;
187
188static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
189static void vmw_master_init(struct vmw_master *);
190static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
191 void *ptr);
192
193MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
194module_param_named(enable_fbdev, enable_fbdev, int, 0600);
195
196static void vmw_print_capabilities(uint32_t capabilities)
197{
198 DRM_INFO("Capabilities:\n");
199 if (capabilities & SVGA_CAP_RECT_COPY)
200 DRM_INFO(" Rect copy.\n");
201 if (capabilities & SVGA_CAP_CURSOR)
202 DRM_INFO(" Cursor.\n");
203 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
204 DRM_INFO(" Cursor bypass.\n");
205 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
206 DRM_INFO(" Cursor bypass 2.\n");
207 if (capabilities & SVGA_CAP_8BIT_EMULATION)
208 DRM_INFO(" 8bit emulation.\n");
209 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
210 DRM_INFO(" Alpha cursor.\n");
211 if (capabilities & SVGA_CAP_3D)
212 DRM_INFO(" 3D.\n");
213 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
214 DRM_INFO(" Extended Fifo.\n");
215 if (capabilities & SVGA_CAP_MULTIMON)
216 DRM_INFO(" Multimon.\n");
217 if (capabilities & SVGA_CAP_PITCHLOCK)
218 DRM_INFO(" Pitchlock.\n");
219 if (capabilities & SVGA_CAP_IRQMASK)
220 DRM_INFO(" Irq mask.\n");
221 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
222 DRM_INFO(" Display Topology.\n");
223 if (capabilities & SVGA_CAP_GMR)
224 DRM_INFO(" GMR.\n");
225 if (capabilities & SVGA_CAP_TRACES)
226 DRM_INFO(" Traces.\n");
227 if (capabilities & SVGA_CAP_GMR2)
228 DRM_INFO(" GMR2.\n");
229 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
230 DRM_INFO(" Screen Object 2.\n");
231}
232
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242
243
244
245
246
247static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
248{
249 struct ttm_bo_kmap_obj map;
250 volatile SVGA3dQueryResult *result;
251 bool dummy;
252 int ret;
253 struct ttm_bo_device *bdev = &dev_priv->bdev;
254 struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
255
256 ttm_bo_reserve(bo, false, false, false, 0);
257 spin_lock(&bdev->fence_lock);
258 ret = ttm_bo_wait(bo, false, false, false);
259 spin_unlock(&bdev->fence_lock);
260 if (unlikely(ret != 0))
261 (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
262 10*HZ);
263
264 ret = ttm_bo_kmap(bo, 0, 1, &map);
265 if (likely(ret == 0)) {
266 result = ttm_kmap_obj_virtual(&map, &dummy);
267 result->totalSize = sizeof(*result);
268 result->state = SVGA3D_QUERYSTATE_PENDING;
269 result->result32 = 0xff;
270 ttm_bo_kunmap(&map);
271 } else
272 DRM_ERROR("Dummy query buffer map failed.\n");
273 ttm_bo_unreserve(bo);
274}
275
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280
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285
286
287
288static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
289{
290 return ttm_bo_create(&dev_priv->bdev,
291 PAGE_SIZE,
292 ttm_bo_type_device,
293 &vmw_vram_sys_placement,
294 0, 0, false, NULL,
295 &dev_priv->dummy_query_bo);
296}
297
298
299static int vmw_request_device(struct vmw_private *dev_priv)
300{
301 int ret;
302
303 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
304 if (unlikely(ret != 0)) {
305 DRM_ERROR("Unable to initialize FIFO.\n");
306 return ret;
307 }
308 vmw_fence_fifo_up(dev_priv->fman);
309 ret = vmw_dummy_query_bo_create(dev_priv);
310 if (unlikely(ret != 0))
311 goto out_no_query_bo;
312 vmw_dummy_query_bo_prepare(dev_priv);
313
314 return 0;
315
316out_no_query_bo:
317 vmw_fence_fifo_down(dev_priv->fman);
318 vmw_fifo_release(dev_priv, &dev_priv->fifo);
319 return ret;
320}
321
322static void vmw_release_device(struct vmw_private *dev_priv)
323{
324
325
326
327
328
329 BUG_ON(dev_priv->pinned_bo != NULL);
330
331 ttm_bo_unref(&dev_priv->dummy_query_bo);
332 vmw_fence_fifo_down(dev_priv->fman);
333 vmw_fifo_release(dev_priv, &dev_priv->fifo);
334}
335
336
337
338
339
340
341
342int vmw_3d_resource_inc(struct vmw_private *dev_priv,
343 bool unhide_svga)
344{
345 int ret = 0;
346
347 mutex_lock(&dev_priv->release_mutex);
348 if (unlikely(dev_priv->num_3d_resources++ == 0)) {
349 ret = vmw_request_device(dev_priv);
350 if (unlikely(ret != 0))
351 --dev_priv->num_3d_resources;
352 } else if (unhide_svga) {
353 mutex_lock(&dev_priv->hw_mutex);
354 vmw_write(dev_priv, SVGA_REG_ENABLE,
355 vmw_read(dev_priv, SVGA_REG_ENABLE) &
356 ~SVGA_REG_ENABLE_HIDE);
357 mutex_unlock(&dev_priv->hw_mutex);
358 }
359
360 mutex_unlock(&dev_priv->release_mutex);
361 return ret;
362}
363
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365
366
367
368
369
370
371
372void vmw_3d_resource_dec(struct vmw_private *dev_priv,
373 bool hide_svga)
374{
375 int32_t n3d;
376
377 mutex_lock(&dev_priv->release_mutex);
378 if (unlikely(--dev_priv->num_3d_resources == 0))
379 vmw_release_device(dev_priv);
380 else if (hide_svga) {
381 mutex_lock(&dev_priv->hw_mutex);
382 vmw_write(dev_priv, SVGA_REG_ENABLE,
383 vmw_read(dev_priv, SVGA_REG_ENABLE) |
384 SVGA_REG_ENABLE_HIDE);
385 mutex_unlock(&dev_priv->hw_mutex);
386 }
387
388 n3d = (int32_t) dev_priv->num_3d_resources;
389 mutex_unlock(&dev_priv->release_mutex);
390
391 BUG_ON(n3d < 0);
392}
393
394
395
396
397
398
399
400
401
402
403static void vmw_get_initial_size(struct vmw_private *dev_priv)
404{
405 uint32_t width;
406 uint32_t height;
407
408 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
409 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
410
411 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
412 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
413
414 if (width > dev_priv->fb_max_width ||
415 height > dev_priv->fb_max_height) {
416
417
418
419
420
421 width = VMW_MIN_INITIAL_WIDTH;
422 height = VMW_MIN_INITIAL_HEIGHT;
423 }
424
425 dev_priv->initial_width = width;
426 dev_priv->initial_height = height;
427}
428
429static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
430{
431 struct vmw_private *dev_priv;
432 int ret;
433 uint32_t svga_id;
434
435 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
436 if (unlikely(dev_priv == NULL)) {
437 DRM_ERROR("Failed allocating a device private struct.\n");
438 return -ENOMEM;
439 }
440 memset(dev_priv, 0, sizeof(*dev_priv));
441
442 pci_set_master(dev->pdev);
443
444 dev_priv->dev = dev;
445 dev_priv->vmw_chipset = chipset;
446 dev_priv->last_read_seqno = (uint32_t) -100;
447 mutex_init(&dev_priv->hw_mutex);
448 mutex_init(&dev_priv->cmdbuf_mutex);
449 mutex_init(&dev_priv->release_mutex);
450 rwlock_init(&dev_priv->resource_lock);
451 idr_init(&dev_priv->context_idr);
452 idr_init(&dev_priv->surface_idr);
453 idr_init(&dev_priv->stream_idr);
454 mutex_init(&dev_priv->init_mutex);
455 init_waitqueue_head(&dev_priv->fence_queue);
456 init_waitqueue_head(&dev_priv->fifo_queue);
457 dev_priv->fence_queue_waiters = 0;
458 atomic_set(&dev_priv->fifo_queue_waiters, 0);
459 INIT_LIST_HEAD(&dev_priv->surface_lru);
460 dev_priv->used_memory_size = 0;
461
462 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
463 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
464 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
465
466 dev_priv->enable_fb = enable_fbdev;
467
468 mutex_lock(&dev_priv->hw_mutex);
469
470 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
471 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
472 if (svga_id != SVGA_ID_2) {
473 ret = -ENOSYS;
474 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
475 mutex_unlock(&dev_priv->hw_mutex);
476 goto out_err0;
477 }
478
479 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
480
481 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
482 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
483 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
484 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
485
486 vmw_get_initial_size(dev_priv);
487
488 if (dev_priv->capabilities & SVGA_CAP_GMR) {
489 dev_priv->max_gmr_descriptors =
490 vmw_read(dev_priv,
491 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
492 dev_priv->max_gmr_ids =
493 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
494 }
495 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
496 dev_priv->max_gmr_pages =
497 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
498 dev_priv->memory_size =
499 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
500 dev_priv->memory_size -= dev_priv->vram_size;
501 } else {
502
503
504
505
506 dev_priv->memory_size = 512*1024*1024;
507 }
508
509 mutex_unlock(&dev_priv->hw_mutex);
510
511 vmw_print_capabilities(dev_priv->capabilities);
512
513 if (dev_priv->capabilities & SVGA_CAP_GMR) {
514 DRM_INFO("Max GMR ids is %u\n",
515 (unsigned)dev_priv->max_gmr_ids);
516 DRM_INFO("Max GMR descriptors is %u\n",
517 (unsigned)dev_priv->max_gmr_descriptors);
518 }
519 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
520 DRM_INFO("Max number of GMR pages is %u\n",
521 (unsigned)dev_priv->max_gmr_pages);
522 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
523 (unsigned)dev_priv->memory_size / 1024);
524 }
525 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
526 dev_priv->vram_start, dev_priv->vram_size / 1024);
527 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
528 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
529
530 ret = vmw_ttm_global_init(dev_priv);
531 if (unlikely(ret != 0))
532 goto out_err0;
533
534
535 vmw_master_init(&dev_priv->fbdev_master);
536 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
537 dev_priv->active_master = &dev_priv->fbdev_master;
538
539
540 ret = ttm_bo_device_init(&dev_priv->bdev,
541 dev_priv->bo_global_ref.ref.object,
542 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
543 false);
544 if (unlikely(ret != 0)) {
545 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
546 goto out_err1;
547 }
548
549 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
550 (dev_priv->vram_size >> PAGE_SHIFT));
551 if (unlikely(ret != 0)) {
552 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
553 goto out_err2;
554 }
555
556 dev_priv->has_gmr = true;
557 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
558 dev_priv->max_gmr_ids) != 0) {
559 DRM_INFO("No GMR memory available. "
560 "Graphics memory resources are very limited.\n");
561 dev_priv->has_gmr = false;
562 }
563
564 dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
565 dev_priv->mmio_size, DRM_MTRR_WC);
566
567 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
568 dev_priv->mmio_size);
569
570 if (unlikely(dev_priv->mmio_virt == NULL)) {
571 ret = -ENOMEM;
572 DRM_ERROR("Failed mapping MMIO.\n");
573 goto out_err3;
574 }
575
576
577 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
578 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
579 !vmw_fifo_have_pitchlock(dev_priv)) {
580 ret = -ENOSYS;
581 DRM_ERROR("Hardware has no pitchlock\n");
582 goto out_err4;
583 }
584
585 dev_priv->tdev = ttm_object_device_init
586 (dev_priv->mem_global_ref.object, 12);
587
588 if (unlikely(dev_priv->tdev == NULL)) {
589 DRM_ERROR("Unable to initialize TTM object management.\n");
590 ret = -ENOMEM;
591 goto out_err4;
592 }
593
594 dev->dev_private = dev_priv;
595
596 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
597 dev_priv->stealth = (ret != 0);
598 if (dev_priv->stealth) {
599
600
601
602
603 DRM_INFO("It appears like vesafb is loaded. "
604 "Ignore above error if any.\n");
605 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
606 if (unlikely(ret != 0)) {
607 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
608 goto out_no_device;
609 }
610 }
611
612 dev_priv->fman = vmw_fence_manager_init(dev_priv);
613 if (unlikely(dev_priv->fman == NULL))
614 goto out_no_fman;
615
616
617 ret = vmw_3d_resource_inc(dev_priv, true);
618 if (unlikely(ret != 0))
619 goto out_no_fifo;
620 vmw_kms_save_vga(dev_priv);
621
622
623 ret = vmw_kms_init(dev_priv);
624 if (unlikely(ret != 0))
625 goto out_no_kms;
626 vmw_overlay_init(dev_priv);
627
628
629 DRM_INFO("Detected %sdevice 3D availability.\n",
630 vmw_fifo_have_3d(dev_priv) ?
631 "" : "no ");
632
633
634 if (dev_priv->enable_fb) {
635 vmw_fb_init(dev_priv);
636 } else {
637 vmw_kms_restore_vga(dev_priv);
638 vmw_3d_resource_dec(dev_priv, true);
639 }
640
641 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
642 ret = drm_irq_install(dev);
643 if (unlikely(ret != 0)) {
644 DRM_ERROR("Failed installing irq: %d\n", ret);
645 goto out_no_irq;
646 }
647 }
648
649 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
650 register_pm_notifier(&dev_priv->pm_nb);
651
652 return 0;
653
654out_no_irq:
655 if (dev_priv->enable_fb)
656 vmw_fb_close(dev_priv);
657 vmw_overlay_close(dev_priv);
658 vmw_kms_close(dev_priv);
659out_no_kms:
660
661 if (dev_priv->enable_fb) {
662 vmw_kms_restore_vga(dev_priv);
663 vmw_3d_resource_dec(dev_priv, false);
664 }
665out_no_fifo:
666 vmw_fence_manager_takedown(dev_priv->fman);
667out_no_fman:
668 if (dev_priv->stealth)
669 pci_release_region(dev->pdev, 2);
670 else
671 pci_release_regions(dev->pdev);
672out_no_device:
673 ttm_object_device_release(&dev_priv->tdev);
674out_err4:
675 iounmap(dev_priv->mmio_virt);
676out_err3:
677 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
678 dev_priv->mmio_size, DRM_MTRR_WC);
679 if (dev_priv->has_gmr)
680 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
681 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
682out_err2:
683 (void)ttm_bo_device_release(&dev_priv->bdev);
684out_err1:
685 vmw_ttm_global_release(dev_priv);
686out_err0:
687 idr_destroy(&dev_priv->surface_idr);
688 idr_destroy(&dev_priv->context_idr);
689 idr_destroy(&dev_priv->stream_idr);
690 kfree(dev_priv);
691 return ret;
692}
693
694static int vmw_driver_unload(struct drm_device *dev)
695{
696 struct vmw_private *dev_priv = vmw_priv(dev);
697
698 unregister_pm_notifier(&dev_priv->pm_nb);
699
700 if (dev_priv->ctx.cmd_bounce)
701 vfree(dev_priv->ctx.cmd_bounce);
702 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
703 drm_irq_uninstall(dev_priv->dev);
704 if (dev_priv->enable_fb) {
705 vmw_fb_close(dev_priv);
706 vmw_kms_restore_vga(dev_priv);
707 vmw_3d_resource_dec(dev_priv, false);
708 }
709 vmw_kms_close(dev_priv);
710 vmw_overlay_close(dev_priv);
711 vmw_fence_manager_takedown(dev_priv->fman);
712 if (dev_priv->stealth)
713 pci_release_region(dev->pdev, 2);
714 else
715 pci_release_regions(dev->pdev);
716
717 ttm_object_device_release(&dev_priv->tdev);
718 iounmap(dev_priv->mmio_virt);
719 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
720 dev_priv->mmio_size, DRM_MTRR_WC);
721 if (dev_priv->has_gmr)
722 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
723 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
724 (void)ttm_bo_device_release(&dev_priv->bdev);
725 vmw_ttm_global_release(dev_priv);
726 idr_destroy(&dev_priv->surface_idr);
727 idr_destroy(&dev_priv->context_idr);
728 idr_destroy(&dev_priv->stream_idr);
729
730 kfree(dev_priv);
731
732 return 0;
733}
734
735static void vmw_preclose(struct drm_device *dev,
736 struct drm_file *file_priv)
737{
738 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
739 struct vmw_private *dev_priv = vmw_priv(dev);
740
741 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
742}
743
744static void vmw_postclose(struct drm_device *dev,
745 struct drm_file *file_priv)
746{
747 struct vmw_fpriv *vmw_fp;
748
749 vmw_fp = vmw_fpriv(file_priv);
750 ttm_object_file_release(&vmw_fp->tfile);
751 if (vmw_fp->locked_master)
752 drm_master_put(&vmw_fp->locked_master);
753 kfree(vmw_fp);
754}
755
756static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
757{
758 struct vmw_private *dev_priv = vmw_priv(dev);
759 struct vmw_fpriv *vmw_fp;
760 int ret = -ENOMEM;
761
762 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
763 if (unlikely(vmw_fp == NULL))
764 return ret;
765
766 INIT_LIST_HEAD(&vmw_fp->fence_events);
767 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
768 if (unlikely(vmw_fp->tfile == NULL))
769 goto out_no_tfile;
770
771 file_priv->driver_priv = vmw_fp;
772
773 if (unlikely(dev_priv->bdev.dev_mapping == NULL))
774 dev_priv->bdev.dev_mapping =
775 file_priv->filp->f_path.dentry->d_inode->i_mapping;
776
777 return 0;
778
779out_no_tfile:
780 kfree(vmw_fp);
781 return ret;
782}
783
784static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
785 unsigned long arg)
786{
787 struct drm_file *file_priv = filp->private_data;
788 struct drm_device *dev = file_priv->minor->dev;
789 unsigned int nr = DRM_IOCTL_NR(cmd);
790
791
792
793
794
795 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
796 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
797 struct drm_ioctl_desc *ioctl =
798 &vmw_ioctls[nr - DRM_COMMAND_BASE];
799
800 if (unlikely(ioctl->cmd_drv != cmd)) {
801 DRM_ERROR("Invalid command format, ioctl %d\n",
802 nr - DRM_COMMAND_BASE);
803 return -EINVAL;
804 }
805 }
806
807 return drm_ioctl(filp, cmd, arg);
808}
809
810static int vmw_firstopen(struct drm_device *dev)
811{
812 struct vmw_private *dev_priv = vmw_priv(dev);
813 dev_priv->is_opened = true;
814
815 return 0;
816}
817
818static void vmw_lastclose(struct drm_device *dev)
819{
820 struct vmw_private *dev_priv = vmw_priv(dev);
821 struct drm_crtc *crtc;
822 struct drm_mode_set set;
823 int ret;
824
825
826
827
828
829 if (!dev_priv->is_opened)
830 return;
831
832 dev_priv->is_opened = false;
833 set.x = 0;
834 set.y = 0;
835 set.fb = NULL;
836 set.mode = NULL;
837 set.connectors = NULL;
838 set.num_connectors = 0;
839
840 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
841 set.crtc = crtc;
842 ret = crtc->funcs->set_config(&set);
843 WARN_ON(ret != 0);
844 }
845
846}
847
848static void vmw_master_init(struct vmw_master *vmaster)
849{
850 ttm_lock_init(&vmaster->lock);
851 INIT_LIST_HEAD(&vmaster->fb_surf);
852 mutex_init(&vmaster->fb_surf_mutex);
853}
854
855static int vmw_master_create(struct drm_device *dev,
856 struct drm_master *master)
857{
858 struct vmw_master *vmaster;
859
860 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
861 if (unlikely(vmaster == NULL))
862 return -ENOMEM;
863
864 vmw_master_init(vmaster);
865 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
866 master->driver_priv = vmaster;
867
868 return 0;
869}
870
871static void vmw_master_destroy(struct drm_device *dev,
872 struct drm_master *master)
873{
874 struct vmw_master *vmaster = vmw_master(master);
875
876 master->driver_priv = NULL;
877 kfree(vmaster);
878}
879
880
881static int vmw_master_set(struct drm_device *dev,
882 struct drm_file *file_priv,
883 bool from_open)
884{
885 struct vmw_private *dev_priv = vmw_priv(dev);
886 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
887 struct vmw_master *active = dev_priv->active_master;
888 struct vmw_master *vmaster = vmw_master(file_priv->master);
889 int ret = 0;
890
891 if (!dev_priv->enable_fb) {
892 ret = vmw_3d_resource_inc(dev_priv, true);
893 if (unlikely(ret != 0))
894 return ret;
895 vmw_kms_save_vga(dev_priv);
896 mutex_lock(&dev_priv->hw_mutex);
897 vmw_write(dev_priv, SVGA_REG_TRACES, 0);
898 mutex_unlock(&dev_priv->hw_mutex);
899 }
900
901 if (active) {
902 BUG_ON(active != &dev_priv->fbdev_master);
903 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
904 if (unlikely(ret != 0))
905 goto out_no_active_lock;
906
907 ttm_lock_set_kill(&active->lock, true, SIGTERM);
908 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
909 if (unlikely(ret != 0)) {
910 DRM_ERROR("Unable to clean VRAM on "
911 "master drop.\n");
912 }
913
914 dev_priv->active_master = NULL;
915 }
916
917 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
918 if (!from_open) {
919 ttm_vt_unlock(&vmaster->lock);
920 BUG_ON(vmw_fp->locked_master != file_priv->master);
921 drm_master_put(&vmw_fp->locked_master);
922 }
923
924 dev_priv->active_master = vmaster;
925
926 return 0;
927
928out_no_active_lock:
929 if (!dev_priv->enable_fb) {
930 mutex_lock(&dev_priv->hw_mutex);
931 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
932 mutex_unlock(&dev_priv->hw_mutex);
933 vmw_kms_restore_vga(dev_priv);
934 vmw_3d_resource_dec(dev_priv, true);
935 }
936 return ret;
937}
938
939static void vmw_master_drop(struct drm_device *dev,
940 struct drm_file *file_priv,
941 bool from_release)
942{
943 struct vmw_private *dev_priv = vmw_priv(dev);
944 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
945 struct vmw_master *vmaster = vmw_master(file_priv->master);
946 int ret;
947
948
949
950
951
952
953 vmw_fp->locked_master = drm_master_get(file_priv->master);
954 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
955 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
956
957 if (unlikely((ret != 0))) {
958 DRM_ERROR("Unable to lock TTM at VT switch.\n");
959 drm_master_put(&vmw_fp->locked_master);
960 }
961
962 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
963
964 if (!dev_priv->enable_fb) {
965 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
966 if (unlikely(ret != 0))
967 DRM_ERROR("Unable to clean VRAM on master drop.\n");
968 mutex_lock(&dev_priv->hw_mutex);
969 vmw_write(dev_priv, SVGA_REG_TRACES, 1);
970 mutex_unlock(&dev_priv->hw_mutex);
971 vmw_kms_restore_vga(dev_priv);
972 vmw_3d_resource_dec(dev_priv, true);
973 }
974
975 dev_priv->active_master = &dev_priv->fbdev_master;
976 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
977 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
978
979 if (dev_priv->enable_fb)
980 vmw_fb_on(dev_priv);
981}
982
983
984static void vmw_remove(struct pci_dev *pdev)
985{
986 struct drm_device *dev = pci_get_drvdata(pdev);
987
988 drm_put_dev(dev);
989}
990
991static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
992 void *ptr)
993{
994 struct vmw_private *dev_priv =
995 container_of(nb, struct vmw_private, pm_nb);
996 struct vmw_master *vmaster = dev_priv->active_master;
997
998 switch (val) {
999 case PM_HIBERNATION_PREPARE:
1000 case PM_SUSPEND_PREPARE:
1001 ttm_suspend_lock(&vmaster->lock);
1002
1003
1004
1005
1006
1007 vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
1008 ttm_bo_swapout_all(&dev_priv->bdev);
1009
1010 break;
1011 case PM_POST_HIBERNATION:
1012 case PM_POST_SUSPEND:
1013 case PM_POST_RESTORE:
1014 ttm_suspend_unlock(&vmaster->lock);
1015
1016 break;
1017 case PM_RESTORE_PREPARE:
1018 break;
1019 default:
1020 break;
1021 }
1022 return 0;
1023}
1024
1025
1026
1027
1028
1029static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1030{
1031 struct drm_device *dev = pci_get_drvdata(pdev);
1032 struct vmw_private *dev_priv = vmw_priv(dev);
1033
1034 if (dev_priv->num_3d_resources != 0) {
1035 DRM_INFO("Can't suspend or hibernate "
1036 "while 3D resources are active.\n");
1037 return -EBUSY;
1038 }
1039
1040 pci_save_state(pdev);
1041 pci_disable_device(pdev);
1042 pci_set_power_state(pdev, PCI_D3hot);
1043 return 0;
1044}
1045
1046static int vmw_pci_resume(struct pci_dev *pdev)
1047{
1048 pci_set_power_state(pdev, PCI_D0);
1049 pci_restore_state(pdev);
1050 return pci_enable_device(pdev);
1051}
1052
1053static int vmw_pm_suspend(struct device *kdev)
1054{
1055 struct pci_dev *pdev = to_pci_dev(kdev);
1056 struct pm_message dummy;
1057
1058 dummy.event = 0;
1059
1060 return vmw_pci_suspend(pdev, dummy);
1061}
1062
1063static int vmw_pm_resume(struct device *kdev)
1064{
1065 struct pci_dev *pdev = to_pci_dev(kdev);
1066
1067 return vmw_pci_resume(pdev);
1068}
1069
1070static int vmw_pm_prepare(struct device *kdev)
1071{
1072 struct pci_dev *pdev = to_pci_dev(kdev);
1073 struct drm_device *dev = pci_get_drvdata(pdev);
1074 struct vmw_private *dev_priv = vmw_priv(dev);
1075
1076
1077
1078
1079
1080 dev_priv->suspended = true;
1081 if (dev_priv->enable_fb)
1082 vmw_3d_resource_dec(dev_priv, true);
1083
1084 if (dev_priv->num_3d_resources != 0) {
1085
1086 DRM_INFO("Can't suspend or hibernate "
1087 "while 3D resources are active.\n");
1088
1089 if (dev_priv->enable_fb)
1090 vmw_3d_resource_inc(dev_priv, true);
1091 dev_priv->suspended = false;
1092 return -EBUSY;
1093 }
1094
1095 return 0;
1096}
1097
1098static void vmw_pm_complete(struct device *kdev)
1099{
1100 struct pci_dev *pdev = to_pci_dev(kdev);
1101 struct drm_device *dev = pci_get_drvdata(pdev);
1102 struct vmw_private *dev_priv = vmw_priv(dev);
1103
1104
1105
1106
1107
1108 if (dev_priv->enable_fb)
1109 vmw_3d_resource_inc(dev_priv, false);
1110
1111 dev_priv->suspended = false;
1112}
1113
1114static const struct dev_pm_ops vmw_pm_ops = {
1115 .prepare = vmw_pm_prepare,
1116 .complete = vmw_pm_complete,
1117 .suspend = vmw_pm_suspend,
1118 .resume = vmw_pm_resume,
1119};
1120
1121static const struct file_operations vmwgfx_driver_fops = {
1122 .owner = THIS_MODULE,
1123 .open = drm_open,
1124 .release = drm_release,
1125 .unlocked_ioctl = vmw_unlocked_ioctl,
1126 .mmap = vmw_mmap,
1127 .poll = vmw_fops_poll,
1128 .read = vmw_fops_read,
1129 .fasync = drm_fasync,
1130#if defined(CONFIG_COMPAT)
1131 .compat_ioctl = drm_compat_ioctl,
1132#endif
1133 .llseek = noop_llseek,
1134};
1135
1136static struct drm_driver driver = {
1137 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
1138 DRIVER_MODESET,
1139 .load = vmw_driver_load,
1140 .unload = vmw_driver_unload,
1141 .firstopen = vmw_firstopen,
1142 .lastclose = vmw_lastclose,
1143 .irq_preinstall = vmw_irq_preinstall,
1144 .irq_postinstall = vmw_irq_postinstall,
1145 .irq_uninstall = vmw_irq_uninstall,
1146 .irq_handler = vmw_irq_handler,
1147 .get_vblank_counter = vmw_get_vblank_counter,
1148 .enable_vblank = vmw_enable_vblank,
1149 .disable_vblank = vmw_disable_vblank,
1150 .reclaim_buffers_locked = NULL,
1151 .ioctls = vmw_ioctls,
1152 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
1153 .dma_quiescent = NULL,
1154 .master_create = vmw_master_create,
1155 .master_destroy = vmw_master_destroy,
1156 .master_set = vmw_master_set,
1157 .master_drop = vmw_master_drop,
1158 .open = vmw_driver_open,
1159 .preclose = vmw_preclose,
1160 .postclose = vmw_postclose,
1161 .fops = &vmwgfx_driver_fops,
1162 .name = VMWGFX_DRIVER_NAME,
1163 .desc = VMWGFX_DRIVER_DESC,
1164 .date = VMWGFX_DRIVER_DATE,
1165 .major = VMWGFX_DRIVER_MAJOR,
1166 .minor = VMWGFX_DRIVER_MINOR,
1167 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1168};
1169
1170static struct pci_driver vmw_pci_driver = {
1171 .name = VMWGFX_DRIVER_NAME,
1172 .id_table = vmw_pci_id_list,
1173 .probe = vmw_probe,
1174 .remove = vmw_remove,
1175 .driver = {
1176 .pm = &vmw_pm_ops
1177 }
1178};
1179
1180static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1181{
1182 return drm_get_pci_dev(pdev, ent, &driver);
1183}
1184
1185static int __init vmwgfx_init(void)
1186{
1187 int ret;
1188 ret = drm_pci_init(&driver, &vmw_pci_driver);
1189 if (ret)
1190 DRM_ERROR("Failed initializing DRM.\n");
1191 return ret;
1192}
1193
1194static void __exit vmwgfx_exit(void)
1195{
1196 drm_pci_exit(&driver, &vmw_pci_driver);
1197}
1198
1199module_init(vmwgfx_init);
1200module_exit(vmwgfx_exit);
1201
1202MODULE_AUTHOR("VMware Inc. and others");
1203MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1204MODULE_LICENSE("GPL and additional rights");
1205MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1206 __stringify(VMWGFX_DRIVER_MINOR) "."
1207 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1208 "0");
1209
