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9#ifndef BNX2X_HSI_H
10#define BNX2X_HSI_H
11
12#include "bnx2x_fw_defs.h"
13
14#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
15
16struct license_key {
17 u32 reserved[6];
18
19 u32 max_iscsi_conn;
20#define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
21#define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
22#define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
23#define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
24
25 u32 reserved_a;
26
27 u32 max_fcoe_conn;
28#define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
29#define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
30#define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
31#define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
32
33 u32 reserved_b[4];
34};
35
36
37#define PORT_0 0
38#define PORT_1 1
39#define PORT_MAX 2
40#define NVM_PATH_MAX 2
41
42
43
44
45#define PIN_CFG_NA 0x00000000
46#define PIN_CFG_GPIO0_P0 0x00000001
47#define PIN_CFG_GPIO1_P0 0x00000002
48#define PIN_CFG_GPIO2_P0 0x00000003
49#define PIN_CFG_GPIO3_P0 0x00000004
50#define PIN_CFG_GPIO0_P1 0x00000005
51#define PIN_CFG_GPIO1_P1 0x00000006
52#define PIN_CFG_GPIO2_P1 0x00000007
53#define PIN_CFG_GPIO3_P1 0x00000008
54#define PIN_CFG_EPIO0 0x00000009
55#define PIN_CFG_EPIO1 0x0000000a
56#define PIN_CFG_EPIO2 0x0000000b
57#define PIN_CFG_EPIO3 0x0000000c
58#define PIN_CFG_EPIO4 0x0000000d
59#define PIN_CFG_EPIO5 0x0000000e
60#define PIN_CFG_EPIO6 0x0000000f
61#define PIN_CFG_EPIO7 0x00000010
62#define PIN_CFG_EPIO8 0x00000011
63#define PIN_CFG_EPIO9 0x00000012
64#define PIN_CFG_EPIO10 0x00000013
65#define PIN_CFG_EPIO11 0x00000014
66#define PIN_CFG_EPIO12 0x00000015
67#define PIN_CFG_EPIO13 0x00000016
68#define PIN_CFG_EPIO14 0x00000017
69#define PIN_CFG_EPIO15 0x00000018
70#define PIN_CFG_EPIO16 0x00000019
71#define PIN_CFG_EPIO17 0x0000001a
72#define PIN_CFG_EPIO18 0x0000001b
73#define PIN_CFG_EPIO19 0x0000001c
74#define PIN_CFG_EPIO20 0x0000001d
75#define PIN_CFG_EPIO21 0x0000001e
76#define PIN_CFG_EPIO22 0x0000001f
77#define PIN_CFG_EPIO23 0x00000020
78#define PIN_CFG_EPIO24 0x00000021
79#define PIN_CFG_EPIO25 0x00000022
80#define PIN_CFG_EPIO26 0x00000023
81#define PIN_CFG_EPIO27 0x00000024
82#define PIN_CFG_EPIO28 0x00000025
83#define PIN_CFG_EPIO29 0x00000026
84#define PIN_CFG_EPIO30 0x00000027
85#define PIN_CFG_EPIO31 0x00000028
86
87
88#define EPIO_CFG_NA 0x00000000
89#define EPIO_CFG_EPIO0 0x00000001
90#define EPIO_CFG_EPIO1 0x00000002
91#define EPIO_CFG_EPIO2 0x00000003
92#define EPIO_CFG_EPIO3 0x00000004
93#define EPIO_CFG_EPIO4 0x00000005
94#define EPIO_CFG_EPIO5 0x00000006
95#define EPIO_CFG_EPIO6 0x00000007
96#define EPIO_CFG_EPIO7 0x00000008
97#define EPIO_CFG_EPIO8 0x00000009
98#define EPIO_CFG_EPIO9 0x0000000a
99#define EPIO_CFG_EPIO10 0x0000000b
100#define EPIO_CFG_EPIO11 0x0000000c
101#define EPIO_CFG_EPIO12 0x0000000d
102#define EPIO_CFG_EPIO13 0x0000000e
103#define EPIO_CFG_EPIO14 0x0000000f
104#define EPIO_CFG_EPIO15 0x00000010
105#define EPIO_CFG_EPIO16 0x00000011
106#define EPIO_CFG_EPIO17 0x00000012
107#define EPIO_CFG_EPIO18 0x00000013
108#define EPIO_CFG_EPIO19 0x00000014
109#define EPIO_CFG_EPIO20 0x00000015
110#define EPIO_CFG_EPIO21 0x00000016
111#define EPIO_CFG_EPIO22 0x00000017
112#define EPIO_CFG_EPIO23 0x00000018
113#define EPIO_CFG_EPIO24 0x00000019
114#define EPIO_CFG_EPIO25 0x0000001a
115#define EPIO_CFG_EPIO26 0x0000001b
116#define EPIO_CFG_EPIO27 0x0000001c
117#define EPIO_CFG_EPIO28 0x0000001d
118#define EPIO_CFG_EPIO29 0x0000001e
119#define EPIO_CFG_EPIO30 0x0000001f
120#define EPIO_CFG_EPIO31 0x00000020
121
122
123struct shared_hw_cfg {
124
125 u8 part_num[16];
126
127 u32 config;
128 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
131 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
132 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
133
134 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
135
136 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
137
138 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
139 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
140
141 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
142 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
143
144
145 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
146 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
147 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
148 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
149
150
151 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
152
153
154 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
155
156
157 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
158
159 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
160 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
161 #define SHARED_HW_CFG_LED_MAC1 0x00000000
162 #define SHARED_HW_CFG_LED_PHY1 0x00010000
163 #define SHARED_HW_CFG_LED_PHY2 0x00020000
164 #define SHARED_HW_CFG_LED_PHY3 0x00030000
165 #define SHARED_HW_CFG_LED_MAC2 0x00040000
166 #define SHARED_HW_CFG_LED_PHY4 0x00050000
167 #define SHARED_HW_CFG_LED_PHY5 0x00060000
168 #define SHARED_HW_CFG_LED_PHY6 0x00070000
169 #define SHARED_HW_CFG_LED_MAC3 0x00080000
170 #define SHARED_HW_CFG_LED_PHY7 0x00090000
171 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
172 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
173 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
174 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
175 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
176
177
178 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
179 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
180 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
181 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
182 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
183 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
184 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
185 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
186
187 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
188 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
189 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
190
191 #define SHARED_HW_CFG_ATC_MASK 0x80000000
192 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
193 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
194
195 u32 config2;
196
197 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
198 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
199
200 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
201 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
202
203
204
205 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
206 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
207
208 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
209 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
210 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
211
212 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
213
214 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
215 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
216 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
217
218
219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
222
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
229
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236
237 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
238 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
239 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
240 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
241 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
242
243
244 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
245 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
250
251
252
253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
256
257 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
258 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
259 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
260
261 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
262 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
263 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
264
265
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
273
274
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
282
283
284 u32 power_dissipated;
285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
286 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
287 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
288 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
289 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
290 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
291
292 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
293 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
294
295 u32 ump_nc_si_config;
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
302
303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
304 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
305
306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
309 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
310
311 u32 board;
312 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
313 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
314 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
315 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
316
317 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
318 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
319
320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
321 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
322
323 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
324 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
325
326 u32 wc_lane_config;
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
337
338
339 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
340 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
341 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
342 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
343
344 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
345 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
346 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
347 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
348
349
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
358};
359
360
361
362
363
364struct port_hw_cfg {
365
366 u32 pci_id;
367 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
368 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
369
370 u32 pci_sub_id;
371 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
372 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
373
374 u32 power_dissipated;
375 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
376 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
377 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
378 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
379 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
380 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
381 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
382 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
383
384 u32 power_consumed;
385 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
386 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
387 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
388 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
389 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
390 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
391 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
392 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
393
394 u32 mac_upper;
395 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
396 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
397 u32 mac_lower;
398
399 u32 iscsi_mac_upper;
400 u32 iscsi_mac_lower;
401
402 u32 rdma_mac_upper;
403 u32 rdma_mac_lower;
404
405 u32 serdes_config;
406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
407 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
408
409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
410 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
411
412
413
414 u32 pf_config;
415 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
416 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
417
418
419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
420 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
421
422 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
423 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
424
425 u32 vf_config;
426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
427 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
428
429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
430 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
431
432 u32 mf_pci_id;
433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
434 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
435
436
437 u32 sfp_ctrl;
438 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
439 #define PORT_HW_CFG_TX_LASER_SHIFT 0
440 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
441 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
442 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
443 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
444 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
445
446
447 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
448 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
452 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
453 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
454
455
456
457 u32 e3_sfp_ctrl;
458 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
459 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
460
461
462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
463 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
464
465
466
467 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
468 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
469
470
471
472 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
473 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
474
475
476
477
478
479 u32 e3_cmn_pin_cfg;
480 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
481 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
482
483
484
485 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
486 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
487
488
489
490
491
492 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
493 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
494
495
496
497 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
498 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
499
500
501
502
503
504
505 u32 e3_cmn_pin_cfg1;
506 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
507 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
508 u32 reserved0[7];
509
510 u32 aeu_int_mask;
511
512 u32 media_type;
513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
514 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
515
516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
517 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
518
519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
520 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
521
522
523
524
525
526
527 u16 xgxs_config_rx[4];
528 u16 xgxs_config_tx[4];
529
530
531 u32 fcoe_fip_mac_upper;
532 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
533 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
534 u32 fcoe_fip_mac_lower;
535
536 u32 fcoe_wwn_port_name_upper;
537 u32 fcoe_wwn_port_name_lower;
538
539 u32 fcoe_wwn_node_name_upper;
540 u32 fcoe_wwn_node_name_lower;
541
542 u32 Reserved1[49];
543
544
545
546 u32 xgbt_phy_cfg;
547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
548 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
549
550 u32 default_cfg;
551 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
552 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
553 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
554 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
555 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
556 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
557
558 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
559 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
560 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
561 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
562 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
563 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
564
565 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
566 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
567 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
568 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
569 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
570 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
571
572 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
573 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
574 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
575 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
576 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
577 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
578
579
580
581
582
583
584
585 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
586 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
587 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
595 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
596 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
597
598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
608 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
609
610
611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
614 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
615
616
617 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
618 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
619 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
620 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
621
622
623 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
624 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
625 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
626 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
627 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
628 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
629 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
630 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
631
632
633 u32 speed_capability_mask2;
634 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
635 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
636 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
644
645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
655
656
657
658
659
660
661 u32 multi_phy_config;
662 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
663 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
664 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
665 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
666 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
667 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
668 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
669
670
671
672 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
673 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
674 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
675 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
676
677
678
679 u32 external_phy_config2;
680 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
681 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
682
683
684 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
685 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
686 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
705
706
707
708
709 u16 xgxs_config2_rx[4];
710 u16 xgxs_config2_tx[4];
711
712 u32 lane_config;
713 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
714 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
715
716 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
717
718 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
719
720 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
721
722 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
723 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
724 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
725 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
726 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
727 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
728 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
729
730
731 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
732 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
733 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
734
735
736 u32 external_phy_config;
737 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
738 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
739
740 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
741 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
742 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
743 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
762
763 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
764 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
765
766 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
767 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
768 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
769 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
770 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
772
773 u32 speed_capability_mask;
774 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
775 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
776 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
777 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
778 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
785
786 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
787 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
788 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
789 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
790 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
797
798
799 u32 backup_mac_upper;
800 u32 backup_mac_lower;
801
802};
803
804
805
806
807
808struct shared_feat_cfg {
809
810 u32 config;
811 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
812
813
814 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
815 0x00000002
816 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
817 0x00000000
818 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
819 0x00000002
820
821 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
822 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
823 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
824
825 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
826 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
827
828
829
830 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
831 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
832 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
833 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
834 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
836
837
838
839 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
840 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
841
842
843 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
844 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
845
846};
847
848
849
850
851
852struct port_feat_cfg {
853
854 u32 config;
855 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
856 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
857 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
858 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
859 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
860 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
861 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
862 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
863 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
864 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
865 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
866 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
867 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
868 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
869 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
870 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
871 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
872 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
873 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
874 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
875 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
876 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
877 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
878 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
879 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
880 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
881 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
882 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
883 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
884 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
885 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
886 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
887 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
888 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
889 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
890 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
891
892 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
893 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
894 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
895
896 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
897 #define PORT_FEATURE_EN_SIZE_SHIFT 24
898 #define PORT_FEATURE_WOL_ENABLED 0x01000000
899 #define PORT_FEATURE_MBA_ENABLED 0x02000000
900 #define PORT_FEATURE_MFW_ENABLED 0x04000000
901
902
903 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
904 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
905 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
906
907
908
909 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
910 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
911 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
912 0x00000000
913 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
914 0x20000000
915 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
916 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
917
918 u32 wol_config;
919
920 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
921 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
922 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
923 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
924 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
925 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
926 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
927 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
928 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
929
930 u32 mba_config;
931 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
932 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
933 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
934 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
935 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
936 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
937 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
938 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
939
940 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
941 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
942
943 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
944 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
945 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
946 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
947 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
948 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
949 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
950 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
951 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
952 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
953 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
954 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
955 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
956 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
957 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
958 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
967 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
968 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
969 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
970 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
971 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
972 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
973 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
974 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
975 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
976 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
977 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
978 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
979 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
980 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
981 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
982 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
983 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
984 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
985 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
986 u32 bmc_config;
987 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
988 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
989 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
990
991 u32 mba_vlan_cfg;
992 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
993 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
994 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
995
996 u32 resource_cfg;
997 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
998 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
999 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1000 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1001 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1002
1003 u32 smbus_config;
1004 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1005 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1006
1007 u32 vf_config;
1008 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1009 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1010 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1011 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1012 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1013 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1014 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1015 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1016 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1017 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1026
1027 u32 link_config;
1028 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1029 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1030
1031 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1032
1033 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1034 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1035 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1036
1037 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1038 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1039 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1040 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1041 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1042 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1043 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1044 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1045 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1046 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1047 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1048
1049 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1050 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1051 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1052 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1053 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1054 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1055 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1056
1057
1058
1059 u32 mfw_wol_link_cfg;
1060
1061
1062
1063 u32 link_config2;
1064
1065
1066
1067 u32 mfw_wol_link_cfg2;
1068
1069 u32 Reserved2[17];
1070
1071};
1072
1073
1074
1075
1076
1077struct shm_dev_info {
1078
1079 u32 bc_rev;
1080
1081 struct shared_hw_cfg shared_hw_config;
1082
1083 struct port_hw_cfg port_hw_config[PORT_MAX];
1084
1085 struct shared_feat_cfg shared_feature_config;
1086
1087 struct port_feat_cfg port_feature_config[PORT_MAX];
1088
1089};
1090
1091
1092#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1093 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1094#endif
1095
1096#define FUNC_0 0
1097#define FUNC_1 1
1098#define FUNC_2 2
1099#define FUNC_3 3
1100#define FUNC_4 4
1101#define FUNC_5 5
1102#define FUNC_6 6
1103#define FUNC_7 7
1104#define E1_FUNC_MAX 2
1105#define E1H_FUNC_MAX 8
1106#define E2_FUNC_MAX 4
1107
1108#define VN_0 0
1109#define VN_1 1
1110#define VN_2 2
1111#define VN_3 3
1112#define E1VN_MAX 1
1113#define E1HVN_MAX 4
1114
1115#define E2_VF_MAX 64
1116
1117
1118
1119#define DRV_PULSE_PERIOD_MS 250
1120
1121
1122
1123
1124
1125
1126#define FW_ACK_TIME_OUT_MS 5000
1127
1128#define FW_ACK_POLL_TIME_MS 1
1129
1130#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1131
1132#define MFW_TRACE_SIGNATURE 0x54524342
1133
1134
1135
1136
1137struct drv_port_mb {
1138
1139 u32 link_status;
1140
1141
1142 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1143 #define LINK_STATUS_LINK_UP 0x00000001
1144 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1145 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1146 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1147 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1148 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1149 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1150 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1151 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1152 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1153 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1154 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1155 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1156 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1157 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1158 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1159 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1160 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1161
1162 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1163 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1164
1165 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1166 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1167 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1168
1169 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1170 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1171 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1172 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1173 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1174 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1175 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1176
1177 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1178 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1179
1180 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1181 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1182
1183 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1184 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1185 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1186 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1187 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1188
1189 #define LINK_STATUS_SERDES_LINK 0x00100000
1190
1191 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1192 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1193 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1194 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1195
1196 #define LINK_STATUS_PFC_ENABLED 0x20000000
1197
1198 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1199
1200 u32 port_stx;
1201
1202 u32 stat_nig_timer;
1203
1204
1205 u32 ext_phy_fw_version;
1206
1207};
1208
1209
1210struct drv_func_mb {
1211
1212 u32 drv_mb_header;
1213 #define DRV_MSG_CODE_MASK 0xffff0000
1214 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1215 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1216 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1217 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1218 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1219 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1220 #define DRV_MSG_CODE_DCC_OK 0x30000000
1221 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1222 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1223 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1224 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1225 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1226 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1227 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1228 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1229
1230
1231
1232
1233
1234 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1235 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1236 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1237 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1238 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1239 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1240
1241 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1242 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1243
1244 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1245 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1246 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1247
1248 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1249 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1250 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1251
1252 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1253
1254 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1255 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1256
1257 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1258 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1259 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1260 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1261
1262 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1263
1264 u32 drv_mb_param;
1265 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1266 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1267
1268 u32 fw_mb_header;
1269 #define FW_MSG_CODE_MASK 0xffff0000
1270 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1271 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1272 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1273
1274 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1275 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1276
1277 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1278 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1279 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1280 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1281 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1282 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1283 #define FW_MSG_CODE_DCC_DONE 0x30100000
1284 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1285 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1286 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1287 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1288 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1289 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1290 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1291 #define FW_MSG_CODE_NO_KEY 0x80f00000
1292 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1293 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1294 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1295 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1296 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1297 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1298 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1299 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1300 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1301 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1302 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1303 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1304
1305 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1306 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1307
1308 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1309
1310 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1311 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1312 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1313 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1314
1315 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1316
1317 u32 fw_mb_param;
1318
1319 u32 drv_pulse_mb;
1320 #define DRV_PULSE_SEQ_MASK 0x00007fff
1321 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1322
1323
1324
1325
1326 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1327
1328
1329
1330
1331
1332
1333 u32 mcp_pulse_mb;
1334 #define MCP_PULSE_SEQ_MASK 0x00007fff
1335 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1336
1337
1338 #define MCP_EVENT_MASK 0xffff0000
1339 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1340
1341 u32 iscsi_boot_signature;
1342 u32 iscsi_boot_block_offset;
1343
1344 u32 drv_status;
1345 #define DRV_STATUS_PMF 0x00000001
1346 #define DRV_STATUS_VF_DISABLED 0x00000002
1347 #define DRV_STATUS_SET_MF_BW 0x00000004
1348 #define DRV_STATUS_LINK_EVENT 0x00000008
1349
1350 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1351 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1352 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1353 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1354 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1355 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1356 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1357
1358 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1359 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1360 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1361
1362 u32 virt_mac_upper;
1363 #define VIRT_MAC_SIGN_MASK 0xffff0000
1364 #define VIRT_MAC_SIGNATURE 0x564d0000
1365 u32 virt_mac_lower;
1366
1367};
1368
1369
1370
1371
1372
1373
1374#define MGMTFW_STATE_WORD_SIZE 110
1375
1376struct mgmtfw_state {
1377 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1378};
1379
1380
1381
1382
1383
1384struct shared_mf_cfg {
1385
1386 u32 clp_mb;
1387 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1388
1389 #define SHARED_MF_CLP_EXIT 0x00000001
1390
1391 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1392
1393};
1394
1395struct port_mf_cfg {
1396
1397 u32 dynamic_cfg;
1398 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1399 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1400 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1401
1402 u32 reserved[1];
1403
1404};
1405
1406struct func_mf_cfg {
1407
1408 u32 config;
1409
1410
1411 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1412
1413 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1414 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1415 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1416 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1417 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1418 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1419 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1420
1421 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1422 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1423
1424
1425
1426 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1427 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1428 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1429
1430
1431
1432 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1433 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1434 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1435 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1436 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1437 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1438
1439 u32 mac_upper;
1440 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1441 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1442 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1443 u32 mac_lower;
1444 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1445
1446 u32 e1hov_tag;
1447 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1448 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1449 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1450
1451 u32 reserved[2];
1452};
1453
1454
1455struct func_ext_cfg {
1456 u32 func_cfg;
1457 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1458 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1459 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1460 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1461 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1462 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1463
1464 u32 iscsi_mac_addr_upper;
1465 u32 iscsi_mac_addr_lower;
1466
1467 u32 fcoe_mac_addr_upper;
1468 u32 fcoe_mac_addr_lower;
1469
1470 u32 fcoe_wwn_port_name_upper;
1471 u32 fcoe_wwn_port_name_lower;
1472
1473 u32 fcoe_wwn_node_name_upper;
1474 u32 fcoe_wwn_node_name_lower;
1475
1476 u32 preserve_data;
1477 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1478 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1479 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1480 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1481 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1482 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1483};
1484
1485struct mf_cfg {
1486
1487 struct shared_mf_cfg shared_mf_config;
1488
1489 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1490
1491 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
1492
1493
1494
1495
1496 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
1497};
1498
1499
1500
1501
1502struct shmem_region {
1503
1504 u32 validity_map[PORT_MAX];
1505 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1506 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1507
1508 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1509 #define SHR_MEM_VALIDITY_MB 0x00200000
1510 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1511 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1512
1513 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1514 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1515 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1516 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1517
1518 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1519 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1520 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1521 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1522 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1523 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1524
1525 struct shm_dev_info dev_info;
1526
1527 struct license_key drv_lic_key[PORT_MAX];
1528
1529
1530 u32 fw_info_fio_offset;
1531 struct mgmtfw_state mgmtfw_state;
1532
1533 struct drv_port_mb port_mb[PORT_MAX];
1534
1535#ifdef BMAPI
1536
1537
1538 struct drv_func_mb func_mb[1];
1539#else
1540
1541 struct drv_func_mb func_mb[];
1542#endif
1543
1544};
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561struct fw_flr_ack {
1562 u32 pf_ack;
1563 u32 vf_ack[1];
1564 u32 iov_dis_ack;
1565};
1566
1567struct fw_flr_mb {
1568 u32 aggint;
1569 u32 opgen_addr;
1570 struct fw_flr_ack ack;
1571};
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1584#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1611 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1612 (((i)%((fb)/(eb))) * (eb)))
1613
1614#define SHMEM_ARRAY_GET(a, i, eb, fb) \
1615 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1616 SHMEM_ARRAY_MASK(eb))
1617
1618#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1619do { \
1620 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1621 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1622 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1623 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1624} while (0)
1625
1626
1627
1628#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1629#define DCBX_PRI_PG_BITWIDTH 4
1630#define DCBX_PRI_PG_FBITS 8
1631#define DCBX_PRI_PG_GET(a, i) \
1632 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1633#define DCBX_PRI_PG_SET(a, i, val) \
1634 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1635#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1636#define DCBX_BW_PG_BITWIDTH 8
1637#define DCBX_PG_BW_GET(a, i) \
1638 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1639#define DCBX_PG_BW_SET(a, i, val) \
1640 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1641#define DCBX_STRICT_PRI_PG 15
1642#define DCBX_MAX_APP_PROTOCOL 16
1643#define FCOE_APP_IDX 0
1644#define ISCSI_APP_IDX 1
1645#define PREDEFINED_APP_IDX_MAX 2
1646
1647
1648
1649struct dcbx_ets_feature {
1650
1651
1652
1653
1654 u32 enabled;
1655 u32 pg_bw_tbl[2];
1656 u32 pri_pg_tbl[1];
1657};
1658
1659
1660struct dcbx_pfc_feature {
1661#ifdef __BIG_ENDIAN
1662 u8 pri_en_bitmap;
1663 #define DCBX_PFC_PRI_0 0x01
1664 #define DCBX_PFC_PRI_1 0x02
1665 #define DCBX_PFC_PRI_2 0x04
1666 #define DCBX_PFC_PRI_3 0x08
1667 #define DCBX_PFC_PRI_4 0x10
1668 #define DCBX_PFC_PRI_5 0x20
1669 #define DCBX_PFC_PRI_6 0x40
1670 #define DCBX_PFC_PRI_7 0x80
1671 u8 pfc_caps;
1672 u8 reserved;
1673 u8 enabled;
1674#elif defined(__LITTLE_ENDIAN)
1675 u8 enabled;
1676 u8 reserved;
1677 u8 pfc_caps;
1678 u8 pri_en_bitmap;
1679 #define DCBX_PFC_PRI_0 0x01
1680 #define DCBX_PFC_PRI_1 0x02
1681 #define DCBX_PFC_PRI_2 0x04
1682 #define DCBX_PFC_PRI_3 0x08
1683 #define DCBX_PFC_PRI_4 0x10
1684 #define DCBX_PFC_PRI_5 0x20
1685 #define DCBX_PFC_PRI_6 0x40
1686 #define DCBX_PFC_PRI_7 0x80
1687#endif
1688};
1689
1690struct dcbx_app_priority_entry {
1691#ifdef __BIG_ENDIAN
1692 u16 app_id;
1693 u8 pri_bitmap;
1694 u8 appBitfield;
1695 #define DCBX_APP_ENTRY_VALID 0x01
1696 #define DCBX_APP_ENTRY_SF_MASK 0x30
1697 #define DCBX_APP_ENTRY_SF_SHIFT 4
1698 #define DCBX_APP_SF_ETH_TYPE 0x10
1699 #define DCBX_APP_SF_PORT 0x20
1700#elif defined(__LITTLE_ENDIAN)
1701 u8 appBitfield;
1702 #define DCBX_APP_ENTRY_VALID 0x01
1703 #define DCBX_APP_ENTRY_SF_MASK 0x30
1704 #define DCBX_APP_ENTRY_SF_SHIFT 4
1705 #define DCBX_APP_SF_ETH_TYPE 0x10
1706 #define DCBX_APP_SF_PORT 0x20
1707 u8 pri_bitmap;
1708 u16 app_id;
1709#endif
1710};
1711
1712
1713
1714struct dcbx_app_priority_feature {
1715#ifdef __BIG_ENDIAN
1716 u8 reserved;
1717 u8 default_pri;
1718 u8 tc_supported;
1719 u8 enabled;
1720#elif defined(__LITTLE_ENDIAN)
1721 u8 enabled;
1722 u8 tc_supported;
1723 u8 default_pri;
1724 u8 reserved;
1725#endif
1726 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1727};
1728
1729
1730struct dcbx_features {
1731
1732 struct dcbx_ets_feature ets;
1733
1734 struct dcbx_pfc_feature pfc;
1735
1736 struct dcbx_app_priority_feature app;
1737};
1738
1739
1740
1741struct lldp_params {
1742#ifdef __BIG_ENDIAN
1743 u8 msg_fast_tx_interval;
1744 u8 msg_tx_hold;
1745 u8 msg_tx_interval;
1746 u8 admin_status;
1747 #define LLDP_TX_ONLY 0x01
1748 #define LLDP_RX_ONLY 0x02
1749 #define LLDP_TX_RX 0x03
1750 #define LLDP_DISABLED 0x04
1751 u8 reserved1;
1752 u8 tx_fast;
1753 u8 tx_crd_max;
1754 u8 tx_crd;
1755#elif defined(__LITTLE_ENDIAN)
1756 u8 admin_status;
1757 #define LLDP_TX_ONLY 0x01
1758 #define LLDP_RX_ONLY 0x02
1759 #define LLDP_TX_RX 0x03
1760 #define LLDP_DISABLED 0x04
1761 u8 msg_tx_interval;
1762 u8 msg_tx_hold;
1763 u8 msg_fast_tx_interval;
1764 u8 tx_crd;
1765 u8 tx_crd_max;
1766 u8 tx_fast;
1767 u8 reserved1;
1768#endif
1769 #define REM_CHASSIS_ID_STAT_LEN 4
1770 #define REM_PORT_ID_STAT_LEN 4
1771
1772 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1773
1774 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1775};
1776
1777struct lldp_dcbx_stat {
1778 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1779 #define LOCAL_PORT_ID_STAT_LEN 2
1780
1781 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1782
1783 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1784
1785 u32 num_tx_dcbx_pkts;
1786
1787 u32 num_rx_dcbx_pkts;
1788};
1789
1790
1791struct lldp_admin_mib {
1792 u32 ver_cfg_flags;
1793 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1794 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1795 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1796 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1797 #define DCBX_ETS_RECO_VALID 0x00000010
1798 #define DCBX_ETS_WILLING 0x00000020
1799 #define DCBX_PFC_WILLING 0x00000040
1800 #define DCBX_APP_WILLING 0x00000080
1801 #define DCBX_VERSION_CEE 0x00000100
1802 #define DCBX_VERSION_IEEE 0x00000200
1803 #define DCBX_DCBX_ENABLED 0x00000400
1804 #define DCBX_CEE_VERSION_MASK 0x0000f000
1805 #define DCBX_CEE_VERSION_SHIFT 12
1806 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1807 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1808 struct dcbx_features features;
1809};
1810
1811
1812struct lldp_remote_mib {
1813 u32 prefix_seq_num;
1814 u32 flags;
1815 #define DCBX_ETS_TLV_RX 0x00000001
1816 #define DCBX_PFC_TLV_RX 0x00000002
1817 #define DCBX_APP_TLV_RX 0x00000004
1818 #define DCBX_ETS_RX_ERROR 0x00000010
1819 #define DCBX_PFC_RX_ERROR 0x00000020
1820 #define DCBX_APP_RX_ERROR 0x00000040
1821 #define DCBX_ETS_REM_WILLING 0x00000100
1822 #define DCBX_PFC_REM_WILLING 0x00000200
1823 #define DCBX_APP_REM_WILLING 0x00000400
1824 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1825 #define DCBX_REMOTE_MIB_VALID 0x00002000
1826 struct dcbx_features features;
1827 u32 suffix_seq_num;
1828};
1829
1830
1831struct lldp_local_mib {
1832 u32 prefix_seq_num;
1833
1834 u32 error;
1835 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1836 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1837 #define DCBX_LOCAL_APP_ERROR 0x00000004
1838 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1839 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1840 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1841 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1842 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1843 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1844 struct dcbx_features features;
1845 u32 suffix_seq_num;
1846};
1847
1848
1849struct ncsi_oem_fcoe_features {
1850 u32 fcoe_features1;
1851 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1852 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1853
1854 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1855 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1856
1857 u32 fcoe_features2;
1858 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1859 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1860
1861 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1862 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1863
1864 u32 fcoe_features3;
1865 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1866 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1867
1868 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1869 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
1870
1871 u32 fcoe_features4;
1872 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
1873 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
1874};
1875
1876struct ncsi_oem_data {
1877 u32 driver_version[4];
1878 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
1879};
1880
1881struct shmem2_region {
1882
1883 u32 size;
1884
1885 u32 dcc_support;
1886 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1887 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1888 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1889 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1890 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1891 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1892
1893 u32 ext_phy_fw_version2[PORT_MAX];
1894
1895
1896
1897
1898
1899 u32 mf_cfg_addr;
1900 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1901
1902 struct fw_flr_mb flr_mb;
1903 u32 dcbx_lldp_params_offset;
1904 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1905 u32 dcbx_neg_res_offset;
1906 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1907 u32 dcbx_remote_mib_offset;
1908 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1909
1910
1911
1912
1913
1914
1915 u32 other_shmem_base_addr;
1916 u32 other_shmem2_base_addr;
1917
1918
1919
1920
1921 u32 mcp_vf_disabled[E2_VF_MAX / 32];
1922
1923
1924
1925
1926
1927 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32];
1928
1929 u32 dcbx_lldp_dcbx_stat_offset;
1930 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941 u32 edebug_driver_if[2];
1942 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
1943 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
1944 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
1945
1946 u32 nvm_retain_bitmap_addr;
1947
1948 u32 reserved1;
1949
1950 u32 reserved2[E2_FUNC_MAX];
1951
1952 u32 reserved3[E2_FUNC_MAX];
1953 u32 reserved4[E2_FUNC_MAX];
1954
1955 u32 swim_base_addr;
1956 u32 swim_funcs;
1957 u32 swim_main_cb;
1958
1959 u32 reserved5[2];
1960
1961
1962 u32 drv_flags;
1963 #define DRV_FLAGS_DCB_CONFIGURED 0x1
1964
1965
1966 u32 extended_dev_info_shared_addr;
1967 u32 ncsi_oem_data_addr;
1968
1969 u32 ocsd_host_addr;
1970 u32 ocbb_host_addr;
1971 u32 ocsd_req_update_interval;
1972 u32 temperature_in_half_celsius;
1973 u32 glob_struct_in_host;
1974
1975 u32 dcbx_neg_res_ext_offset;
1976#define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
1977
1978 u32 drv_capabilities_flag[E2_FUNC_MAX];
1979#define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
1980#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
1981#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
1982#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
1983
1984 u32 extended_dev_info_shared_cfg_size;
1985
1986 u32 dcbx_en[PORT_MAX];
1987
1988
1989 u32 multi_thread_data_offset;
1990
1991
1992 u32 drv_info_host_addr_lo;
1993 u32 drv_info_host_addr_hi;
1994
1995
1996 u32 drv_info_control;
1997#define DRV_INFO_CONTROL_VER_MASK 0x000000ff
1998#define DRV_INFO_CONTROL_VER_SHIFT 0
1999#define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2000#define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2001 u32 ibft_host_addr;
2002};
2003
2004
2005struct emac_stats {
2006 u32 rx_stat_ifhcinoctets;
2007 u32 rx_stat_ifhcinbadoctets;
2008 u32 rx_stat_etherstatsfragments;
2009 u32 rx_stat_ifhcinucastpkts;
2010 u32 rx_stat_ifhcinmulticastpkts;
2011 u32 rx_stat_ifhcinbroadcastpkts;
2012 u32 rx_stat_dot3statsfcserrors;
2013 u32 rx_stat_dot3statsalignmenterrors;
2014 u32 rx_stat_dot3statscarriersenseerrors;
2015 u32 rx_stat_xonpauseframesreceived;
2016 u32 rx_stat_xoffpauseframesreceived;
2017 u32 rx_stat_maccontrolframesreceived;
2018 u32 rx_stat_xoffstateentered;
2019 u32 rx_stat_dot3statsframestoolong;
2020 u32 rx_stat_etherstatsjabbers;
2021 u32 rx_stat_etherstatsundersizepkts;
2022 u32 rx_stat_etherstatspkts64octets;
2023 u32 rx_stat_etherstatspkts65octetsto127octets;
2024 u32 rx_stat_etherstatspkts128octetsto255octets;
2025 u32 rx_stat_etherstatspkts256octetsto511octets;
2026 u32 rx_stat_etherstatspkts512octetsto1023octets;
2027 u32 rx_stat_etherstatspkts1024octetsto1522octets;
2028 u32 rx_stat_etherstatspktsover1522octets;
2029
2030 u32 rx_stat_falsecarriererrors;
2031
2032 u32 tx_stat_ifhcoutoctets;
2033 u32 tx_stat_ifhcoutbadoctets;
2034 u32 tx_stat_etherstatscollisions;
2035 u32 tx_stat_outxonsent;
2036 u32 tx_stat_outxoffsent;
2037 u32 tx_stat_flowcontroldone;
2038 u32 tx_stat_dot3statssinglecollisionframes;
2039 u32 tx_stat_dot3statsmultiplecollisionframes;
2040 u32 tx_stat_dot3statsdeferredtransmissions;
2041 u32 tx_stat_dot3statsexcessivecollisions;
2042 u32 tx_stat_dot3statslatecollisions;
2043 u32 tx_stat_ifhcoutucastpkts;
2044 u32 tx_stat_ifhcoutmulticastpkts;
2045 u32 tx_stat_ifhcoutbroadcastpkts;
2046 u32 tx_stat_etherstatspkts64octets;
2047 u32 tx_stat_etherstatspkts65octetsto127octets;
2048 u32 tx_stat_etherstatspkts128octetsto255octets;
2049 u32 tx_stat_etherstatspkts256octetsto511octets;
2050 u32 tx_stat_etherstatspkts512octetsto1023octets;
2051 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2052 u32 tx_stat_etherstatspktsover1522octets;
2053 u32 tx_stat_dot3statsinternalmactransmiterrors;
2054};
2055
2056
2057struct bmac1_stats {
2058 u32 tx_stat_gtpkt_lo;
2059 u32 tx_stat_gtpkt_hi;
2060 u32 tx_stat_gtxpf_lo;
2061 u32 tx_stat_gtxpf_hi;
2062 u32 tx_stat_gtfcs_lo;
2063 u32 tx_stat_gtfcs_hi;
2064 u32 tx_stat_gtmca_lo;
2065 u32 tx_stat_gtmca_hi;
2066 u32 tx_stat_gtbca_lo;
2067 u32 tx_stat_gtbca_hi;
2068 u32 tx_stat_gtfrg_lo;
2069 u32 tx_stat_gtfrg_hi;
2070 u32 tx_stat_gtovr_lo;
2071 u32 tx_stat_gtovr_hi;
2072 u32 tx_stat_gt64_lo;
2073 u32 tx_stat_gt64_hi;
2074 u32 tx_stat_gt127_lo;
2075 u32 tx_stat_gt127_hi;
2076 u32 tx_stat_gt255_lo;
2077 u32 tx_stat_gt255_hi;
2078 u32 tx_stat_gt511_lo;
2079 u32 tx_stat_gt511_hi;
2080 u32 tx_stat_gt1023_lo;
2081 u32 tx_stat_gt1023_hi;
2082 u32 tx_stat_gt1518_lo;
2083 u32 tx_stat_gt1518_hi;
2084 u32 tx_stat_gt2047_lo;
2085 u32 tx_stat_gt2047_hi;
2086 u32 tx_stat_gt4095_lo;
2087 u32 tx_stat_gt4095_hi;
2088 u32 tx_stat_gt9216_lo;
2089 u32 tx_stat_gt9216_hi;
2090 u32 tx_stat_gt16383_lo;
2091 u32 tx_stat_gt16383_hi;
2092 u32 tx_stat_gtmax_lo;
2093 u32 tx_stat_gtmax_hi;
2094 u32 tx_stat_gtufl_lo;
2095 u32 tx_stat_gtufl_hi;
2096 u32 tx_stat_gterr_lo;
2097 u32 tx_stat_gterr_hi;
2098 u32 tx_stat_gtbyt_lo;
2099 u32 tx_stat_gtbyt_hi;
2100
2101 u32 rx_stat_gr64_lo;
2102 u32 rx_stat_gr64_hi;
2103 u32 rx_stat_gr127_lo;
2104 u32 rx_stat_gr127_hi;
2105 u32 rx_stat_gr255_lo;
2106 u32 rx_stat_gr255_hi;
2107 u32 rx_stat_gr511_lo;
2108 u32 rx_stat_gr511_hi;
2109 u32 rx_stat_gr1023_lo;
2110 u32 rx_stat_gr1023_hi;
2111 u32 rx_stat_gr1518_lo;
2112 u32 rx_stat_gr1518_hi;
2113 u32 rx_stat_gr2047_lo;
2114 u32 rx_stat_gr2047_hi;
2115 u32 rx_stat_gr4095_lo;
2116 u32 rx_stat_gr4095_hi;
2117 u32 rx_stat_gr9216_lo;
2118 u32 rx_stat_gr9216_hi;
2119 u32 rx_stat_gr16383_lo;
2120 u32 rx_stat_gr16383_hi;
2121 u32 rx_stat_grmax_lo;
2122 u32 rx_stat_grmax_hi;
2123 u32 rx_stat_grpkt_lo;
2124 u32 rx_stat_grpkt_hi;
2125 u32 rx_stat_grfcs_lo;
2126 u32 rx_stat_grfcs_hi;
2127 u32 rx_stat_grmca_lo;
2128 u32 rx_stat_grmca_hi;
2129 u32 rx_stat_grbca_lo;
2130 u32 rx_stat_grbca_hi;
2131 u32 rx_stat_grxcf_lo;
2132 u32 rx_stat_grxcf_hi;
2133 u32 rx_stat_grxpf_lo;
2134 u32 rx_stat_grxpf_hi;
2135 u32 rx_stat_grxuo_lo;
2136 u32 rx_stat_grxuo_hi;
2137 u32 rx_stat_grjbr_lo;
2138 u32 rx_stat_grjbr_hi;
2139 u32 rx_stat_grovr_lo;
2140 u32 rx_stat_grovr_hi;
2141 u32 rx_stat_grflr_lo;
2142 u32 rx_stat_grflr_hi;
2143 u32 rx_stat_grmeg_lo;
2144 u32 rx_stat_grmeg_hi;
2145 u32 rx_stat_grmeb_lo;
2146 u32 rx_stat_grmeb_hi;
2147 u32 rx_stat_grbyt_lo;
2148 u32 rx_stat_grbyt_hi;
2149 u32 rx_stat_grund_lo;
2150 u32 rx_stat_grund_hi;
2151 u32 rx_stat_grfrg_lo;
2152 u32 rx_stat_grfrg_hi;
2153 u32 rx_stat_grerb_lo;
2154 u32 rx_stat_grerb_hi;
2155 u32 rx_stat_grfre_lo;
2156 u32 rx_stat_grfre_hi;
2157 u32 rx_stat_gripj_lo;
2158 u32 rx_stat_gripj_hi;
2159};
2160
2161struct bmac2_stats {
2162 u32 tx_stat_gtpk_lo;
2163 u32 tx_stat_gtpk_hi;
2164 u32 tx_stat_gtxpf_lo;
2165 u32 tx_stat_gtxpf_hi;
2166 u32 tx_stat_gtpp_lo;
2167 u32 tx_stat_gtpp_hi;
2168 u32 tx_stat_gtfcs_lo;
2169 u32 tx_stat_gtfcs_hi;
2170 u32 tx_stat_gtuca_lo;
2171 u32 tx_stat_gtuca_hi;
2172 u32 tx_stat_gtmca_lo;
2173 u32 tx_stat_gtmca_hi;
2174 u32 tx_stat_gtbca_lo;
2175 u32 tx_stat_gtbca_hi;
2176 u32 tx_stat_gtovr_lo;
2177 u32 tx_stat_gtovr_hi;
2178 u32 tx_stat_gtfrg_lo;
2179 u32 tx_stat_gtfrg_hi;
2180 u32 tx_stat_gtpkt1_lo;
2181 u32 tx_stat_gtpkt1_hi;
2182 u32 tx_stat_gt64_lo;
2183 u32 tx_stat_gt64_hi;
2184 u32 tx_stat_gt127_lo;
2185 u32 tx_stat_gt127_hi;
2186 u32 tx_stat_gt255_lo;
2187 u32 tx_stat_gt255_hi;
2188 u32 tx_stat_gt511_lo;
2189 u32 tx_stat_gt511_hi;
2190 u32 tx_stat_gt1023_lo;
2191 u32 tx_stat_gt1023_hi;
2192 u32 tx_stat_gt1518_lo;
2193 u32 tx_stat_gt1518_hi;
2194 u32 tx_stat_gt2047_lo;
2195 u32 tx_stat_gt2047_hi;
2196 u32 tx_stat_gt4095_lo;
2197 u32 tx_stat_gt4095_hi;
2198 u32 tx_stat_gt9216_lo;
2199 u32 tx_stat_gt9216_hi;
2200 u32 tx_stat_gt16383_lo;
2201 u32 tx_stat_gt16383_hi;
2202 u32 tx_stat_gtmax_lo;
2203 u32 tx_stat_gtmax_hi;
2204 u32 tx_stat_gtufl_lo;
2205 u32 tx_stat_gtufl_hi;
2206 u32 tx_stat_gterr_lo;
2207 u32 tx_stat_gterr_hi;
2208 u32 tx_stat_gtbyt_lo;
2209 u32 tx_stat_gtbyt_hi;
2210
2211 u32 rx_stat_gr64_lo;
2212 u32 rx_stat_gr64_hi;
2213 u32 rx_stat_gr127_lo;
2214 u32 rx_stat_gr127_hi;
2215 u32 rx_stat_gr255_lo;
2216 u32 rx_stat_gr255_hi;
2217 u32 rx_stat_gr511_lo;
2218 u32 rx_stat_gr511_hi;
2219 u32 rx_stat_gr1023_lo;
2220 u32 rx_stat_gr1023_hi;
2221 u32 rx_stat_gr1518_lo;
2222 u32 rx_stat_gr1518_hi;
2223 u32 rx_stat_gr2047_lo;
2224 u32 rx_stat_gr2047_hi;
2225 u32 rx_stat_gr4095_lo;
2226 u32 rx_stat_gr4095_hi;
2227 u32 rx_stat_gr9216_lo;
2228 u32 rx_stat_gr9216_hi;
2229 u32 rx_stat_gr16383_lo;
2230 u32 rx_stat_gr16383_hi;
2231 u32 rx_stat_grmax_lo;
2232 u32 rx_stat_grmax_hi;
2233 u32 rx_stat_grpkt_lo;
2234 u32 rx_stat_grpkt_hi;
2235 u32 rx_stat_grfcs_lo;
2236 u32 rx_stat_grfcs_hi;
2237 u32 rx_stat_gruca_lo;
2238 u32 rx_stat_gruca_hi;
2239 u32 rx_stat_grmca_lo;
2240 u32 rx_stat_grmca_hi;
2241 u32 rx_stat_grbca_lo;
2242 u32 rx_stat_grbca_hi;
2243 u32 rx_stat_grxpf_lo;
2244 u32 rx_stat_grxpf_hi;
2245 u32 rx_stat_grpp_lo;
2246 u32 rx_stat_grpp_hi;
2247 u32 rx_stat_grxuo_lo;
2248 u32 rx_stat_grxuo_hi;
2249 u32 rx_stat_grjbr_lo;
2250 u32 rx_stat_grjbr_hi;
2251 u32 rx_stat_grovr_lo;
2252 u32 rx_stat_grovr_hi;
2253 u32 rx_stat_grxcf_lo;
2254 u32 rx_stat_grxcf_hi;
2255 u32 rx_stat_grflr_lo;
2256 u32 rx_stat_grflr_hi;
2257 u32 rx_stat_grpok_lo;
2258 u32 rx_stat_grpok_hi;
2259 u32 rx_stat_grmeg_lo;
2260 u32 rx_stat_grmeg_hi;
2261 u32 rx_stat_grmeb_lo;
2262 u32 rx_stat_grmeb_hi;
2263 u32 rx_stat_grbyt_lo;
2264 u32 rx_stat_grbyt_hi;
2265 u32 rx_stat_grund_lo;
2266 u32 rx_stat_grund_hi;
2267 u32 rx_stat_grfrg_lo;
2268 u32 rx_stat_grfrg_hi;
2269 u32 rx_stat_grerb_lo;
2270 u32 rx_stat_grerb_hi;
2271 u32 rx_stat_grfre_lo;
2272 u32 rx_stat_grfre_hi;
2273 u32 rx_stat_gripj_lo;
2274 u32 rx_stat_gripj_hi;
2275};
2276
2277struct mstat_stats {
2278 struct {
2279
2280
2281
2282 u32 tx_gtxpok_lo;
2283 u32 tx_gtxpok_hi;
2284 u32 tx_gtxpf_lo;
2285 u32 tx_gtxpf_hi;
2286 u32 tx_gtxpp_lo;
2287 u32 tx_gtxpp_hi;
2288 u32 tx_gtfcs_lo;
2289 u32 tx_gtfcs_hi;
2290 u32 tx_gtuca_lo;
2291 u32 tx_gtuca_hi;
2292 u32 tx_gtmca_lo;
2293 u32 tx_gtmca_hi;
2294 u32 tx_gtgca_lo;
2295 u32 tx_gtgca_hi;
2296 u32 tx_gtpkt_lo;
2297 u32 tx_gtpkt_hi;
2298 u32 tx_gt64_lo;
2299 u32 tx_gt64_hi;
2300 u32 tx_gt127_lo;
2301 u32 tx_gt127_hi;
2302 u32 tx_gt255_lo;
2303 u32 tx_gt255_hi;
2304 u32 tx_gt511_lo;
2305 u32 tx_gt511_hi;
2306 u32 tx_gt1023_lo;
2307 u32 tx_gt1023_hi;
2308 u32 tx_gt1518_lo;
2309 u32 tx_gt1518_hi;
2310 u32 tx_gt2047_lo;
2311 u32 tx_gt2047_hi;
2312 u32 tx_gt4095_lo;
2313 u32 tx_gt4095_hi;
2314 u32 tx_gt9216_lo;
2315 u32 tx_gt9216_hi;
2316 u32 tx_gt16383_lo;
2317 u32 tx_gt16383_hi;
2318 u32 tx_gtufl_lo;
2319 u32 tx_gtufl_hi;
2320 u32 tx_gterr_lo;
2321 u32 tx_gterr_hi;
2322 u32 tx_gtbyt_lo;
2323 u32 tx_gtbyt_hi;
2324 u32 tx_collisions_lo;
2325 u32 tx_collisions_hi;
2326 u32 tx_singlecollision_lo;
2327 u32 tx_singlecollision_hi;
2328 u32 tx_multiplecollisions_lo;
2329 u32 tx_multiplecollisions_hi;
2330 u32 tx_deferred_lo;
2331 u32 tx_deferred_hi;
2332 u32 tx_excessivecollisions_lo;
2333 u32 tx_excessivecollisions_hi;
2334 u32 tx_latecollisions_lo;
2335 u32 tx_latecollisions_hi;
2336 } stats_tx;
2337
2338 struct {
2339 u32 rx_gr64_lo;
2340 u32 rx_gr64_hi;
2341 u32 rx_gr127_lo;
2342 u32 rx_gr127_hi;
2343 u32 rx_gr255_lo;
2344 u32 rx_gr255_hi;
2345 u32 rx_gr511_lo;
2346 u32 rx_gr511_hi;
2347 u32 rx_gr1023_lo;
2348 u32 rx_gr1023_hi;
2349 u32 rx_gr1518_lo;
2350 u32 rx_gr1518_hi;
2351 u32 rx_gr2047_lo;
2352 u32 rx_gr2047_hi;
2353 u32 rx_gr4095_lo;
2354 u32 rx_gr4095_hi;
2355 u32 rx_gr9216_lo;
2356 u32 rx_gr9216_hi;
2357 u32 rx_gr16383_lo;
2358 u32 rx_gr16383_hi;
2359 u32 rx_grpkt_lo;
2360 u32 rx_grpkt_hi;
2361 u32 rx_grfcs_lo;
2362 u32 rx_grfcs_hi;
2363 u32 rx_gruca_lo;
2364 u32 rx_gruca_hi;
2365 u32 rx_grmca_lo;
2366 u32 rx_grmca_hi;
2367 u32 rx_grbca_lo;
2368 u32 rx_grbca_hi;
2369 u32 rx_grxpf_lo;
2370 u32 rx_grxpf_hi;
2371 u32 rx_grxpp_lo;
2372 u32 rx_grxpp_hi;
2373 u32 rx_grxuo_lo;
2374 u32 rx_grxuo_hi;
2375 u32 rx_grovr_lo;
2376 u32 rx_grovr_hi;
2377 u32 rx_grxcf_lo;
2378 u32 rx_grxcf_hi;
2379 u32 rx_grflr_lo;
2380 u32 rx_grflr_hi;
2381 u32 rx_grpok_lo;
2382 u32 rx_grpok_hi;
2383 u32 rx_grbyt_lo;
2384 u32 rx_grbyt_hi;
2385 u32 rx_grund_lo;
2386 u32 rx_grund_hi;
2387 u32 rx_grfrg_lo;
2388 u32 rx_grfrg_hi;
2389 u32 rx_grerb_lo;
2390 u32 rx_grerb_hi;
2391 u32 rx_grfre_lo;
2392 u32 rx_grfre_hi;
2393
2394 u32 rx_alignmenterrors_lo;
2395 u32 rx_alignmenterrors_hi;
2396 u32 rx_falsecarrier_lo;
2397 u32 rx_falsecarrier_hi;
2398 u32 rx_llfcmsgcnt_lo;
2399 u32 rx_llfcmsgcnt_hi;
2400 } stats_rx;
2401};
2402
2403union mac_stats {
2404 struct emac_stats emac_stats;
2405 struct bmac1_stats bmac1_stats;
2406 struct bmac2_stats bmac2_stats;
2407 struct mstat_stats mstat_stats;
2408};
2409
2410
2411struct mac_stx {
2412
2413 u32 rx_stat_ifhcinbadoctets_hi;
2414 u32 rx_stat_ifhcinbadoctets_lo;
2415
2416
2417 u32 tx_stat_ifhcoutbadoctets_hi;
2418 u32 tx_stat_ifhcoutbadoctets_lo;
2419
2420
2421 u32 rx_stat_dot3statsfcserrors_hi;
2422 u32 rx_stat_dot3statsfcserrors_lo;
2423
2424 u32 rx_stat_dot3statsalignmenterrors_hi;
2425 u32 rx_stat_dot3statsalignmenterrors_lo;
2426
2427 u32 rx_stat_dot3statscarriersenseerrors_hi;
2428 u32 rx_stat_dot3statscarriersenseerrors_lo;
2429
2430 u32 rx_stat_falsecarriererrors_hi;
2431 u32 rx_stat_falsecarriererrors_lo;
2432
2433
2434 u32 rx_stat_etherstatsundersizepkts_hi;
2435 u32 rx_stat_etherstatsundersizepkts_lo;
2436
2437 u32 rx_stat_dot3statsframestoolong_hi;
2438 u32 rx_stat_dot3statsframestoolong_lo;
2439
2440
2441 u32 rx_stat_etherstatsfragments_hi;
2442 u32 rx_stat_etherstatsfragments_lo;
2443
2444 u32 rx_stat_etherstatsjabbers_hi;
2445 u32 rx_stat_etherstatsjabbers_lo;
2446
2447
2448 u32 rx_stat_maccontrolframesreceived_hi;
2449 u32 rx_stat_maccontrolframesreceived_lo;
2450 u32 rx_stat_mac_xpf_hi;
2451 u32 rx_stat_mac_xpf_lo;
2452 u32 rx_stat_mac_xcf_hi;
2453 u32 rx_stat_mac_xcf_lo;
2454
2455
2456 u32 rx_stat_xoffstateentered_hi;
2457 u32 rx_stat_xoffstateentered_lo;
2458
2459 u32 rx_stat_xonpauseframesreceived_hi;
2460 u32 rx_stat_xonpauseframesreceived_lo;
2461
2462 u32 rx_stat_xoffpauseframesreceived_hi;
2463 u32 rx_stat_xoffpauseframesreceived_lo;
2464
2465 u32 tx_stat_outxonsent_hi;
2466 u32 tx_stat_outxonsent_lo;
2467
2468 u32 tx_stat_outxoffsent_hi;
2469 u32 tx_stat_outxoffsent_lo;
2470
2471 u32 tx_stat_flowcontroldone_hi;
2472 u32 tx_stat_flowcontroldone_lo;
2473
2474
2475 u32 tx_stat_etherstatscollisions_hi;
2476 u32 tx_stat_etherstatscollisions_lo;
2477
2478 u32 tx_stat_dot3statssinglecollisionframes_hi;
2479 u32 tx_stat_dot3statssinglecollisionframes_lo;
2480
2481 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2482 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2483
2484 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2485 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2486
2487 u32 tx_stat_dot3statsexcessivecollisions_hi;
2488 u32 tx_stat_dot3statsexcessivecollisions_lo;
2489
2490 u32 tx_stat_dot3statslatecollisions_hi;
2491 u32 tx_stat_dot3statslatecollisions_lo;
2492
2493
2494 u32 tx_stat_etherstatspkts64octets_hi;
2495 u32 tx_stat_etherstatspkts64octets_lo;
2496
2497 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2498 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2499
2500 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2501 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2502
2503 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2504 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2505
2506 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2507 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2508
2509 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2510 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2511
2512 u32 tx_stat_etherstatspktsover1522octets_hi;
2513 u32 tx_stat_etherstatspktsover1522octets_lo;
2514 u32 tx_stat_mac_2047_hi;
2515 u32 tx_stat_mac_2047_lo;
2516 u32 tx_stat_mac_4095_hi;
2517 u32 tx_stat_mac_4095_lo;
2518 u32 tx_stat_mac_9216_hi;
2519 u32 tx_stat_mac_9216_lo;
2520 u32 tx_stat_mac_16383_hi;
2521 u32 tx_stat_mac_16383_lo;
2522
2523
2524 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2525 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2526
2527
2528 u32 tx_stat_mac_ufl_hi;
2529 u32 tx_stat_mac_ufl_lo;
2530};
2531
2532
2533#define MAC_STX_IDX_MAX 2
2534
2535struct host_port_stats {
2536 u32 host_port_stats_counter;
2537
2538 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2539
2540 u32 brb_drop_hi;
2541 u32 brb_drop_lo;
2542
2543 u32 not_used;
2544 u32 pfc_frames_tx_hi;
2545 u32 pfc_frames_tx_lo;
2546 u32 pfc_frames_rx_hi;
2547 u32 pfc_frames_rx_lo;
2548};
2549
2550
2551struct host_func_stats {
2552 u32 host_func_stats_start;
2553
2554 u32 total_bytes_received_hi;
2555 u32 total_bytes_received_lo;
2556
2557 u32 total_bytes_transmitted_hi;
2558 u32 total_bytes_transmitted_lo;
2559
2560 u32 total_unicast_packets_received_hi;
2561 u32 total_unicast_packets_received_lo;
2562
2563 u32 total_multicast_packets_received_hi;
2564 u32 total_multicast_packets_received_lo;
2565
2566 u32 total_broadcast_packets_received_hi;
2567 u32 total_broadcast_packets_received_lo;
2568
2569 u32 total_unicast_packets_transmitted_hi;
2570 u32 total_unicast_packets_transmitted_lo;
2571
2572 u32 total_multicast_packets_transmitted_hi;
2573 u32 total_multicast_packets_transmitted_lo;
2574
2575 u32 total_broadcast_packets_transmitted_hi;
2576 u32 total_broadcast_packets_transmitted_lo;
2577
2578 u32 valid_bytes_received_hi;
2579 u32 valid_bytes_received_lo;
2580
2581 u32 host_func_stats_end;
2582};
2583
2584
2585#define VICSTATST_UIF_INDEX 2
2586
2587
2588#define DRV_INFO_CUR_VER 1
2589
2590
2591enum drv_info_opcode {
2592 ETH_STATS_OPCODE,
2593 FCOE_STATS_OPCODE,
2594 ISCSI_STATS_OPCODE
2595};
2596
2597#define ETH_STAT_INFO_VERSION_LEN 12
2598
2599struct eth_stats_info {
2600
2601 u8 version[ETH_STAT_INFO_VERSION_LEN];
2602
2603 u8 mac_local[8];
2604 u8 mac_add1[8];
2605 u8 mac_add2[8];
2606 u32 mtu_size;
2607 u32 feature_flags;
2608#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01
2609#define FEATURE_ETH_LSO_MASK 0x02
2610#define FEATURE_ETH_BOOTMODE_MASK 0x1C
2611#define FEATURE_ETH_BOOTMODE_SHIFT 2
2612#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
2613#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2)
2614#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2)
2615#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2)
2616#define FEATURE_ETH_TOE_MASK 0x20
2617 u32 lso_max_size;
2618 u32 lso_min_seg_cnt;
2619
2620 u32 ipv4_ofld_cnt;
2621
2622 u32 ipv6_ofld_cnt;
2623 u32 promiscuous_mode;
2624 u32 txq_size;
2625 u32 rxq_size;
2626
2627 u32 txq_avg_depth;
2628
2629 u32 rxq_avg_depth;
2630
2631 u32 iov_offload;
2632
2633 u32 netq_cnt;
2634 u32 vf_cnt;
2635};
2636
2637
2638struct fcoe_stats_info {
2639 u8 version[12];
2640 u8 mac_local[8];
2641 u8 mac_add1[8];
2642 u8 mac_add2[8];
2643
2644 u32 qos_priority;
2645 u32 txq_size;
2646 u32 rxq_size;
2647
2648 u32 txq_avg_depth;
2649
2650 u32 rxq_avg_depth;
2651 u32 rx_frames_lo;
2652 u32 rx_frames_hi;
2653 u32 rx_bytes_lo;
2654 u32 rx_bytes_hi;
2655 u32 tx_frames_lo;
2656 u32 tx_frames_hi;
2657 u32 tx_bytes_lo;
2658 u32 tx_bytes_hi;
2659};
2660
2661
2662struct iscsi_stats_info {
2663 u8 version[12];
2664 u8 mac_local[8];
2665 u8 mac_add1[8];
2666
2667 u32 qos_priority;
2668 u8 initiator_name[64];
2669 u8 ww_port_name[64];
2670 u8 boot_target_name[64];
2671 u8 boot_target_ip[16];
2672 u32 boot_target_portal;
2673 u8 boot_init_ip[16];
2674 u32 max_frame_size;
2675 u32 txq_size;
2676 u32 rxq_size;
2677 u32 txq_avg_depth;
2678 u32 rxq_avg_depth;
2679 u32 rx_pdus_lo;
2680 u32 rx_pdus_hi;
2681 u32 rx_bytes_lo;
2682 u32 rx_bytes_hi;
2683 u32 tx_pdus_lo;
2684 u32 tx_pdus_hi;
2685 u32 tx_bytes_lo;
2686 u32 tx_bytes_hi;
2687 u32 pcp_prior_map_tbl;
2688
2689
2690
2691
2692};
2693
2694union drv_info_to_mcp {
2695 struct eth_stats_info ether_stat;
2696 struct fcoe_stats_info fcoe_stat;
2697 struct iscsi_stats_info iscsi_stat;
2698};
2699#define BCM_5710_FW_MAJOR_VERSION 7
2700#define BCM_5710_FW_MINOR_VERSION 2
2701#define BCM_5710_FW_REVISION_VERSION 16
2702#define BCM_5710_FW_ENGINEERING_VERSION 0
2703#define BCM_5710_FW_COMPILE_FLAGS 1
2704
2705
2706
2707
2708
2709struct atten_sp_status_block {
2710 __le32 attn_bits;
2711 __le32 attn_bits_ack;
2712 u8 status_block_id;
2713 u8 reserved0;
2714 __le16 attn_bits_index;
2715 __le32 reserved1;
2716};
2717
2718
2719
2720
2721
2722struct cstorm_eth_ag_context {
2723 u32 __reserved0[10];
2724};
2725
2726
2727
2728
2729
2730struct dmae_command {
2731 u32 opcode;
2732#define DMAE_COMMAND_SRC (0x1<<0)
2733#define DMAE_COMMAND_SRC_SHIFT 0
2734#define DMAE_COMMAND_DST (0x3<<1)
2735#define DMAE_COMMAND_DST_SHIFT 1
2736#define DMAE_COMMAND_C_DST (0x1<<3)
2737#define DMAE_COMMAND_C_DST_SHIFT 3
2738#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2739#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2740#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2741#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2742#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2743#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2744#define DMAE_COMMAND_ENDIANITY (0x3<<9)
2745#define DMAE_COMMAND_ENDIANITY_SHIFT 9
2746#define DMAE_COMMAND_PORT (0x1<<11)
2747#define DMAE_COMMAND_PORT_SHIFT 11
2748#define DMAE_COMMAND_CRC_RESET (0x1<<12)
2749#define DMAE_COMMAND_CRC_RESET_SHIFT 12
2750#define DMAE_COMMAND_SRC_RESET (0x1<<13)
2751#define DMAE_COMMAND_SRC_RESET_SHIFT 13
2752#define DMAE_COMMAND_DST_RESET (0x1<<14)
2753#define DMAE_COMMAND_DST_RESET_SHIFT 14
2754#define DMAE_COMMAND_E1HVN (0x3<<15)
2755#define DMAE_COMMAND_E1HVN_SHIFT 15
2756#define DMAE_COMMAND_DST_VN (0x3<<17)
2757#define DMAE_COMMAND_DST_VN_SHIFT 17
2758#define DMAE_COMMAND_C_FUNC (0x1<<19)
2759#define DMAE_COMMAND_C_FUNC_SHIFT 19
2760#define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2761#define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2762#define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2763#define DMAE_COMMAND_RESERVED0_SHIFT 22
2764 u32 src_addr_lo;
2765 u32 src_addr_hi;
2766 u32 dst_addr_lo;
2767 u32 dst_addr_hi;
2768#if defined(__BIG_ENDIAN)
2769 u16 opcode_iov;
2770#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2771#define DMAE_COMMAND_SRC_VFID_SHIFT 0
2772#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2773#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2774#define DMAE_COMMAND_RESERVED1 (0x1<<7)
2775#define DMAE_COMMAND_RESERVED1_SHIFT 7
2776#define DMAE_COMMAND_DST_VFID (0x3F<<8)
2777#define DMAE_COMMAND_DST_VFID_SHIFT 8
2778#define DMAE_COMMAND_DST_VFPF (0x1<<14)
2779#define DMAE_COMMAND_DST_VFPF_SHIFT 14
2780#define DMAE_COMMAND_RESERVED2 (0x1<<15)
2781#define DMAE_COMMAND_RESERVED2_SHIFT 15
2782 u16 len;
2783#elif defined(__LITTLE_ENDIAN)
2784 u16 len;
2785 u16 opcode_iov;
2786#define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2787#define DMAE_COMMAND_SRC_VFID_SHIFT 0
2788#define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2789#define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2790#define DMAE_COMMAND_RESERVED1 (0x1<<7)
2791#define DMAE_COMMAND_RESERVED1_SHIFT 7
2792#define DMAE_COMMAND_DST_VFID (0x3F<<8)
2793#define DMAE_COMMAND_DST_VFID_SHIFT 8
2794#define DMAE_COMMAND_DST_VFPF (0x1<<14)
2795#define DMAE_COMMAND_DST_VFPF_SHIFT 14
2796#define DMAE_COMMAND_RESERVED2 (0x1<<15)
2797#define DMAE_COMMAND_RESERVED2_SHIFT 15
2798#endif
2799 u32 comp_addr_lo;
2800 u32 comp_addr_hi;
2801 u32 comp_val;
2802 u32 crc32;
2803 u32 crc32_c;
2804#if defined(__BIG_ENDIAN)
2805 u16 crc16_c;
2806 u16 crc16;
2807#elif defined(__LITTLE_ENDIAN)
2808 u16 crc16;
2809 u16 crc16_c;
2810#endif
2811#if defined(__BIG_ENDIAN)
2812 u16 reserved3;
2813 u16 crc_t10;
2814#elif defined(__LITTLE_ENDIAN)
2815 u16 crc_t10;
2816 u16 reserved3;
2817#endif
2818#if defined(__BIG_ENDIAN)
2819 u16 xsum8;
2820 u16 xsum16;
2821#elif defined(__LITTLE_ENDIAN)
2822 u16 xsum16;
2823 u16 xsum8;
2824#endif
2825};
2826
2827
2828
2829
2830
2831struct doorbell_hdr {
2832 u8 header;
2833#define DOORBELL_HDR_RX (0x1<<0)
2834#define DOORBELL_HDR_RX_SHIFT 0
2835#define DOORBELL_HDR_DB_TYPE (0x1<<1)
2836#define DOORBELL_HDR_DB_TYPE_SHIFT 1
2837#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2838#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2839#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2840#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2841};
2842
2843
2844
2845
2846struct eth_tx_doorbell {
2847#if defined(__BIG_ENDIAN)
2848 u16 npackets;
2849 u8 params;
2850#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2851#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2852#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2853#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2854#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2855#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2856 struct doorbell_hdr hdr;
2857#elif defined(__LITTLE_ENDIAN)
2858 struct doorbell_hdr hdr;
2859 u8 params;
2860#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2861#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2862#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2863#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2864#define ETH_TX_DOORBELL_SPARE (0x1<<7)
2865#define ETH_TX_DOORBELL_SPARE_SHIFT 7
2866 u16 npackets;
2867#endif
2868};
2869
2870
2871
2872
2873
2874struct hc_status_block_e1x {
2875 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2876 __le16 running_index[HC_SB_MAX_SM];
2877 __le32 rsrv[11];
2878};
2879
2880
2881
2882
2883struct host_hc_status_block_e1x {
2884 struct hc_status_block_e1x sb;
2885};
2886
2887
2888
2889
2890
2891struct hc_status_block_e2 {
2892 __le16 index_values[HC_SB_MAX_INDICES_E2];
2893 __le16 running_index[HC_SB_MAX_SM];
2894 __le32 reserved[11];
2895};
2896
2897
2898
2899
2900struct host_hc_status_block_e2 {
2901 struct hc_status_block_e2 sb;
2902};
2903
2904
2905
2906
2907
2908struct hc_sp_status_block {
2909 __le16 index_values[HC_SP_SB_MAX_INDICES];
2910 __le16 running_index;
2911 __le16 rsrv;
2912 u32 rsrv1;
2913};
2914
2915
2916
2917
2918struct host_sp_status_block {
2919 struct atten_sp_status_block atten_status_block;
2920 struct hc_sp_status_block sp_sb;
2921};
2922
2923
2924
2925
2926
2927struct igu_ack_register {
2928#if defined(__BIG_ENDIAN)
2929 u16 sb_id_and_flags;
2930#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2931#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2932#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2933#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2934#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2935#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2936#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2937#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2938#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2939#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2940 u16 status_block_index;
2941#elif defined(__LITTLE_ENDIAN)
2942 u16 status_block_index;
2943 u16 sb_id_and_flags;
2944#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2945#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2946#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2947#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2948#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2949#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2950#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2951#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2952#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2953#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2954#endif
2955};
2956
2957
2958
2959
2960
2961struct igu_backward_compatible {
2962 u32 sb_id_and_flags;
2963#define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
2964#define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
2965#define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2966#define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2967#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2968#define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2969#define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2970#define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2971#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2972#define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2973#define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2974#define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2975 u32 reserved_2;
2976};
2977
2978
2979
2980
2981
2982struct igu_regular {
2983 u32 sb_id_and_flags;
2984#define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2985#define IGU_REGULAR_SB_INDEX_SHIFT 0
2986#define IGU_REGULAR_RESERVED0 (0x1<<20)
2987#define IGU_REGULAR_RESERVED0_SHIFT 20
2988#define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2989#define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2990#define IGU_REGULAR_BUPDATE (0x1<<24)
2991#define IGU_REGULAR_BUPDATE_SHIFT 24
2992#define IGU_REGULAR_ENABLE_INT (0x3<<25)
2993#define IGU_REGULAR_ENABLE_INT_SHIFT 25
2994#define IGU_REGULAR_RESERVED_1 (0x1<<27)
2995#define IGU_REGULAR_RESERVED_1_SHIFT 27
2996#define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2997#define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2998#define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2999#define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3000#define IGU_REGULAR_BCLEANUP (0x1<<31)
3001#define IGU_REGULAR_BCLEANUP_SHIFT 31
3002 u32 reserved_2;
3003};
3004
3005
3006
3007
3008union igu_consprod_reg {
3009 struct igu_regular regular;
3010 struct igu_backward_compatible backward_compatible;
3011};
3012
3013
3014
3015
3016
3017enum igu_ctrl_cmd {
3018 IGU_CTRL_CMD_TYPE_RD,
3019 IGU_CTRL_CMD_TYPE_WR,
3020 MAX_IGU_CTRL_CMD
3021};
3022
3023
3024
3025
3026
3027struct igu_ctrl_reg {
3028 u32 ctrl_data;
3029#define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3030#define IGU_CTRL_REG_ADDRESS_SHIFT 0
3031#define IGU_CTRL_REG_FID (0x7F<<12)
3032#define IGU_CTRL_REG_FID_SHIFT 12
3033#define IGU_CTRL_REG_RESERVED (0x1<<19)
3034#define IGU_CTRL_REG_RESERVED_SHIFT 19
3035#define IGU_CTRL_REG_TYPE (0x1<<20)
3036#define IGU_CTRL_REG_TYPE_SHIFT 20
3037#define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3038#define IGU_CTRL_REG_UNUSED_SHIFT 21
3039};
3040
3041
3042
3043
3044
3045enum igu_int_cmd {
3046 IGU_INT_ENABLE,
3047 IGU_INT_DISABLE,
3048 IGU_INT_NOP,
3049 IGU_INT_NOP2,
3050 MAX_IGU_INT_CMD
3051};
3052
3053
3054
3055
3056
3057enum igu_seg_access {
3058 IGU_SEG_ACCESS_NORM,
3059 IGU_SEG_ACCESS_DEF,
3060 IGU_SEG_ACCESS_ATTN,
3061 MAX_IGU_SEG_ACCESS
3062};
3063
3064
3065
3066
3067
3068struct parsing_flags {
3069 __le16 flags;
3070#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3071#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3072#define PARSING_FLAGS_VLAN (0x1<<1)
3073#define PARSING_FLAGS_VLAN_SHIFT 1
3074#define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3075#define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3076#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3077#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3078#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3079#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3080#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3081#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3082#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3083#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3084#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3085#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3086#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3087#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3088#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3089#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3090#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3091#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3092#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3093#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3094#define PARSING_FLAGS_RESERVED0 (0x3<<14)
3095#define PARSING_FLAGS_RESERVED0_SHIFT 14
3096};
3097
3098
3099
3100
3101
3102enum prs_flags_ack_type {
3103 PRS_FLAG_PUREACK_PIGGY,
3104 PRS_FLAG_PUREACK_PURE,
3105 MAX_PRS_FLAGS_ACK_TYPE
3106};
3107
3108
3109
3110
3111
3112enum prs_flags_eth_addr_type {
3113 PRS_FLAG_ETHTYPE_NON_UNICAST,
3114 PRS_FLAG_ETHTYPE_UNICAST,
3115 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3116};
3117
3118
3119
3120
3121
3122enum prs_flags_over_eth {
3123 PRS_FLAG_OVERETH_UNKNOWN,
3124 PRS_FLAG_OVERETH_IPV4,
3125 PRS_FLAG_OVERETH_IPV6,
3126 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3127 MAX_PRS_FLAGS_OVER_ETH
3128};
3129
3130
3131
3132
3133
3134enum prs_flags_over_ip {
3135 PRS_FLAG_OVERIP_UNKNOWN,
3136 PRS_FLAG_OVERIP_TCP,
3137 PRS_FLAG_OVERIP_UDP,
3138 MAX_PRS_FLAGS_OVER_IP
3139};
3140
3141
3142
3143
3144
3145struct sdm_op_gen {
3146 __le32 command;
3147#define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3148#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3149#define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3150#define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3151#define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3152#define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3153#define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3154#define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3155#define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3156#define SDM_OP_GEN_RESERVED_SHIFT 17
3157};
3158
3159
3160
3161
3162
3163struct timers_block_context {
3164 u32 __reserved_0;
3165 u32 __reserved_1;
3166 u32 __reserved_2;
3167 u32 flags;
3168#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3169#define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3170#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3171#define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3172#define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3173#define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3174};
3175
3176
3177
3178
3179
3180struct tstorm_eth_ag_context {
3181 u32 __reserved0[14];
3182};
3183
3184
3185
3186
3187
3188struct ustorm_eth_ag_context {
3189 u32 __reserved0;
3190#if defined(__BIG_ENDIAN)
3191 u8 cdu_usage;
3192 u8 __reserved2;
3193 u16 __reserved1;
3194#elif defined(__LITTLE_ENDIAN)
3195 u16 __reserved1;
3196 u8 __reserved2;
3197 u8 cdu_usage;
3198#endif
3199 u32 __reserved3[6];
3200};
3201
3202
3203
3204
3205
3206struct xstorm_eth_ag_context {
3207 u32 reserved0;
3208#if defined(__BIG_ENDIAN)
3209 u8 cdu_reserved;
3210 u8 reserved2;
3211 u16 reserved1;
3212#elif defined(__LITTLE_ENDIAN)
3213 u16 reserved1;
3214 u8 reserved2;
3215 u8 cdu_reserved;
3216#endif
3217 u32 reserved3[30];
3218};
3219
3220
3221
3222
3223
3224struct doorbell {
3225#if defined(__BIG_ENDIAN)
3226 u16 zero_fill2;
3227 u8 zero_fill1;
3228 struct doorbell_hdr header;
3229#elif defined(__LITTLE_ENDIAN)
3230 struct doorbell_hdr header;
3231 u8 zero_fill1;
3232 u16 zero_fill2;
3233#endif
3234};
3235
3236
3237
3238
3239
3240struct doorbell_set_prod {
3241#if defined(__BIG_ENDIAN)
3242 u16 prod;
3243 u8 zero_fill1;
3244 struct doorbell_hdr header;
3245#elif defined(__LITTLE_ENDIAN)
3246 struct doorbell_hdr header;
3247 u8 zero_fill1;
3248 u16 prod;
3249#endif
3250};
3251
3252
3253struct regpair {
3254 __le32 lo;
3255 __le32 hi;
3256};
3257
3258
3259
3260
3261
3262enum classify_rule {
3263 CLASSIFY_RULE_OPCODE_MAC,
3264 CLASSIFY_RULE_OPCODE_VLAN,
3265 CLASSIFY_RULE_OPCODE_PAIR,
3266 MAX_CLASSIFY_RULE
3267};
3268
3269
3270
3271
3272
3273enum classify_rule_action_type {
3274 CLASSIFY_RULE_REMOVE,
3275 CLASSIFY_RULE_ADD,
3276 MAX_CLASSIFY_RULE_ACTION_TYPE
3277};
3278
3279
3280
3281
3282
3283struct client_init_general_data {
3284 u8 client_id;
3285 u8 statistics_counter_id;
3286 u8 statistics_en_flg;
3287 u8 is_fcoe_flg;
3288 u8 activate_flg;
3289 u8 sp_client_id;
3290 __le16 mtu;
3291 u8 statistics_zero_flg;
3292 u8 func_id;
3293 u8 cos;
3294 u8 traffic_type;
3295 u32 reserved0;
3296};
3297
3298
3299
3300
3301
3302struct client_init_rx_data {
3303 u8 tpa_en;
3304#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3305#define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3306#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3307#define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3308#define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3309#define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3310#define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3311#define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3312 u8 vmqueue_mode_en_flg;
3313 u8 extra_data_over_sgl_en_flg;
3314 u8 cache_line_alignment_log_size;
3315 u8 enable_dynamic_hc;
3316 u8 max_sges_for_packet;
3317 u8 client_qzone_id;
3318 u8 drop_ip_cs_err_flg;
3319 u8 drop_tcp_cs_err_flg;
3320 u8 drop_ttl0_flg;
3321 u8 drop_udp_cs_err_flg;
3322 u8 inner_vlan_removal_enable_flg;
3323 u8 outer_vlan_removal_enable_flg;
3324 u8 status_block_id;
3325 u8 rx_sb_index_number;
3326 u8 dont_verify_rings_pause_thr_flg;
3327 u8 max_tpa_queues;
3328 u8 silent_vlan_removal_flg;
3329 __le16 max_bytes_on_bd;
3330 __le16 sge_buff_size;
3331 u8 approx_mcast_engine_id;
3332 u8 rss_engine_id;
3333 struct regpair bd_page_base;
3334 struct regpair sge_page_base;
3335 struct regpair cqe_page_base;
3336 u8 is_leading_rss;
3337 u8 is_approx_mcast;
3338 __le16 max_agg_size;
3339 __le16 state;
3340#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3341#define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3342#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3343#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3344#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3345#define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3346#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3347#define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3348#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3349#define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3350#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3351#define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3352#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3353#define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3354#define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3355#define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3356 __le16 cqe_pause_thr_low;
3357 __le16 cqe_pause_thr_high;
3358 __le16 bd_pause_thr_low;
3359 __le16 bd_pause_thr_high;
3360 __le16 sge_pause_thr_low;
3361 __le16 sge_pause_thr_high;
3362 __le16 rx_cos_mask;
3363 __le16 silent_vlan_value;
3364 __le16 silent_vlan_mask;
3365 __le32 reserved6[2];
3366};
3367
3368
3369
3370
3371struct client_init_tx_data {
3372 u8 enforce_security_flg;
3373 u8 tx_status_block_id;
3374 u8 tx_sb_index_number;
3375 u8 tss_leading_client_id;
3376 u8 tx_switching_flg;
3377 u8 anti_spoofing_flg;
3378 __le16 default_vlan;
3379 struct regpair tx_bd_page_base;
3380 __le16 state;
3381#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3382#define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3383#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3384#define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3385#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3386#define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3387#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3388#define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3389#define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3390#define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3391 u8 default_vlan_flg;
3392 u8 reserved2;
3393 __le32 reserved3;
3394};
3395
3396
3397
3398
3399struct client_init_ramrod_data {
3400 struct client_init_general_data general;
3401 struct client_init_rx_data rx;
3402 struct client_init_tx_data tx;
3403};
3404
3405
3406
3407
3408
3409struct client_update_ramrod_data {
3410 u8 client_id;
3411 u8 func_id;
3412 u8 inner_vlan_removal_enable_flg;
3413 u8 inner_vlan_removal_change_flg;
3414 u8 outer_vlan_removal_enable_flg;
3415 u8 outer_vlan_removal_change_flg;
3416 u8 anti_spoofing_enable_flg;
3417 u8 anti_spoofing_change_flg;
3418 u8 activate_flg;
3419 u8 activate_change_flg;
3420 __le16 default_vlan;
3421 u8 default_vlan_enable_flg;
3422 u8 default_vlan_change_flg;
3423 __le16 silent_vlan_value;
3424 __le16 silent_vlan_mask;
3425 u8 silent_vlan_removal_flg;
3426 u8 silent_vlan_change_flg;
3427 __le32 echo;
3428};
3429
3430
3431
3432
3433
3434struct cstorm_eth_st_context {
3435 u32 __reserved0[4];
3436};
3437
3438
3439struct double_regpair {
3440 u32 regpair0_lo;
3441 u32 regpair0_hi;
3442 u32 regpair1_lo;
3443 u32 regpair1_hi;
3444};
3445
3446
3447
3448
3449
3450enum eth_addr_type {
3451 UNKNOWN_ADDRESS,
3452 UNICAST_ADDRESS,
3453 MULTICAST_ADDRESS,
3454 BROADCAST_ADDRESS,
3455 MAX_ETH_ADDR_TYPE
3456};
3457
3458
3459
3460
3461
3462struct eth_classify_cmd_header {
3463 u8 cmd_general_data;
3464#define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3465#define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3466#define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3467#define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3468#define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3469#define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3470#define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3471#define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3472#define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3473#define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3474 u8 func_id;
3475 u8 client_id;
3476 u8 reserved1;
3477};
3478
3479
3480
3481
3482
3483struct eth_classify_header {
3484 u8 rule_cnt;
3485 u8 reserved0;
3486 __le16 reserved1;
3487 __le32 echo;
3488};
3489
3490
3491
3492
3493
3494struct eth_classify_mac_cmd {
3495 struct eth_classify_cmd_header header;
3496 __le32 reserved0;
3497 __le16 mac_lsb;
3498 __le16 mac_mid;
3499 __le16 mac_msb;
3500 __le16 reserved1;
3501};
3502
3503
3504
3505
3506
3507struct eth_classify_pair_cmd {
3508 struct eth_classify_cmd_header header;
3509 __le32 reserved0;
3510 __le16 mac_lsb;
3511 __le16 mac_mid;
3512 __le16 mac_msb;
3513 __le16 vlan;
3514};
3515
3516
3517
3518
3519
3520struct eth_classify_vlan_cmd {
3521 struct eth_classify_cmd_header header;
3522 __le32 reserved0;
3523 __le32 reserved1;
3524 __le16 reserved2;
3525 __le16 vlan;
3526};
3527
3528
3529
3530
3531union eth_classify_rule_cmd {
3532 struct eth_classify_mac_cmd mac;
3533 struct eth_classify_vlan_cmd vlan;
3534 struct eth_classify_pair_cmd pair;
3535};
3536
3537
3538
3539
3540struct eth_classify_rules_ramrod_data {
3541 struct eth_classify_header header;
3542 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3543};
3544
3545
3546
3547
3548
3549struct eth_common_ramrod_data {
3550 __le32 client_id;
3551 __le32 reserved1;
3552};
3553
3554
3555
3556
3557
3558struct ustorm_eth_st_context {
3559 u32 reserved0[52];
3560};
3561
3562
3563
3564
3565struct tstorm_eth_st_context {
3566 u32 __reserved0[28];
3567};
3568
3569
3570
3571
3572struct xstorm_eth_st_context {
3573 u32 reserved0[60];
3574};
3575
3576
3577
3578
3579struct eth_context {
3580 struct ustorm_eth_st_context ustorm_st_context;
3581 struct tstorm_eth_st_context tstorm_st_context;
3582 struct xstorm_eth_ag_context xstorm_ag_context;
3583 struct tstorm_eth_ag_context tstorm_ag_context;
3584 struct cstorm_eth_ag_context cstorm_ag_context;
3585 struct ustorm_eth_ag_context ustorm_ag_context;
3586 struct timers_block_context timers_context;
3587 struct xstorm_eth_st_context xstorm_st_context;
3588 struct cstorm_eth_st_context cstorm_st_context;
3589};
3590
3591
3592
3593
3594
3595union eth_sgl_or_raw_data {
3596 __le16 sgl[8];
3597 u32 raw_data[4];
3598};
3599
3600
3601
3602
3603struct eth_end_agg_rx_cqe {
3604 u8 type_error_flags;
3605#define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3606#define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3607#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3608#define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3609#define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3610#define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3611 u8 reserved1;
3612 u8 queue_index;
3613 u8 reserved2;
3614 __le32 timestamp_delta;
3615 __le16 num_of_coalesced_segs;
3616 __le16 pkt_len;
3617 u8 pure_ack_count;
3618 u8 reserved3;
3619 __le16 reserved4;
3620 union eth_sgl_or_raw_data sgl_or_raw_data;
3621 __le32 reserved5[8];
3622};
3623
3624
3625
3626
3627
3628struct eth_fast_path_rx_cqe {
3629 u8 type_error_flags;
3630#define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3631#define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3632#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3633#define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3634#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3635#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3636#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3637#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3638#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3639#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3640#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3641#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3642 u8 status_flags;
3643#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3644#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3645#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3646#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3647#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3648#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3649#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3650#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3651#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3652#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3653#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3654#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3655 u8 queue_index;
3656 u8 placement_offset;
3657 __le32 rss_hash_result;
3658 __le16 vlan_tag;
3659 __le16 pkt_len_or_gro_seg_len;
3660 __le16 len_on_bd;
3661 struct parsing_flags pars_flags;
3662 union eth_sgl_or_raw_data sgl_or_raw_data;
3663 __le32 reserved1[8];
3664};
3665
3666
3667
3668
3669
3670struct eth_filter_rules_cmd {
3671 u8 cmd_general_data;
3672#define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3673#define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3674#define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3675#define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3676#define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3677#define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3678 u8 func_id;
3679 u8 client_id;
3680 u8 reserved1;
3681 __le16 state;
3682#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3683#define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3684#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3685#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3686#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3687#define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3688#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3689#define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3690#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3691#define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3692#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3693#define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3694#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3695#define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3696#define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3697#define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3698 __le16 reserved3;
3699 struct regpair reserved4;
3700};
3701
3702
3703
3704
3705
3706struct eth_filter_rules_ramrod_data {
3707 struct eth_classify_header header;
3708 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3709};
3710
3711
3712
3713
3714
3715struct eth_general_rules_ramrod_data {
3716 struct eth_classify_header header;
3717 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3718};
3719
3720
3721
3722
3723
3724struct eth_halt_ramrod_data {
3725 __le32 client_id;
3726 __le32 reserved0;
3727};
3728
3729
3730
3731
3732
3733struct eth_multicast_rules_cmd {
3734 u8 cmd_general_data;
3735#define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3736#define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3737#define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3738#define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3739#define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3740#define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3741#define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3742#define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3743 u8 func_id;
3744 u8 bin_id;
3745 u8 engine_id;
3746 __le32 reserved2;
3747 struct regpair reserved3;
3748};
3749
3750
3751
3752
3753
3754struct eth_multicast_rules_ramrod_data {
3755 struct eth_classify_header header;
3756 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3757};
3758
3759
3760
3761
3762
3763struct ramrod_data {
3764 __le32 data_lo;
3765 __le32 data_hi;
3766};
3767
3768
3769
3770
3771union eth_ramrod_data {
3772 struct ramrod_data general;
3773};
3774
3775
3776
3777
3778
3779enum eth_rss_hash_type {
3780 DEFAULT_HASH_TYPE,
3781 IPV4_HASH_TYPE,
3782 TCP_IPV4_HASH_TYPE,
3783 IPV6_HASH_TYPE,
3784 TCP_IPV6_HASH_TYPE,
3785 VLAN_PRI_HASH_TYPE,
3786 E1HOV_PRI_HASH_TYPE,
3787 DSCP_HASH_TYPE,
3788 MAX_ETH_RSS_HASH_TYPE
3789};
3790
3791
3792
3793
3794
3795enum eth_rss_mode {
3796 ETH_RSS_MODE_DISABLED,
3797 ETH_RSS_MODE_REGULAR,
3798 ETH_RSS_MODE_VLAN_PRI,
3799 ETH_RSS_MODE_E1HOV_PRI,
3800 ETH_RSS_MODE_IP_DSCP,
3801 MAX_ETH_RSS_MODE
3802};
3803
3804
3805
3806
3807
3808struct eth_rss_update_ramrod_data {
3809 u8 rss_engine_id;
3810 u8 capabilities;
3811#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3812#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3813#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3814#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3815#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3816#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3817#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3818#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3819#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3820#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3821#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3822#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3823#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
3824#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
3825#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3826#define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3827 u8 rss_result_mask;
3828 u8 rss_mode;
3829 __le32 __reserved2;
3830 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
3831 __le32 rss_key[T_ETH_RSS_KEY];
3832 __le32 echo;
3833 __le32 reserved3;
3834};
3835
3836
3837
3838
3839
3840struct eth_rx_bd {
3841 __le32 addr_lo;
3842 __le32 addr_hi;
3843};
3844
3845
3846
3847
3848
3849struct common_ramrod_eth_rx_cqe {
3850 u8 ramrod_type;
3851#define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3852#define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3853#define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3854#define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3855#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3856#define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3857 u8 conn_type;
3858 __le16 reserved1;
3859 __le32 conn_and_cmd_data;
3860#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3861#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3862#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3863#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3864 struct ramrod_data protocol_data;
3865 __le32 echo;
3866 __le32 reserved2[11];
3867};
3868
3869
3870
3871
3872struct eth_rx_cqe_next_page {
3873 __le32 addr_lo;
3874 __le32 addr_hi;
3875 __le32 reserved[14];
3876};
3877
3878
3879
3880
3881union eth_rx_cqe {
3882 struct eth_fast_path_rx_cqe fast_path_cqe;
3883 struct common_ramrod_eth_rx_cqe ramrod_cqe;
3884 struct eth_rx_cqe_next_page next_page_cqe;
3885 struct eth_end_agg_rx_cqe end_agg_cqe;
3886};
3887
3888
3889
3890
3891
3892enum eth_rx_cqe_type {
3893 RX_ETH_CQE_TYPE_ETH_FASTPATH,
3894 RX_ETH_CQE_TYPE_ETH_RAMROD,
3895 RX_ETH_CQE_TYPE_ETH_START_AGG,
3896 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
3897 MAX_ETH_RX_CQE_TYPE
3898};
3899
3900
3901
3902
3903
3904enum eth_rx_fp_sel {
3905 ETH_FP_CQE_REGULAR,
3906 ETH_FP_CQE_RAW,
3907 MAX_ETH_RX_FP_SEL
3908};
3909
3910
3911
3912
3913
3914struct eth_rx_sge {
3915 __le32 addr_lo;
3916 __le32 addr_hi;
3917};
3918
3919
3920
3921
3922
3923struct spe_hdr {
3924 __le32 conn_and_cmd_data;
3925#define SPE_HDR_CID (0xFFFFFF<<0)
3926#define SPE_HDR_CID_SHIFT 0
3927#define SPE_HDR_CMD_ID (0xFF<<24)
3928#define SPE_HDR_CMD_ID_SHIFT 24
3929 __le16 type;
3930#define SPE_HDR_CONN_TYPE (0xFF<<0)
3931#define SPE_HDR_CONN_TYPE_SHIFT 0
3932#define SPE_HDR_FUNCTION_ID (0xFF<<8)
3933#define SPE_HDR_FUNCTION_ID_SHIFT 8
3934 __le16 reserved1;
3935};
3936
3937
3938
3939
3940union eth_specific_data {
3941 u8 protocol_data[8];
3942 struct regpair client_update_ramrod_data;
3943 struct regpair client_init_ramrod_init_data;
3944 struct eth_halt_ramrod_data halt_ramrod_data;
3945 struct regpair update_data_addr;
3946 struct eth_common_ramrod_data common_ramrod_data;
3947 struct regpair classify_cfg_addr;
3948 struct regpair filter_cfg_addr;
3949 struct regpair mcast_cfg_addr;
3950};
3951
3952
3953
3954
3955struct eth_spe {
3956 struct spe_hdr hdr;
3957 union eth_specific_data data;
3958};
3959
3960
3961
3962
3963
3964enum eth_spqe_cmd_id {
3965 RAMROD_CMD_ID_ETH_UNUSED,
3966 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
3967 RAMROD_CMD_ID_ETH_HALT,
3968 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
3969 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
3970 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
3971 RAMROD_CMD_ID_ETH_EMPTY,
3972 RAMROD_CMD_ID_ETH_TERMINATE,
3973 RAMROD_CMD_ID_ETH_TPA_UPDATE,
3974 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
3975 RAMROD_CMD_ID_ETH_FILTER_RULES,
3976 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3977 RAMROD_CMD_ID_ETH_RSS_UPDATE,
3978 RAMROD_CMD_ID_ETH_SET_MAC,
3979 MAX_ETH_SPQE_CMD_ID
3980};
3981
3982
3983
3984
3985
3986enum eth_tpa_update_command {
3987 TPA_UPDATE_NONE_COMMAND,
3988 TPA_UPDATE_ENABLE_COMMAND,
3989 TPA_UPDATE_DISABLE_COMMAND,
3990 MAX_ETH_TPA_UPDATE_COMMAND
3991};
3992
3993
3994
3995
3996
3997struct eth_tx_bd {
3998 __le32 addr_lo;
3999 __le32 addr_hi;
4000 __le16 total_pkt_bytes;
4001 __le16 nbytes;
4002 u8 reserved[4];
4003};
4004
4005
4006
4007
4008
4009struct eth_tx_bd_flags {
4010 u8 as_bitfield;
4011#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4012#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4013#define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4014#define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4015#define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4016#define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4017#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4018#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4019#define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4020#define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4021#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4022#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4023#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4024#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4025};
4026
4027
4028
4029
4030struct eth_tx_start_bd {
4031 __le32 addr_lo;
4032 __le32 addr_hi;
4033 __le16 nbd;
4034 __le16 nbytes;
4035 __le16 vlan_or_ethertype;
4036 struct eth_tx_bd_flags bd_flags;
4037 u8 general_data;
4038#define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4039#define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4040#define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4041#define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4042#define ETH_TX_START_BD_RESREVED (0x1<<5)
4043#define ETH_TX_START_BD_RESREVED_SHIFT 5
4044#define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
4045#define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
4046};
4047
4048
4049
4050
4051struct eth_tx_parse_bd_e1x {
4052 u8 global_data;
4053#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4054#define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4055#define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
4056#define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
4057#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
4058#define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
4059#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
4060#define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
4061#define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
4062#define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
4063 u8 tcp_flags;
4064#define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4065#define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4066#define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4067#define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4068#define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4069#define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4070#define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4071#define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4072#define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4073#define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4074#define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4075#define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4076#define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4077#define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4078#define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4079#define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4080 u8 ip_hlen_w;
4081 s8 reserved;
4082 __le16 total_hlen_w;
4083 __le16 tcp_pseudo_csum;
4084 __le16 lso_mss;
4085 __le16 ip_id;
4086 __le32 tcp_send_seq;
4087};
4088
4089
4090
4091
4092struct eth_tx_parse_bd_e2 {
4093 __le16 dst_mac_addr_lo;
4094 __le16 dst_mac_addr_mid;
4095 __le16 dst_mac_addr_hi;
4096 __le16 src_mac_addr_lo;
4097 __le16 src_mac_addr_mid;
4098 __le16 src_mac_addr_hi;
4099 __le32 parsing_data;
4100#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
4101#define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
4102#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
4103#define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
4104#define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
4105#define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
4106#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
4107#define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
4108};
4109
4110
4111
4112
4113struct eth_tx_next_bd {
4114 __le32 addr_lo;
4115 __le32 addr_hi;
4116 u8 reserved[8];
4117};
4118
4119
4120
4121
4122union eth_tx_bd_types {
4123 struct eth_tx_start_bd start_bd;
4124 struct eth_tx_bd reg_bd;
4125 struct eth_tx_parse_bd_e1x parse_bd_e1x;
4126 struct eth_tx_parse_bd_e2 parse_bd_e2;
4127 struct eth_tx_next_bd next_bd;
4128};
4129
4130
4131
4132
4133struct eth_tx_bds_array {
4134 union eth_tx_bd_types bds[13];
4135};
4136
4137
4138
4139
4140
4141enum eth_tx_vlan_type {
4142 X_ETH_NO_VLAN,
4143 X_ETH_OUTBAND_VLAN,
4144 X_ETH_INBAND_VLAN,
4145 X_ETH_FW_ADDED_VLAN,
4146 MAX_ETH_TX_VLAN_TYPE
4147};
4148
4149
4150
4151
4152
4153enum eth_vlan_filter_mode {
4154 ETH_VLAN_FILTER_ANY_VLAN,
4155 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4156 ETH_VLAN_FILTER_CLASSIFY,
4157 MAX_ETH_VLAN_FILTER_MODE
4158};
4159
4160
4161
4162
4163
4164struct mac_configuration_hdr {
4165 u8 length;
4166 u8 offset;
4167 __le16 client_id;
4168 __le32 echo;
4169};
4170
4171
4172
4173
4174struct mac_configuration_entry {
4175 __le16 lsb_mac_addr;
4176 __le16 middle_mac_addr;
4177 __le16 msb_mac_addr;
4178 __le16 vlan_id;
4179 u8 pf_id;
4180 u8 flags;
4181#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4182#define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4183#define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4184#define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4185#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4186#define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4187#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4188#define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4189#define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4190#define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4191#define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4192#define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4193 __le16 reserved0;
4194 __le32 clients_bit_vector;
4195};
4196
4197
4198
4199
4200struct mac_configuration_cmd {
4201 struct mac_configuration_hdr hdr;
4202 struct mac_configuration_entry config_table[64];
4203};
4204
4205
4206
4207
4208
4209enum set_mac_action_type {
4210 T_ETH_MAC_COMMAND_INVALIDATE,
4211 T_ETH_MAC_COMMAND_SET,
4212 MAX_SET_MAC_ACTION_TYPE
4213};
4214
4215
4216
4217
4218
4219enum tpa_mode {
4220 TPA_LRO,
4221 TPA_GRO,
4222 MAX_TPA_MODE};
4223
4224
4225
4226
4227
4228struct tpa_update_ramrod_data {
4229 u8 update_ipv4;
4230 u8 update_ipv6;
4231 u8 client_id;
4232 u8 max_tpa_queues;
4233 u8 max_sges_for_packet;
4234 u8 complete_on_both_clients;
4235 u8 dont_verify_rings_pause_thr_flg;
4236 u8 tpa_mode;
4237 __le16 sge_buff_size;
4238 __le16 max_agg_size;
4239 __le32 sge_page_base_lo;
4240 __le32 sge_page_base_hi;
4241 __le16 sge_pause_thr_low;
4242 __le16 sge_pause_thr_high;
4243};
4244
4245
4246
4247
4248
4249struct tstorm_eth_approximate_match_multicast_filtering {
4250 u32 mcast_add_hash_bit_array[8];
4251};
4252
4253
4254
4255
4256
4257struct tstorm_eth_function_common_config {
4258 __le16 config_flags;
4259#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4260#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4261#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4262#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4263#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4264#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4265#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4266#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4267#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4268#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4269#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4270#define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4271#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4272#define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4273 u8 rss_result_mask;
4274 u8 reserved1;
4275 __le16 vlan_id[2];
4276};
4277
4278
4279
4280
4281
4282struct tstorm_eth_mac_filter_config {
4283 __le32 ucast_drop_all;
4284 __le32 ucast_accept_all;
4285 __le32 mcast_drop_all;
4286 __le32 mcast_accept_all;
4287 __le32 bcast_accept_all;
4288 __le32 vlan_filter[2];
4289 __le32 unmatched_unicast;
4290};
4291
4292
4293
4294
4295
4296struct tx_queue_init_ramrod_data {
4297 struct client_init_general_data general;
4298 struct client_init_tx_data tx;
4299};
4300
4301
4302
4303
4304
4305struct ustorm_eth_rx_producers {
4306#if defined(__BIG_ENDIAN)
4307 u16 bd_prod;
4308 u16 cqe_prod;
4309#elif defined(__LITTLE_ENDIAN)
4310 u16 cqe_prod;
4311 u16 bd_prod;
4312#endif
4313#if defined(__BIG_ENDIAN)
4314 u16 reserved;
4315 u16 sge_prod;
4316#elif defined(__LITTLE_ENDIAN)
4317 u16 sge_prod;
4318 u16 reserved;
4319#endif
4320};
4321
4322
4323
4324
4325
4326struct fcoe_rx_stat_params_section0 {
4327 __le32 fcoe_rx_pkt_cnt;
4328 __le32 fcoe_rx_byte_cnt;
4329};
4330
4331
4332
4333
4334
4335struct fcoe_rx_stat_params_section1 {
4336 __le32 fcoe_ver_cnt;
4337 __le32 fcoe_rx_drop_pkt_cnt;
4338};
4339
4340
4341
4342
4343
4344struct fcoe_rx_stat_params_section2 {
4345 __le32 fc_crc_cnt;
4346 __le32 eofa_del_cnt;
4347 __le32 miss_frame_cnt;
4348 __le32 seq_timeout_cnt;
4349 __le32 drop_seq_cnt;
4350 __le32 fcoe_rx_drop_pkt_cnt;
4351 __le32 fcp_rx_pkt_cnt;
4352 __le32 reserved0;
4353};
4354
4355
4356
4357
4358
4359struct fcoe_tx_stat_params {
4360 __le32 fcoe_tx_pkt_cnt;
4361 __le32 fcoe_tx_byte_cnt;
4362 __le32 fcp_tx_pkt_cnt;
4363 __le32 reserved0;
4364};
4365
4366
4367
4368
4369struct fcoe_statistics_params {
4370 struct fcoe_tx_stat_params tx_stat;
4371 struct fcoe_rx_stat_params_section0 rx_stat0;
4372 struct fcoe_rx_stat_params_section1 rx_stat1;
4373 struct fcoe_rx_stat_params_section2 rx_stat2;
4374};
4375
4376
4377
4378
4379
4380struct cfc_del_event_data {
4381 u32 cid;
4382 u32 reserved0;
4383 u32 reserved1;
4384};
4385
4386
4387
4388
4389
4390struct cmng_flags_per_port {
4391 u32 cmng_enables;
4392#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4393#define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4394#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4395#define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4396#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4397#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4398#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4399#define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4400#define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4401#define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4402 u32 __reserved1;
4403};
4404
4405
4406
4407
4408
4409struct rate_shaping_vars_per_port {
4410 u32 rs_periodic_timeout;
4411 u32 rs_threshold;
4412};
4413
4414
4415
4416
4417struct fairness_vars_per_port {
4418 u32 upper_bound;
4419 u32 fair_threshold;
4420 u32 fairness_timeout;
4421 u32 reserved0;
4422};
4423
4424
4425
4426
4427struct safc_struct_per_port {
4428#if defined(__BIG_ENDIAN)
4429 u16 __reserved1;
4430 u8 __reserved0;
4431 u8 safc_timeout_usec;
4432#elif defined(__LITTLE_ENDIAN)
4433 u8 safc_timeout_usec;
4434 u8 __reserved0;
4435 u16 __reserved1;
4436#endif
4437 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4438 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4439};
4440
4441
4442
4443
4444struct cmng_struct_per_port {
4445 struct rate_shaping_vars_per_port rs_vars;
4446 struct fairness_vars_per_port fair_vars;
4447 struct safc_struct_per_port safc_vars;
4448 struct cmng_flags_per_port flags;
4449};
4450
4451
4452
4453
4454
4455enum common_spqe_cmd_id {
4456 RAMROD_CMD_ID_COMMON_UNUSED,
4457 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4458 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4459 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4460 RAMROD_CMD_ID_COMMON_CFC_DEL,
4461 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4462 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4463 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4464 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4465 RAMROD_CMD_ID_COMMON_RESERVED1,
4466 MAX_COMMON_SPQE_CMD_ID
4467};
4468
4469
4470
4471
4472
4473enum connection_type {
4474 ETH_CONNECTION_TYPE,
4475 TOE_CONNECTION_TYPE,
4476 RDMA_CONNECTION_TYPE,
4477 ISCSI_CONNECTION_TYPE,
4478 FCOE_CONNECTION_TYPE,
4479 RESERVED_CONNECTION_TYPE_0,
4480 RESERVED_CONNECTION_TYPE_1,
4481 RESERVED_CONNECTION_TYPE_2,
4482 NONE_CONNECTION_TYPE,
4483 MAX_CONNECTION_TYPE
4484};
4485
4486
4487
4488
4489
4490enum cos_mode {
4491 OVERRIDE_COS,
4492 STATIC_COS,
4493 FW_WRR,
4494 MAX_COS_MODE
4495};
4496
4497
4498
4499
4500
4501struct hc_dynamic_drv_counter {
4502 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4503};
4504
4505
4506
4507
4508struct cstorm_queue_zone_data {
4509 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4510 struct regpair reserved[2];
4511};
4512
4513
4514
4515
4516
4517struct vf_pf_channel_zone_data {
4518 u32 msg_addr_lo;
4519 u32 msg_addr_hi;
4520};
4521
4522
4523
4524
4525struct non_trigger_vf_zone {
4526 struct vf_pf_channel_zone_data vf_pf_channel;
4527};
4528
4529
4530
4531
4532struct vf_pf_channel_zone_trigger {
4533 u8 addr_valid;
4534};
4535
4536
4537
4538
4539struct trigger_vf_zone {
4540#if defined(__BIG_ENDIAN)
4541 u16 reserved1;
4542 u8 reserved0;
4543 struct vf_pf_channel_zone_trigger vf_pf_channel;
4544#elif defined(__LITTLE_ENDIAN)
4545 struct vf_pf_channel_zone_trigger vf_pf_channel;
4546 u8 reserved0;
4547 u16 reserved1;
4548#endif
4549 u32 reserved2;
4550};
4551
4552
4553
4554
4555struct cstorm_vf_zone_data {
4556 struct non_trigger_vf_zone non_trigger;
4557 struct trigger_vf_zone trigger;
4558};
4559
4560
4561
4562
4563
4564struct dynamic_hc_sm_config {
4565 u32 threshold[3];
4566 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4567 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4568 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4569 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4570 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4571};
4572
4573
4574
4575
4576struct dynamic_hc_config {
4577 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4578};
4579
4580
4581struct e2_integ_data {
4582#if defined(__BIG_ENDIAN)
4583 u8 flags;
4584#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4585#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4586#define E2_INTEG_DATA_LB_TX (0x1<<1)
4587#define E2_INTEG_DATA_LB_TX_SHIFT 1
4588#define E2_INTEG_DATA_COS_TX (0x1<<2)
4589#define E2_INTEG_DATA_COS_TX_SHIFT 2
4590#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4591#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4592#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4593#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4594#define E2_INTEG_DATA_RESERVED (0x7<<5)
4595#define E2_INTEG_DATA_RESERVED_SHIFT 5
4596 u8 cos;
4597 u8 voq;
4598 u8 pbf_queue;
4599#elif defined(__LITTLE_ENDIAN)
4600 u8 pbf_queue;
4601 u8 voq;
4602 u8 cos;
4603 u8 flags;
4604#define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4605#define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4606#define E2_INTEG_DATA_LB_TX (0x1<<1)
4607#define E2_INTEG_DATA_LB_TX_SHIFT 1
4608#define E2_INTEG_DATA_COS_TX (0x1<<2)
4609#define E2_INTEG_DATA_COS_TX_SHIFT 2
4610#define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4611#define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4612#define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4613#define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4614#define E2_INTEG_DATA_RESERVED (0x7<<5)
4615#define E2_INTEG_DATA_RESERVED_SHIFT 5
4616#endif
4617#if defined(__BIG_ENDIAN)
4618 u16 reserved3;
4619 u8 reserved2;
4620 u8 ramEn;
4621#elif defined(__LITTLE_ENDIAN)
4622 u8 ramEn;
4623 u8 reserved2;
4624 u16 reserved3;
4625#endif
4626};
4627
4628
4629
4630
4631
4632struct eth_event_data {
4633 u32 echo;
4634 u32 reserved0;
4635 u32 reserved1;
4636};
4637
4638
4639
4640
4641
4642struct vf_pf_event_data {
4643 u8 vf_id;
4644 u8 reserved0;
4645 u16 reserved1;
4646 u32 msg_addr_lo;
4647 u32 msg_addr_hi;
4648};
4649
4650
4651
4652
4653struct vf_flr_event_data {
4654 u8 vf_id;
4655 u8 reserved0;
4656 u16 reserved1;
4657 u32 reserved2;
4658 u32 reserved3;
4659};
4660
4661
4662
4663
4664struct malicious_vf_event_data {
4665 u8 vf_id;
4666 u8 reserved0;
4667 u16 reserved1;
4668 u32 reserved2;
4669 u32 reserved3;
4670};
4671
4672
4673
4674
4675union event_data {
4676 struct vf_pf_event_data vf_pf_event;
4677 struct eth_event_data eth_event;
4678 struct cfc_del_event_data cfc_del_event;
4679 struct vf_flr_event_data vf_flr_event;
4680 struct malicious_vf_event_data malicious_vf_event;
4681};
4682
4683
4684
4685
4686
4687struct event_ring_data {
4688 struct regpair base_addr;
4689#if defined(__BIG_ENDIAN)
4690 u8 index_id;
4691 u8 sb_id;
4692 u16 producer;
4693#elif defined(__LITTLE_ENDIAN)
4694 u16 producer;
4695 u8 sb_id;
4696 u8 index_id;
4697#endif
4698 u32 reserved0;
4699};
4700
4701
4702
4703
4704
4705struct event_ring_msg {
4706 u8 opcode;
4707 u8 error;
4708 u16 reserved1;
4709 union event_data data;
4710};
4711
4712
4713
4714
4715struct event_ring_next {
4716 struct regpair addr;
4717 u32 reserved[2];
4718};
4719
4720
4721
4722
4723union event_ring_elem {
4724 struct event_ring_msg message;
4725 struct event_ring_next next_page;
4726};
4727
4728
4729
4730
4731
4732enum event_ring_opcode {
4733 EVENT_RING_OPCODE_VF_PF_CHANNEL,
4734 EVENT_RING_OPCODE_FUNCTION_START,
4735 EVENT_RING_OPCODE_FUNCTION_STOP,
4736 EVENT_RING_OPCODE_CFC_DEL,
4737 EVENT_RING_OPCODE_CFC_DEL_WB,
4738 EVENT_RING_OPCODE_STAT_QUERY,
4739 EVENT_RING_OPCODE_STOP_TRAFFIC,
4740 EVENT_RING_OPCODE_START_TRAFFIC,
4741 EVENT_RING_OPCODE_VF_FLR,
4742 EVENT_RING_OPCODE_MALICIOUS_VF,
4743 EVENT_RING_OPCODE_FORWARD_SETUP,
4744 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
4745 EVENT_RING_OPCODE_FUNCTION_UPDATE,
4746 EVENT_RING_OPCODE_RESERVED1,
4747 EVENT_RING_OPCODE_SET_MAC,
4748 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
4749 EVENT_RING_OPCODE_FILTERS_RULES,
4750 EVENT_RING_OPCODE_MULTICAST_RULES,
4751 MAX_EVENT_RING_OPCODE
4752};
4753
4754
4755
4756
4757
4758enum fairness_mode {
4759 FAIRNESS_COS_WRR_MODE,
4760 FAIRNESS_COS_ETS_MODE,
4761 MAX_FAIRNESS_MODE
4762};
4763
4764
4765
4766
4767
4768struct fairness_vars_per_vn {
4769 u32 cos_credit_delta[MAX_COS_NUMBER];
4770 u32 vn_credit_delta;
4771 u32 __reserved0;
4772};
4773
4774
4775
4776
4777
4778struct priority_cos {
4779 u8 priority;
4780 u8 cos;
4781 __le16 reserved1;
4782};
4783
4784
4785
4786
4787struct flow_control_configuration {
4788 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
4789 u8 dcb_enabled;
4790 u8 dcb_version;
4791 u8 dont_add_pri_0_en;
4792 u8 reserved1;
4793 __le32 reserved2;
4794};
4795
4796
4797
4798
4799
4800struct function_start_data {
4801 __le16 function_mode;
4802 __le16 sd_vlan_tag;
4803 u16 reserved;
4804 u8 path_id;
4805 u8 network_cos_mode;
4806};
4807
4808
4809
4810
4811
4812struct fw_version {
4813#if defined(__BIG_ENDIAN)
4814 u8 engineering;
4815 u8 revision;
4816 u8 minor;
4817 u8 major;
4818#elif defined(__LITTLE_ENDIAN)
4819 u8 major;
4820 u8 minor;
4821 u8 revision;
4822 u8 engineering;
4823#endif
4824 u32 flags;
4825#define FW_VERSION_OPTIMIZED (0x1<<0)
4826#define FW_VERSION_OPTIMIZED_SHIFT 0
4827#define FW_VERSION_BIG_ENDIEN (0x1<<1)
4828#define FW_VERSION_BIG_ENDIEN_SHIFT 1
4829#define FW_VERSION_CHIP_VERSION (0x3<<2)
4830#define FW_VERSION_CHIP_VERSION_SHIFT 2
4831#define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
4832#define __FW_VERSION_RESERVED_SHIFT 4
4833};
4834
4835
4836
4837
4838
4839struct hc_dynamic_sb_drv_counters {
4840 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
4841};
4842
4843
4844
4845
4846
4847struct hc_index_data {
4848#if defined(__BIG_ENDIAN)
4849 u8 flags;
4850#define HC_INDEX_DATA_SM_ID (0x1<<0)
4851#define HC_INDEX_DATA_SM_ID_SHIFT 0
4852#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4853#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4854#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4855#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4856#define HC_INDEX_DATA_RESERVE (0x1F<<3)
4857#define HC_INDEX_DATA_RESERVE_SHIFT 3
4858 u8 timeout;
4859#elif defined(__LITTLE_ENDIAN)
4860 u8 timeout;
4861 u8 flags;
4862#define HC_INDEX_DATA_SM_ID (0x1<<0)
4863#define HC_INDEX_DATA_SM_ID_SHIFT 0
4864#define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4865#define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4866#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4867#define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4868#define HC_INDEX_DATA_RESERVE (0x1F<<3)
4869#define HC_INDEX_DATA_RESERVE_SHIFT 3
4870#endif
4871};
4872
4873
4874
4875
4876
4877struct hc_status_block_sm {
4878#if defined(__BIG_ENDIAN)
4879 u8 igu_seg_id;
4880 u8 igu_sb_id;
4881 u8 timer_value;
4882 u8 __flags;
4883#elif defined(__LITTLE_ENDIAN)
4884 u8 __flags;
4885 u8 timer_value;
4886 u8 igu_sb_id;
4887 u8 igu_seg_id;
4888#endif
4889 u32 time_to_expire;
4890};
4891
4892
4893
4894
4895struct pci_entity {
4896#if defined(__BIG_ENDIAN)
4897 u8 vf_valid;
4898 u8 vf_id;
4899 u8 vnic_id;
4900 u8 pf_id;
4901#elif defined(__LITTLE_ENDIAN)
4902 u8 pf_id;
4903 u8 vnic_id;
4904 u8 vf_id;
4905 u8 vf_valid;
4906#endif
4907};
4908
4909
4910
4911
4912struct hc_sb_data {
4913 struct regpair host_sb_addr;
4914 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
4915 struct pci_entity p_func;
4916#if defined(__BIG_ENDIAN)
4917 u8 rsrv0;
4918 u8 state;
4919 u8 dhc_qzone_id;
4920 u8 same_igu_sb_1b;
4921#elif defined(__LITTLE_ENDIAN)
4922 u8 same_igu_sb_1b;
4923 u8 dhc_qzone_id;
4924 u8 state;
4925 u8 rsrv0;
4926#endif
4927 struct regpair rsrv1[2];
4928};
4929
4930
4931
4932
4933
4934enum hc_segment {
4935 HC_REGULAR_SEGMENT,
4936 HC_DEFAULT_SEGMENT,
4937 MAX_HC_SEGMENT
4938};
4939
4940
4941
4942
4943
4944struct hc_sp_status_block_data {
4945 struct regpair host_sb_addr;
4946#if defined(__BIG_ENDIAN)
4947 u8 rsrv1;
4948 u8 state;
4949 u8 igu_seg_id;
4950 u8 igu_sb_id;
4951#elif defined(__LITTLE_ENDIAN)
4952 u8 igu_sb_id;
4953 u8 igu_seg_id;
4954 u8 state;
4955 u8 rsrv1;
4956#endif
4957 struct pci_entity p_func;
4958};
4959
4960
4961
4962
4963
4964struct hc_status_block_data_e1x {
4965 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
4966 struct hc_sb_data common;
4967};
4968
4969
4970
4971
4972
4973struct hc_status_block_data_e2 {
4974 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
4975 struct hc_sb_data common;
4976};
4977
4978
4979
4980
4981
4982enum igu_mode {
4983 HC_IGU_BC_MODE,
4984 HC_IGU_NBC_MODE,
4985 MAX_IGU_MODE
4986};
4987
4988
4989
4990
4991
4992enum ip_ver {
4993 IP_V4,
4994 IP_V6,
4995 MAX_IP_VER
4996};
4997
4998
4999
5000
5001
5002enum mf_mode {
5003 SINGLE_FUNCTION,
5004 MULTI_FUNCTION_SD,
5005 MULTI_FUNCTION_SI,
5006 MULTI_FUNCTION_RESERVED,
5007 MAX_MF_MODE
5008};
5009
5010
5011
5012
5013struct tstorm_per_pf_stats {
5014 struct regpair rcv_error_bytes;
5015};
5016
5017
5018
5019
5020struct per_pf_stats {
5021 struct tstorm_per_pf_stats tstorm_pf_statistics;
5022};
5023
5024
5025
5026
5027
5028struct tstorm_per_port_stats {
5029 __le32 mac_discard;
5030 __le32 mac_filter_discard;
5031 __le32 brb_truncate_discard;
5032 __le32 mf_tag_discard;
5033 __le32 packet_drop;
5034 __le32 reserved;
5035};
5036
5037
5038
5039
5040struct per_port_stats {
5041 struct tstorm_per_port_stats tstorm_port_statistics;
5042};
5043
5044
5045
5046
5047
5048struct tstorm_per_queue_stats {
5049 struct regpair rcv_ucast_bytes;
5050 __le32 rcv_ucast_pkts;
5051 __le32 checksum_discard;
5052 struct regpair rcv_bcast_bytes;
5053 __le32 rcv_bcast_pkts;
5054 __le32 pkts_too_big_discard;
5055 struct regpair rcv_mcast_bytes;
5056 __le32 rcv_mcast_pkts;
5057 __le32 ttl0_discard;
5058 __le16 no_buff_discard;
5059 __le16 reserved0;
5060 __le32 reserved1;
5061};
5062
5063
5064
5065
5066struct ustorm_per_queue_stats {
5067 struct regpair ucast_no_buff_bytes;
5068 struct regpair mcast_no_buff_bytes;
5069 struct regpair bcast_no_buff_bytes;
5070 __le32 ucast_no_buff_pkts;
5071 __le32 mcast_no_buff_pkts;
5072 __le32 bcast_no_buff_pkts;
5073 __le32 coalesced_pkts;
5074 struct regpair coalesced_bytes;
5075 __le32 coalesced_events;
5076 __le32 coalesced_aborts;
5077};
5078
5079
5080
5081
5082struct xstorm_per_queue_stats {
5083 struct regpair ucast_bytes_sent;
5084 struct regpair mcast_bytes_sent;
5085 struct regpair bcast_bytes_sent;
5086 __le32 ucast_pkts_sent;
5087 __le32 mcast_pkts_sent;
5088 __le32 bcast_pkts_sent;
5089 __le32 error_drop_pkts;
5090};
5091
5092
5093
5094
5095struct per_queue_stats {
5096 struct tstorm_per_queue_stats tstorm_queue_statistics;
5097 struct ustorm_per_queue_stats ustorm_queue_statistics;
5098 struct xstorm_per_queue_stats xstorm_queue_statistics;
5099};
5100
5101
5102
5103
5104
5105struct pram_fw_version {
5106 u8 major;
5107 u8 minor;
5108 u8 revision;
5109 u8 engineering;
5110 u8 flags;
5111#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5112#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5113#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5114#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5115#define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5116#define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5117#define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5118#define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5119#define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5120#define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5121};
5122
5123
5124
5125
5126
5127union protocol_common_specific_data {
5128 u8 protocol_data[8];
5129 struct regpair phy_address;
5130 struct regpair mac_config_addr;
5131};
5132
5133
5134
5135
5136struct protocol_common_spe {
5137 struct spe_hdr hdr;
5138 union protocol_common_specific_data data;
5139};
5140
5141
5142
5143
5144
5145struct rate_shaping_counter {
5146 u32 quota;
5147#if defined(__BIG_ENDIAN)
5148 u16 __reserved0;
5149 u16 rate;
5150#elif defined(__LITTLE_ENDIAN)
5151 u16 rate;
5152 u16 __reserved0;
5153#endif
5154};
5155
5156
5157
5158
5159
5160struct rate_shaping_vars_per_vn {
5161 struct rate_shaping_counter vn_counter;
5162};
5163
5164
5165
5166
5167
5168struct slow_path_element {
5169 struct spe_hdr hdr;
5170 struct regpair protocol_data;
5171};
5172
5173
5174
5175
5176
5177struct stats_counter {
5178 __le16 xstats_counter;
5179 __le16 reserved0;
5180 __le32 reserved1;
5181 __le16 tstats_counter;
5182 __le16 reserved2;
5183 __le32 reserved3;
5184 __le16 ustats_counter;
5185 __le16 reserved4;
5186 __le32 reserved5;
5187 __le16 cstats_counter;
5188 __le16 reserved6;
5189 __le32 reserved7;
5190};
5191
5192
5193
5194
5195
5196struct stats_query_entry {
5197 u8 kind;
5198 u8 index;
5199 __le16 funcID;
5200 __le32 reserved;
5201 struct regpair address;
5202};
5203
5204
5205
5206
5207struct stats_query_cmd_group {
5208 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5209};
5210
5211
5212
5213
5214
5215struct stats_query_header {
5216 u8 cmd_num;
5217 u8 reserved0;
5218 __le16 drv_stats_counter;
5219 __le32 reserved1;
5220 struct regpair stats_counters_addrs;
5221};
5222
5223
5224
5225
5226
5227enum stats_query_type {
5228 STATS_TYPE_QUEUE,
5229 STATS_TYPE_PORT,
5230 STATS_TYPE_PF,
5231 STATS_TYPE_TOE,
5232 STATS_TYPE_FCOE,
5233 MAX_STATS_QUERY_TYPE
5234};
5235
5236
5237
5238
5239
5240enum status_block_state {
5241 SB_DISABLED,
5242 SB_ENABLED,
5243 SB_CLEANED,
5244 MAX_STATUS_BLOCK_STATE
5245};
5246
5247
5248
5249
5250
5251enum storm_id {
5252 USTORM_ID,
5253 CSTORM_ID,
5254 XSTORM_ID,
5255 TSTORM_ID,
5256 ATTENTION_ID,
5257 MAX_STORM_ID
5258};
5259
5260
5261
5262
5263
5264enum traffic_type {
5265 LLFC_TRAFFIC_TYPE_NW,
5266 LLFC_TRAFFIC_TYPE_FCOE,
5267 LLFC_TRAFFIC_TYPE_ISCSI,
5268 MAX_TRAFFIC_TYPE
5269};
5270
5271
5272
5273
5274
5275struct tstorm_queue_zone_data {
5276 struct regpair reserved[4];
5277};
5278
5279
5280
5281
5282
5283struct tstorm_vf_zone_data {
5284 struct regpair reserved;
5285};
5286
5287
5288
5289
5290
5291struct ustorm_queue_zone_data {
5292 struct ustorm_eth_rx_producers eth_rx_producers;
5293 struct regpair reserved[3];
5294};
5295
5296
5297
5298
5299
5300struct ustorm_vf_zone_data {
5301 struct regpair reserved;
5302};
5303
5304
5305
5306
5307
5308struct vf_pf_channel_data {
5309#if defined(__BIG_ENDIAN)
5310 u16 reserved0;
5311 u8 valid;
5312 u8 state;
5313#elif defined(__LITTLE_ENDIAN)
5314 u8 state;
5315 u8 valid;
5316 u16 reserved0;
5317#endif
5318 u32 reserved1;
5319};
5320
5321
5322
5323
5324
5325enum vf_pf_channel_state {
5326 VF_PF_CHANNEL_STATE_READY,
5327 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5328 MAX_VF_PF_CHANNEL_STATE
5329};
5330
5331
5332
5333
5334
5335struct xstorm_queue_zone_data {
5336 struct regpair reserved[4];
5337};
5338
5339
5340
5341
5342
5343struct xstorm_vf_zone_data {
5344 struct regpair reserved;
5345};
5346
5347#endif
5348