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10#ifndef _T3_H
11#define _T3_H
12
13#define TG3_64BIT_REG_HIGH 0x00UL
14#define TG3_64BIT_REG_LOW 0x04UL
15
16
17#define TG3_BDINFO_HOST_ADDR 0x0UL
18#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL
19#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001
20#define BDINFO_FLAGS_DISABLED 0x00000002
21#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
22#define BDINFO_FLAGS_MAXLEN_SHIFT 16
23#define TG3_BDINFO_NIC_ADDR 0xcUL
24#define TG3_BDINFO_SIZE 0x10UL
25
26#define TG3_RX_STD_MAX_SIZE_5700 512
27#define TG3_RX_STD_MAX_SIZE_5717 2048
28#define TG3_RX_JMB_MAX_SIZE_5700 256
29#define TG3_RX_JMB_MAX_SIZE_5717 1024
30#define TG3_RX_RET_MAX_SIZE_5700 1024
31#define TG3_RX_RET_MAX_SIZE_5705 512
32#define TG3_RX_RET_MAX_SIZE_5717 4096
33
34#define TG3_RSS_INDIR_TBL_SIZE 128
35
36
37#define TG3PCI_VENDOR 0x00000000
38#define TG3PCI_VENDOR_BROADCOM 0x14e4
39#define TG3PCI_DEVICE 0x00000002
40#define TG3PCI_DEVICE_TIGON3_1 0x1644
41#define TG3PCI_DEVICE_TIGON3_2 0x1645
42#define TG3PCI_DEVICE_TIGON3_3 0x1646
43#define TG3PCI_DEVICE_TIGON3_4 0x1647
44#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
45#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
46#define TG3PCI_DEVICE_TIGON3_57780 0x1692
47#define TG3PCI_DEVICE_TIGON3_57760 0x1690
48#define TG3PCI_DEVICE_TIGON3_57790 0x1694
49#define TG3PCI_DEVICE_TIGON3_57788 0x1691
50#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699
51#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0
52#define TG3PCI_DEVICE_TIGON3_5717 0x1655
53#define TG3PCI_DEVICE_TIGON3_5718 0x1656
54#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
55#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
56#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
57#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
58#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
59#define TG3PCI_DEVICE_TIGON3_57795 0x16b6
60#define TG3PCI_DEVICE_TIGON3_5719 0x1657
61#define TG3PCI_DEVICE_TIGON3_5720 0x165f
62#define TG3PCI_DEVICE_TIGON3_57762 0x1682
63#define TG3PCI_DEVICE_TIGON3_57766 0x1686
64#define TG3PCI_DEVICE_TIGON3_57786 0x16b3
65#define TG3PCI_DEVICE_TIGON3_57782 0x16b7
66
67#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
68#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
69#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
70#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
71#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
72#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
73#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
74#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
75#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
76#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
77#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
78#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
79#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
80#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
81#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
82#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
83#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
84#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
85#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
86#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
87#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
88#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
89#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
90#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
91#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
92#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
93#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
94#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
95#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
96#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
97#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
98
99#define TG3PCI_MSI_DATA 0x00000064
100
101#define TG3PCI_MISC_HOST_CTRL 0x00000068
102#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
103#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
104#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
105#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
106#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
107#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
108#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
109#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
110#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
111#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
112#define MISC_HOST_CTRL_CHIPREV 0xffff0000
113#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
114#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
115 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
116 MISC_HOST_CTRL_CHIPREV_SHIFT)
117#define CHIPREV_ID_5700_A0 0x7000
118#define CHIPREV_ID_5700_A1 0x7001
119#define CHIPREV_ID_5700_B0 0x7100
120#define CHIPREV_ID_5700_B1 0x7101
121#define CHIPREV_ID_5700_B3 0x7102
122#define CHIPREV_ID_5700_ALTIMA 0x7104
123#define CHIPREV_ID_5700_C0 0x7200
124#define CHIPREV_ID_5701_A0 0x0000
125#define CHIPREV_ID_5701_B0 0x0100
126#define CHIPREV_ID_5701_B2 0x0102
127#define CHIPREV_ID_5701_B5 0x0105
128#define CHIPREV_ID_5703_A0 0x1000
129#define CHIPREV_ID_5703_A1 0x1001
130#define CHIPREV_ID_5703_A2 0x1002
131#define CHIPREV_ID_5703_A3 0x1003
132#define CHIPREV_ID_5704_A0 0x2000
133#define CHIPREV_ID_5704_A1 0x2001
134#define CHIPREV_ID_5704_A2 0x2002
135#define CHIPREV_ID_5704_A3 0x2003
136#define CHIPREV_ID_5705_A0 0x3000
137#define CHIPREV_ID_5705_A1 0x3001
138#define CHIPREV_ID_5705_A2 0x3002
139#define CHIPREV_ID_5705_A3 0x3003
140#define CHIPREV_ID_5750_A0 0x4000
141#define CHIPREV_ID_5750_A1 0x4001
142#define CHIPREV_ID_5750_A3 0x4003
143#define CHIPREV_ID_5750_C2 0x4202
144#define CHIPREV_ID_5752_A0_HW 0x5000
145#define CHIPREV_ID_5752_A0 0x6000
146#define CHIPREV_ID_5752_A1 0x6001
147#define CHIPREV_ID_5714_A2 0x9002
148#define CHIPREV_ID_5906_A1 0xc001
149#define CHIPREV_ID_57780_A0 0x57780000
150#define CHIPREV_ID_57780_A1 0x57780001
151#define CHIPREV_ID_5717_A0 0x05717000
152#define CHIPREV_ID_57765_A0 0x57785000
153#define CHIPREV_ID_5719_A0 0x05719000
154#define CHIPREV_ID_5720_A0 0x05720000
155#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
156#define ASIC_REV_5700 0x07
157#define ASIC_REV_5701 0x00
158#define ASIC_REV_5703 0x01
159#define ASIC_REV_5704 0x02
160#define ASIC_REV_5705 0x03
161#define ASIC_REV_5750 0x04
162#define ASIC_REV_5752 0x06
163#define ASIC_REV_5780 0x08
164#define ASIC_REV_5714 0x09
165#define ASIC_REV_5755 0x0a
166#define ASIC_REV_5787 0x0b
167#define ASIC_REV_5906 0x0c
168#define ASIC_REV_USE_PROD_ID_REG 0x0f
169#define ASIC_REV_5784 0x5784
170#define ASIC_REV_5761 0x5761
171#define ASIC_REV_5785 0x5785
172#define ASIC_REV_57780 0x57780
173#define ASIC_REV_5717 0x5717
174#define ASIC_REV_57765 0x57785
175#define ASIC_REV_5719 0x5719
176#define ASIC_REV_5720 0x5720
177#define ASIC_REV_57766 0x57766
178#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
179#define CHIPREV_5700_AX 0x70
180#define CHIPREV_5700_BX 0x71
181#define CHIPREV_5700_CX 0x72
182#define CHIPREV_5701_AX 0x00
183#define CHIPREV_5703_AX 0x10
184#define CHIPREV_5704_AX 0x20
185#define CHIPREV_5704_BX 0x21
186#define CHIPREV_5750_AX 0x40
187#define CHIPREV_5750_BX 0x41
188#define CHIPREV_5784_AX 0x57840
189#define CHIPREV_5761_AX 0x57610
190#define CHIPREV_57765_AX 0x577650
191#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
192#define METAL_REV_A0 0x00
193#define METAL_REV_A1 0x01
194#define METAL_REV_B0 0x00
195#define METAL_REV_B1 0x01
196#define METAL_REV_B2 0x02
197#define TG3PCI_DMA_RW_CTRL 0x0000006c
198#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
199#define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
200#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
201#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
202#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
203#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
204#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
205#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
206#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
207#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
208#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
209#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
210#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
211#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
212#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
213#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
214#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
215#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
216#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
217#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
218#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
219#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
220#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
221#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
222#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
223#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
224#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
225#define DMA_RWCTRL_ONE_DMA 0x00004000
226#define DMA_RWCTRL_READ_WATER 0x00070000
227#define DMA_RWCTRL_READ_WATER_SHIFT 16
228#define DMA_RWCTRL_WRITE_WATER 0x00380000
229#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
230#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
231#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
232#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
233#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
234#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
235#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
236#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
237#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
238#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
239#define TG3PCI_PCISTATE 0x00000070
240#define PCISTATE_FORCE_RESET 0x00000001
241#define PCISTATE_INT_NOT_ACTIVE 0x00000002
242#define PCISTATE_CONV_PCI_MODE 0x00000004
243#define PCISTATE_BUS_SPEED_HIGH 0x00000008
244#define PCISTATE_BUS_32BIT 0x00000010
245#define PCISTATE_ROM_ENABLE 0x00000020
246#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
247#define PCISTATE_FLAT_VIEW 0x00000100
248#define PCISTATE_RETRY_SAME_DMA 0x00002000
249#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
250#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
251#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
252#define TG3PCI_CLOCK_CTRL 0x00000074
253#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
254#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
255#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
256#define CLOCK_CTRL_ALTCLK 0x00001000
257#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
258#define CLOCK_CTRL_44MHZ_CORE 0x00040000
259#define CLOCK_CTRL_625_CORE 0x00100000
260#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
261#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
262#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
263#define TG3PCI_REG_BASE_ADDR 0x00000078
264#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
265#define TG3PCI_REG_DATA 0x00000080
266#define TG3PCI_MEM_WIN_DATA 0x00000084
267#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
268
269#define TG3PCI_STD_RING_PROD_IDX 0x00000098
270#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0
271
272#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
273#define DUAL_MAC_CTRL_CH_MASK 0x00000003
274#define DUAL_MAC_CTRL_ID 0x00000004
275#define TG3PCI_PRODID_ASICREV 0x000000bc
276#define PROD_ID_ASIC_REV_MASK 0x0fffffff
277
278
279#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
280#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
281
282
283#define TG3_CORR_ERR_STAT 0x00000110
284#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
285
286
287
288#define MAILBOX_INTERRUPT_0 0x00000200
289#define MAILBOX_INTERRUPT_1 0x00000208
290#define MAILBOX_INTERRUPT_2 0x00000210
291#define MAILBOX_INTERRUPT_3 0x00000218
292#define MAILBOX_GENERAL_0 0x00000220
293#define MAILBOX_GENERAL_1 0x00000228
294#define MAILBOX_GENERAL_2 0x00000230
295#define MAILBOX_GENERAL_3 0x00000238
296#define MAILBOX_GENERAL_4 0x00000240
297#define MAILBOX_GENERAL_5 0x00000248
298#define MAILBOX_GENERAL_6 0x00000250
299#define MAILBOX_GENERAL_7 0x00000258
300#define MAILBOX_RELOAD_STAT 0x00000260
301#define MAILBOX_RCV_STD_PROD_IDX 0x00000268
302#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
303 TG3_64BIT_REG_LOW)
304#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270
305#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
306 TG3_64BIT_REG_LOW)
307#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278
308#define MAILBOX_RCVRET_CON_IDX_0 0x00000280
309#define MAILBOX_RCVRET_CON_IDX_1 0x00000288
310#define MAILBOX_RCVRET_CON_IDX_2 0x00000290
311#define MAILBOX_RCVRET_CON_IDX_3 0x00000298
312#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0
313#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8
314#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0
315#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8
316#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0
317#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8
318#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0
319#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8
320#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0
321#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8
322#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0
323#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8
324#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300
325#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308
326#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310
327#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318
328#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320
329#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328
330#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330
331#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338
332#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340
333#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348
334#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350
335#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358
336#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360
337#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368
338#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370
339#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378
340#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380
341#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388
342#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390
343#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398
344#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0
345#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8
346#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0
347#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8
348#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0
349#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8
350#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0
351#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8
352#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0
353#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8
354#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0
355#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8
356
357
358#define MAC_MODE 0x00000400
359#define MAC_MODE_RESET 0x00000001
360#define MAC_MODE_HALF_DUPLEX 0x00000002
361#define MAC_MODE_PORT_MODE_MASK 0x0000000c
362#define MAC_MODE_PORT_MODE_TBI 0x0000000c
363#define MAC_MODE_PORT_MODE_GMII 0x00000008
364#define MAC_MODE_PORT_MODE_MII 0x00000004
365#define MAC_MODE_PORT_MODE_NONE 0x00000000
366#define MAC_MODE_PORT_INT_LPBACK 0x00000010
367#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
368#define MAC_MODE_TX_BURSTING 0x00000100
369#define MAC_MODE_MAX_DEFER 0x00000200
370#define MAC_MODE_LINK_POLARITY 0x00000400
371#define MAC_MODE_RXSTAT_ENABLE 0x00000800
372#define MAC_MODE_RXSTAT_CLEAR 0x00001000
373#define MAC_MODE_RXSTAT_FLUSH 0x00002000
374#define MAC_MODE_TXSTAT_ENABLE 0x00004000
375#define MAC_MODE_TXSTAT_CLEAR 0x00008000
376#define MAC_MODE_TXSTAT_FLUSH 0x00010000
377#define MAC_MODE_SEND_CONFIGS 0x00020000
378#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
379#define MAC_MODE_ACPI_ENABLE 0x00080000
380#define MAC_MODE_MIP_ENABLE 0x00100000
381#define MAC_MODE_TDE_ENABLE 0x00200000
382#define MAC_MODE_RDE_ENABLE 0x00400000
383#define MAC_MODE_FHDE_ENABLE 0x00800000
384#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
385#define MAC_MODE_APE_RX_EN 0x08000000
386#define MAC_MODE_APE_TX_EN 0x10000000
387#define MAC_STATUS 0x00000404
388#define MAC_STATUS_PCS_SYNCED 0x00000001
389#define MAC_STATUS_SIGNAL_DET 0x00000002
390#define MAC_STATUS_RCVD_CFG 0x00000004
391#define MAC_STATUS_CFG_CHANGED 0x00000008
392#define MAC_STATUS_SYNC_CHANGED 0x00000010
393#define MAC_STATUS_PORT_DEC_ERR 0x00000400
394#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
395#define MAC_STATUS_MI_COMPLETION 0x00400000
396#define MAC_STATUS_MI_INTERRUPT 0x00800000
397#define MAC_STATUS_AP_ERROR 0x01000000
398#define MAC_STATUS_ODI_ERROR 0x02000000
399#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
400#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
401#define MAC_EVENT 0x00000408
402#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
403#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
404#define MAC_EVENT_MI_COMPLETION 0x00400000
405#define MAC_EVENT_MI_INTERRUPT 0x00800000
406#define MAC_EVENT_AP_ERROR 0x01000000
407#define MAC_EVENT_ODI_ERROR 0x02000000
408#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
409#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
410#define MAC_LED_CTRL 0x0000040c
411#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
412#define LED_CTRL_1000MBPS_ON 0x00000002
413#define LED_CTRL_100MBPS_ON 0x00000004
414#define LED_CTRL_10MBPS_ON 0x00000008
415#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
416#define LED_CTRL_TRAFFIC_BLINK 0x00000020
417#define LED_CTRL_TRAFFIC_LED 0x00000040
418#define LED_CTRL_1000MBPS_STATUS 0x00000080
419#define LED_CTRL_100MBPS_STATUS 0x00000100
420#define LED_CTRL_10MBPS_STATUS 0x00000200
421#define LED_CTRL_TRAFFIC_STATUS 0x00000400
422#define LED_CTRL_MODE_MAC 0x00000000
423#define LED_CTRL_MODE_PHY_1 0x00000800
424#define LED_CTRL_MODE_PHY_2 0x00001000
425#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
426#define LED_CTRL_MODE_SHARED 0x00004000
427#define LED_CTRL_MODE_COMBO 0x00008000
428#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
429#define LED_CTRL_BLINK_RATE_SHIFT 19
430#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
431#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
432#define MAC_ADDR_0_HIGH 0x00000410
433#define MAC_ADDR_0_LOW 0x00000414
434#define MAC_ADDR_1_HIGH 0x00000418
435#define MAC_ADDR_1_LOW 0x0000041c
436#define MAC_ADDR_2_HIGH 0x00000420
437#define MAC_ADDR_2_LOW 0x00000424
438#define MAC_ADDR_3_HIGH 0x00000428
439#define MAC_ADDR_3_LOW 0x0000042c
440#define MAC_ACPI_MBUF_PTR 0x00000430
441#define MAC_ACPI_LEN_OFFSET 0x00000434
442#define ACPI_LENOFF_LEN_MASK 0x0000ffff
443#define ACPI_LENOFF_LEN_SHIFT 0
444#define ACPI_LENOFF_OFF_MASK 0x0fff0000
445#define ACPI_LENOFF_OFF_SHIFT 16
446#define MAC_TX_BACKOFF_SEED 0x00000438
447#define TX_BACKOFF_SEED_MASK 0x000003ff
448#define MAC_RX_MTU_SIZE 0x0000043c
449#define RX_MTU_SIZE_MASK 0x0000ffff
450#define MAC_PCS_TEST 0x00000440
451#define PCS_TEST_PATTERN_MASK 0x000fffff
452#define PCS_TEST_PATTERN_SHIFT 0
453#define PCS_TEST_ENABLE 0x00100000
454#define MAC_TX_AUTO_NEG 0x00000444
455#define TX_AUTO_NEG_MASK 0x0000ffff
456#define TX_AUTO_NEG_SHIFT 0
457#define MAC_RX_AUTO_NEG 0x00000448
458#define RX_AUTO_NEG_MASK 0x0000ffff
459#define RX_AUTO_NEG_SHIFT 0
460#define MAC_MI_COM 0x0000044c
461#define MI_COM_CMD_MASK 0x0c000000
462#define MI_COM_CMD_WRITE 0x04000000
463#define MI_COM_CMD_READ 0x08000000
464#define MI_COM_READ_FAILED 0x10000000
465#define MI_COM_START 0x20000000
466#define MI_COM_BUSY 0x20000000
467#define MI_COM_PHY_ADDR_MASK 0x03e00000
468#define MI_COM_PHY_ADDR_SHIFT 21
469#define MI_COM_REG_ADDR_MASK 0x001f0000
470#define MI_COM_REG_ADDR_SHIFT 16
471#define MI_COM_DATA_MASK 0x0000ffff
472#define MAC_MI_STAT 0x00000450
473#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
474#define MAC_MI_STAT_10MBPS_MODE 0x00000002
475#define MAC_MI_MODE 0x00000454
476#define MAC_MI_MODE_CLK_10MHZ 0x00000001
477#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
478#define MAC_MI_MODE_AUTO_POLL 0x00000010
479#define MAC_MI_MODE_500KHZ_CONST 0x00008000
480#define MAC_MI_MODE_BASE 0x000c0000
481#define MAC_AUTO_POLL_STATUS 0x00000458
482#define MAC_AUTO_POLL_ERROR 0x00000001
483#define MAC_TX_MODE 0x0000045c
484#define TX_MODE_RESET 0x00000001
485#define TX_MODE_ENABLE 0x00000002
486#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
487#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
488#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
489#define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
490#define TX_MODE_JMB_FRM_LEN 0x00400000
491#define TX_MODE_CNT_DN_MODE 0x00800000
492#define MAC_TX_STATUS 0x00000460
493#define TX_STATUS_XOFFED 0x00000001
494#define TX_STATUS_SENT_XOFF 0x00000002
495#define TX_STATUS_SENT_XON 0x00000004
496#define TX_STATUS_LINK_UP 0x00000008
497#define TX_STATUS_ODI_UNDERRUN 0x00000010
498#define TX_STATUS_ODI_OVERRUN 0x00000020
499#define MAC_TX_LENGTHS 0x00000464
500#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
501#define TX_LENGTHS_SLOT_TIME_SHIFT 0
502#define TX_LENGTHS_IPG_MASK 0x00000f00
503#define TX_LENGTHS_IPG_SHIFT 8
504#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
505#define TX_LENGTHS_IPG_CRS_SHIFT 12
506#define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
507#define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
508#define MAC_RX_MODE 0x00000468
509#define RX_MODE_RESET 0x00000001
510#define RX_MODE_ENABLE 0x00000002
511#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
512#define RX_MODE_KEEP_MAC_CTRL 0x00000008
513#define RX_MODE_KEEP_PAUSE 0x00000010
514#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
515#define RX_MODE_ACCEPT_RUNTS 0x00000040
516#define RX_MODE_LEN_CHECK 0x00000080
517#define RX_MODE_PROMISC 0x00000100
518#define RX_MODE_NO_CRC_CHECK 0x00000200
519#define RX_MODE_KEEP_VLAN_TAG 0x00000400
520#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
521#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
522#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
523#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
524#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
525#define RX_MODE_RSS_ENABLE 0x00800000
526#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
527#define MAC_RX_STATUS 0x0000046c
528#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
529#define RX_STATUS_XOFF_RCVD 0x00000002
530#define RX_STATUS_XON_RCVD 0x00000004
531#define MAC_HASH_REG_0 0x00000470
532#define MAC_HASH_REG_1 0x00000474
533#define MAC_HASH_REG_2 0x00000478
534#define MAC_HASH_REG_3 0x0000047c
535#define MAC_RCV_RULE_0 0x00000480
536#define MAC_RCV_VALUE_0 0x00000484
537#define MAC_RCV_RULE_1 0x00000488
538#define MAC_RCV_VALUE_1 0x0000048c
539#define MAC_RCV_RULE_2 0x00000490
540#define MAC_RCV_VALUE_2 0x00000494
541#define MAC_RCV_RULE_3 0x00000498
542#define MAC_RCV_VALUE_3 0x0000049c
543#define MAC_RCV_RULE_4 0x000004a0
544#define MAC_RCV_VALUE_4 0x000004a4
545#define MAC_RCV_RULE_5 0x000004a8
546#define MAC_RCV_VALUE_5 0x000004ac
547#define MAC_RCV_RULE_6 0x000004b0
548#define MAC_RCV_VALUE_6 0x000004b4
549#define MAC_RCV_RULE_7 0x000004b8
550#define MAC_RCV_VALUE_7 0x000004bc
551#define MAC_RCV_RULE_8 0x000004c0
552#define MAC_RCV_VALUE_8 0x000004c4
553#define MAC_RCV_RULE_9 0x000004c8
554#define MAC_RCV_VALUE_9 0x000004cc
555#define MAC_RCV_RULE_10 0x000004d0
556#define MAC_RCV_VALUE_10 0x000004d4
557#define MAC_RCV_RULE_11 0x000004d8
558#define MAC_RCV_VALUE_11 0x000004dc
559#define MAC_RCV_RULE_12 0x000004e0
560#define MAC_RCV_VALUE_12 0x000004e4
561#define MAC_RCV_RULE_13 0x000004e8
562#define MAC_RCV_VALUE_13 0x000004ec
563#define MAC_RCV_RULE_14 0x000004f0
564#define MAC_RCV_VALUE_14 0x000004f4
565#define MAC_RCV_RULE_15 0x000004f8
566#define MAC_RCV_VALUE_15 0x000004fc
567#define RCV_RULE_DISABLE_MASK 0x7fffffff
568#define MAC_RCV_RULE_CFG 0x00000500
569#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
570#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
571
572#define MAC_HASHREGU_0 0x00000520
573#define MAC_HASHREGU_1 0x00000524
574#define MAC_HASHREGU_2 0x00000528
575#define MAC_HASHREGU_3 0x0000052c
576#define MAC_EXTADDR_0_HIGH 0x00000530
577#define MAC_EXTADDR_0_LOW 0x00000534
578#define MAC_EXTADDR_1_HIGH 0x00000538
579#define MAC_EXTADDR_1_LOW 0x0000053c
580#define MAC_EXTADDR_2_HIGH 0x00000540
581#define MAC_EXTADDR_2_LOW 0x00000544
582#define MAC_EXTADDR_3_HIGH 0x00000548
583#define MAC_EXTADDR_3_LOW 0x0000054c
584#define MAC_EXTADDR_4_HIGH 0x00000550
585#define MAC_EXTADDR_4_LOW 0x00000554
586#define MAC_EXTADDR_5_HIGH 0x00000558
587#define MAC_EXTADDR_5_LOW 0x0000055c
588#define MAC_EXTADDR_6_HIGH 0x00000560
589#define MAC_EXTADDR_6_LOW 0x00000564
590#define MAC_EXTADDR_7_HIGH 0x00000568
591#define MAC_EXTADDR_7_LOW 0x0000056c
592#define MAC_EXTADDR_8_HIGH 0x00000570
593#define MAC_EXTADDR_8_LOW 0x00000574
594#define MAC_EXTADDR_9_HIGH 0x00000578
595#define MAC_EXTADDR_9_LOW 0x0000057c
596#define MAC_EXTADDR_10_HIGH 0x00000580
597#define MAC_EXTADDR_10_LOW 0x00000584
598#define MAC_EXTADDR_11_HIGH 0x00000588
599#define MAC_EXTADDR_11_LOW 0x0000058c
600#define MAC_SERDES_CFG 0x00000590
601#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
602#define MAC_SERDES_STAT 0x00000594
603
604#define MAC_PHYCFG1 0x000005a0
605#define MAC_PHYCFG1_RGMII_INT 0x00000001
606#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
607#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
608#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
609#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
610#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
611#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
612#define MAC_PHYCFG1_TXC_DRV 0x20000000
613#define MAC_PHYCFG2 0x000005a4
614#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
615#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
616#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
617#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
618#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
619#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
620#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
621#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
622#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
623#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
624#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
625#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
626#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
627#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
628#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
629#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
630#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
631#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
632#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
633#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
634#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
635#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
636#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
637#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
638#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
639#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
640#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
641#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
642#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
643#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
644#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
645#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
646#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
647#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
648#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
649#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
650#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
651#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
652#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
653#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
654#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
655#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
656#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
657#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
658#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
659#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
660#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
661#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
662#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
663#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
664#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
665#define MAC_PHYCFG2_50610_LED_MODES \
666 (MAC_PHYCFG2_EMODE_MASK_50610 | \
667 MAC_PHYCFG2_EMODE_COMP_50610 | \
668 MAC_PHYCFG2_FMODE_MASK_50610 | \
669 MAC_PHYCFG2_FMODE_COMP_50610 | \
670 MAC_PHYCFG2_GMODE_MASK_50610 | \
671 MAC_PHYCFG2_GMODE_COMP_50610 | \
672 MAC_PHYCFG2_ACT_MASK_50610 | \
673 MAC_PHYCFG2_ACT_COMP_50610 | \
674 MAC_PHYCFG2_QUAL_MASK_50610 | \
675 MAC_PHYCFG2_QUAL_COMP_50610)
676#define MAC_PHYCFG2_AC131_LED_MODES \
677 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
678 MAC_PHYCFG2_EMODE_COMP_AC131 | \
679 MAC_PHYCFG2_FMODE_MASK_AC131 | \
680 MAC_PHYCFG2_FMODE_COMP_AC131 | \
681 MAC_PHYCFG2_GMODE_MASK_AC131 | \
682 MAC_PHYCFG2_GMODE_COMP_AC131 | \
683 MAC_PHYCFG2_ACT_MASK_AC131 | \
684 MAC_PHYCFG2_ACT_COMP_AC131 | \
685 MAC_PHYCFG2_QUAL_MASK_AC131 | \
686 MAC_PHYCFG2_QUAL_COMP_AC131)
687#define MAC_PHYCFG2_RTL8211C_LED_MODES \
688 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
689 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
690 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
691 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
692 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
693 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
694 MAC_PHYCFG2_ACT_MASK_RT8211 | \
695 MAC_PHYCFG2_ACT_COMP_RT8211 | \
696 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
697 MAC_PHYCFG2_QUAL_COMP_RT8211)
698#define MAC_PHYCFG2_RTL8201E_LED_MODES \
699 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
700 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
701 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
702 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
703 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
704 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
705 MAC_PHYCFG2_ACT_MASK_RT8201 | \
706 MAC_PHYCFG2_ACT_COMP_RT8201 | \
707 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
708 MAC_PHYCFG2_QUAL_COMP_RT8201)
709#define MAC_EXT_RGMII_MODE 0x000005a8
710#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
711#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
712#define MAC_RGMII_MODE_TX_RESET 0x00000004
713#define MAC_RGMII_MODE_RX_INT_B 0x00000100
714#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
715#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
716#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
717
718#define SERDES_RX_CTRL 0x000005b0
719#define SERDES_RX_SIG_DETECT 0x00000400
720#define SG_DIG_CTRL 0x000005b0
721#define SG_DIG_USING_HW_AUTONEG 0x80000000
722#define SG_DIG_SOFT_RESET 0x40000000
723#define SG_DIG_DISABLE_LINKRDY 0x20000000
724#define SG_DIG_CRC16_CLEAR_N 0x01000000
725#define SG_DIG_EN10B 0x00800000
726#define SG_DIG_CLEAR_STATUS 0x00400000
727#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
728#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
729#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
730#define SG_DIG_SPEED_STATUS_SHIFT 18
731#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
732#define SG_DIG_RESTART_AUTONEG 0x00010000
733#define SG_DIG_FIBER_MODE 0x00008000
734#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
735#define SG_DIG_PAUSE_MASK 0x00001800
736#define SG_DIG_PAUSE_CAP 0x00000800
737#define SG_DIG_ASYM_PAUSE 0x00001000
738#define SG_DIG_GBIC_ENABLE 0x00000400
739#define SG_DIG_CHECK_END_ENABLE 0x00000200
740#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
741#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
742#define SG_DIG_GMII_INPUT_SELECT 0x00000040
743#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
744#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
745#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
746#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
747#define SG_DIG_REMOTE_LOOPBACK 0x00000002
748#define SG_DIG_LOOPBACK 0x00000001
749#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
750 SG_DIG_LOCAL_DUPLEX_STATUS | \
751 SG_DIG_LOCAL_LINK_STATUS | \
752 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
753 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
754#define SG_DIG_STATUS 0x000005b4
755#define SG_DIG_CRC16_BUS_MASK 0xffff0000
756#define SG_DIG_PARTNER_FAULT_MASK 0x00600000
757#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000
758#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000
759#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000
760#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000
761#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000
762#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
763#define SG_DIG_IS_SERDES 0x00000100
764#define SG_DIG_COMMA_DETECTOR 0x00000008
765#define SG_DIG_MAC_ACK_STATUS 0x00000004
766#define SG_DIG_AUTONEG_COMPLETE 0x00000002
767#define SG_DIG_AUTONEG_ERROR 0x00000001
768
769#define MAC_TX_MAC_STATE_BASE 0x00000600
770#define MAC_RX_MAC_STATE_BASE 0x00000610
771
772
773#define MAC_RSS_INDIR_TBL_0 0x00000630
774
775#define MAC_RSS_HASH_KEY_0 0x00000670
776#define MAC_RSS_HASH_KEY_1 0x00000674
777#define MAC_RSS_HASH_KEY_2 0x00000678
778#define MAC_RSS_HASH_KEY_3 0x0000067c
779#define MAC_RSS_HASH_KEY_4 0x00000680
780#define MAC_RSS_HASH_KEY_5 0x00000684
781#define MAC_RSS_HASH_KEY_6 0x00000688
782#define MAC_RSS_HASH_KEY_7 0x0000068c
783#define MAC_RSS_HASH_KEY_8 0x00000690
784#define MAC_RSS_HASH_KEY_9 0x00000694
785
786
787#define MAC_TX_STATS_OCTETS 0x00000800
788#define MAC_TX_STATS_RESV1 0x00000804
789#define MAC_TX_STATS_COLLISIONS 0x00000808
790#define MAC_TX_STATS_XON_SENT 0x0000080c
791#define MAC_TX_STATS_XOFF_SENT 0x00000810
792#define MAC_TX_STATS_RESV2 0x00000814
793#define MAC_TX_STATS_MAC_ERRORS 0x00000818
794#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
795#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
796#define MAC_TX_STATS_DEFERRED 0x00000824
797#define MAC_TX_STATS_RESV3 0x00000828
798#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
799#define MAC_TX_STATS_LATE_COL 0x00000830
800#define MAC_TX_STATS_RESV4_1 0x00000834
801#define MAC_TX_STATS_RESV4_2 0x00000838
802#define MAC_TX_STATS_RESV4_3 0x0000083c
803#define MAC_TX_STATS_RESV4_4 0x00000840
804#define MAC_TX_STATS_RESV4_5 0x00000844
805#define MAC_TX_STATS_RESV4_6 0x00000848
806#define MAC_TX_STATS_RESV4_7 0x0000084c
807#define MAC_TX_STATS_RESV4_8 0x00000850
808#define MAC_TX_STATS_RESV4_9 0x00000854
809#define MAC_TX_STATS_RESV4_10 0x00000858
810#define MAC_TX_STATS_RESV4_11 0x0000085c
811#define MAC_TX_STATS_RESV4_12 0x00000860
812#define MAC_TX_STATS_RESV4_13 0x00000864
813#define MAC_TX_STATS_RESV4_14 0x00000868
814#define MAC_TX_STATS_UCAST 0x0000086c
815#define MAC_TX_STATS_MCAST 0x00000870
816#define MAC_TX_STATS_BCAST 0x00000874
817#define MAC_TX_STATS_RESV5_1 0x00000878
818#define MAC_TX_STATS_RESV5_2 0x0000087c
819#define MAC_RX_STATS_OCTETS 0x00000880
820#define MAC_RX_STATS_RESV1 0x00000884
821#define MAC_RX_STATS_FRAGMENTS 0x00000888
822#define MAC_RX_STATS_UCAST 0x0000088c
823#define MAC_RX_STATS_MCAST 0x00000890
824#define MAC_RX_STATS_BCAST 0x00000894
825#define MAC_RX_STATS_FCS_ERRORS 0x00000898
826#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
827#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
828#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
829#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
830#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
831#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
832#define MAC_RX_STATS_JABBERS 0x000008b4
833#define MAC_RX_STATS_UNDERSIZE 0x000008b8
834
835
836
837#define SNDDATAI_MODE 0x00000c00
838#define SNDDATAI_MODE_RESET 0x00000001
839#define SNDDATAI_MODE_ENABLE 0x00000002
840#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
841#define SNDDATAI_STATUS 0x00000c04
842#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
843#define SNDDATAI_STATSCTRL 0x00000c08
844#define SNDDATAI_SCTRL_ENABLE 0x00000001
845#define SNDDATAI_SCTRL_FASTUPD 0x00000002
846#define SNDDATAI_SCTRL_CLEAR 0x00000004
847#define SNDDATAI_SCTRL_FLUSH 0x00000008
848#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
849#define SNDDATAI_STATSENAB 0x00000c0c
850#define SNDDATAI_STATSINCMASK 0x00000c10
851#define ISO_PKT_TX 0x00000c20
852
853#define SNDDATAI_COS_CNT_0 0x00000c80
854#define SNDDATAI_COS_CNT_1 0x00000c84
855#define SNDDATAI_COS_CNT_2 0x00000c88
856#define SNDDATAI_COS_CNT_3 0x00000c8c
857#define SNDDATAI_COS_CNT_4 0x00000c90
858#define SNDDATAI_COS_CNT_5 0x00000c94
859#define SNDDATAI_COS_CNT_6 0x00000c98
860#define SNDDATAI_COS_CNT_7 0x00000c9c
861#define SNDDATAI_COS_CNT_8 0x00000ca0
862#define SNDDATAI_COS_CNT_9 0x00000ca4
863#define SNDDATAI_COS_CNT_10 0x00000ca8
864#define SNDDATAI_COS_CNT_11 0x00000cac
865#define SNDDATAI_COS_CNT_12 0x00000cb0
866#define SNDDATAI_COS_CNT_13 0x00000cb4
867#define SNDDATAI_COS_CNT_14 0x00000cb8
868#define SNDDATAI_COS_CNT_15 0x00000cbc
869#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
870#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
871#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
872#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
873#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
874#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
875#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
876#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
877
878
879
880#define SNDDATAC_MODE 0x00001000
881#define SNDDATAC_MODE_RESET 0x00000001
882#define SNDDATAC_MODE_ENABLE 0x00000002
883#define SNDDATAC_MODE_CDELAY 0x00000010
884
885
886
887#define SNDBDS_MODE 0x00001400
888#define SNDBDS_MODE_RESET 0x00000001
889#define SNDBDS_MODE_ENABLE 0x00000002
890#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
891#define SNDBDS_STATUS 0x00001404
892#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
893#define SNDBDS_HWDIAG 0x00001408
894
895#define SNDBDS_SEL_CON_IDX_0 0x00001440
896#define SNDBDS_SEL_CON_IDX_1 0x00001444
897#define SNDBDS_SEL_CON_IDX_2 0x00001448
898#define SNDBDS_SEL_CON_IDX_3 0x0000144c
899#define SNDBDS_SEL_CON_IDX_4 0x00001450
900#define SNDBDS_SEL_CON_IDX_5 0x00001454
901#define SNDBDS_SEL_CON_IDX_6 0x00001458
902#define SNDBDS_SEL_CON_IDX_7 0x0000145c
903#define SNDBDS_SEL_CON_IDX_8 0x00001460
904#define SNDBDS_SEL_CON_IDX_9 0x00001464
905#define SNDBDS_SEL_CON_IDX_10 0x00001468
906#define SNDBDS_SEL_CON_IDX_11 0x0000146c
907#define SNDBDS_SEL_CON_IDX_12 0x00001470
908#define SNDBDS_SEL_CON_IDX_13 0x00001474
909#define SNDBDS_SEL_CON_IDX_14 0x00001478
910#define SNDBDS_SEL_CON_IDX_15 0x0000147c
911
912
913
914#define SNDBDI_MODE 0x00001800
915#define SNDBDI_MODE_RESET 0x00000001
916#define SNDBDI_MODE_ENABLE 0x00000002
917#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
918#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
919#define SNDBDI_STATUS 0x00001804
920#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
921#define SNDBDI_IN_PROD_IDX_0 0x00001808
922#define SNDBDI_IN_PROD_IDX_1 0x0000180c
923#define SNDBDI_IN_PROD_IDX_2 0x00001810
924#define SNDBDI_IN_PROD_IDX_3 0x00001814
925#define SNDBDI_IN_PROD_IDX_4 0x00001818
926#define SNDBDI_IN_PROD_IDX_5 0x0000181c
927#define SNDBDI_IN_PROD_IDX_6 0x00001820
928#define SNDBDI_IN_PROD_IDX_7 0x00001824
929#define SNDBDI_IN_PROD_IDX_8 0x00001828
930#define SNDBDI_IN_PROD_IDX_9 0x0000182c
931#define SNDBDI_IN_PROD_IDX_10 0x00001830
932#define SNDBDI_IN_PROD_IDX_11 0x00001834
933#define SNDBDI_IN_PROD_IDX_12 0x00001838
934#define SNDBDI_IN_PROD_IDX_13 0x0000183c
935#define SNDBDI_IN_PROD_IDX_14 0x00001840
936#define SNDBDI_IN_PROD_IDX_15 0x00001844
937
938
939
940#define SNDBDC_MODE 0x00001c00
941#define SNDBDC_MODE_RESET 0x00000001
942#define SNDBDC_MODE_ENABLE 0x00000002
943#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
944
945
946
947#define RCVLPC_MODE 0x00002000
948#define RCVLPC_MODE_RESET 0x00000001
949#define RCVLPC_MODE_ENABLE 0x00000002
950#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
951#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
952#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
953#define RCVLPC_STATUS 0x00002004
954#define RCVLPC_STATUS_CLASS0 0x00000004
955#define RCVLPC_STATUS_MAPOOR 0x00000008
956#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
957#define RCVLPC_LOCK 0x00002008
958#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
959#define RCVLPC_LOCK_REQ_SHIFT 0
960#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
961#define RCVLPC_LOCK_GRANT_SHIFT 16
962#define RCVLPC_NON_EMPTY_BITS 0x0000200c
963#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
964#define RCVLPC_CONFIG 0x00002010
965#define RCVLPC_STATSCTRL 0x00002014
966#define RCVLPC_STATSCTRL_ENABLE 0x00000001
967#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
968#define RCVLPC_STATS_ENABLE 0x00002018
969#define RCVLPC_STATSENAB_ASF_FIX 0x00000002
970#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
971#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
972#define RCVLPC_STATS_INCMASK 0x0000201c
973
974#define RCVLPC_SELLST_BASE 0x00002100
975#define SELLST_TAIL 0x00000004
976#define SELLST_CONT 0x00000008
977#define SELLST_UNUSED 0x0000000c
978#define RCVLPC_COS_CNTL_BASE 0x00002200
979#define RCVLPC_DROP_FILTER_CNT 0x00002240
980#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
981#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
982#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
983#define RCVLPC_IN_DISCARDS_CNT 0x00002250
984#define RCVLPC_IN_ERRORS_CNT 0x00002254
985#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
986
987
988
989#define RCVDBDI_MODE 0x00002400
990#define RCVDBDI_MODE_RESET 0x00000001
991#define RCVDBDI_MODE_ENABLE 0x00000002
992#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
993#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
994#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
995#define RCVDBDI_MODE_LRG_RING_SZ 0x00010000
996#define RCVDBDI_STATUS 0x00002404
997#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
998#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
999#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1000#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1001
1002#define RCVDBDI_JUMBO_BD 0x00002440
1003#define RCVDBDI_STD_BD 0x00002450
1004#define RCVDBDI_MINI_BD 0x00002460
1005#define RCVDBDI_JUMBO_CON_IDX 0x00002470
1006#define RCVDBDI_STD_CON_IDX 0x00002474
1007#define RCVDBDI_MINI_CON_IDX 0x00002478
1008
1009#define RCVDBDI_BD_PROD_IDX_0 0x00002480
1010#define RCVDBDI_BD_PROD_IDX_1 0x00002484
1011#define RCVDBDI_BD_PROD_IDX_2 0x00002488
1012#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1013#define RCVDBDI_BD_PROD_IDX_4 0x00002490
1014#define RCVDBDI_BD_PROD_IDX_5 0x00002494
1015#define RCVDBDI_BD_PROD_IDX_6 0x00002498
1016#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1017#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1018#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1019#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1020#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1021#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1022#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1023#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1024#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1025#define RCVDBDI_HWDIAG 0x000024c0
1026
1027
1028
1029#define RCVDCC_MODE 0x00002800
1030#define RCVDCC_MODE_RESET 0x00000001
1031#define RCVDCC_MODE_ENABLE 0x00000002
1032#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1033
1034
1035
1036#define RCVBDI_MODE 0x00002c00
1037#define RCVBDI_MODE_RESET 0x00000001
1038#define RCVBDI_MODE_ENABLE 0x00000002
1039#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1040#define RCVBDI_STATUS 0x00002c04
1041#define RCVBDI_STATUS_RCB_ATTN 0x00000004
1042#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1043#define RCVBDI_STD_PROD_IDX 0x00002c0c
1044#define RCVBDI_MINI_PROD_IDX 0x00002c10
1045#define RCVBDI_MINI_THRESH 0x00002c14
1046#define RCVBDI_STD_THRESH 0x00002c18
1047#define RCVBDI_JUMBO_THRESH 0x00002c1c
1048
1049
1050#define STD_REPLENISH_LWM 0x00002d00
1051#define JMB_REPLENISH_LWM 0x00002d04
1052
1053
1054
1055#define RCVCC_MODE 0x00003000
1056#define RCVCC_MODE_RESET 0x00000001
1057#define RCVCC_MODE_ENABLE 0x00000002
1058#define RCVCC_MODE_ATTN_ENABLE 0x00000004
1059#define RCVCC_STATUS 0x00003004
1060#define RCVCC_STATUS_ERROR_ATTN 0x00000004
1061#define RCVCC_JUMP_PROD_IDX 0x00003008
1062#define RCVCC_STD_PROD_IDX 0x0000300c
1063#define RCVCC_MINI_PROD_IDX 0x00003010
1064
1065
1066
1067#define RCVLSC_MODE 0x00003400
1068#define RCVLSC_MODE_RESET 0x00000001
1069#define RCVLSC_MODE_ENABLE 0x00000002
1070#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1071#define RCVLSC_STATUS 0x00003404
1072#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1073
1074
1075#define TG3_CPMU_DRV_STATUS 0x0000344c
1076
1077
1078#define TG3_CPMU_CTRL 0x00003600
1079#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1080#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1081#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1082#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1083#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1084#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1085#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1086
1087
1088#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1089#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1090#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1091#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1092#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1093#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1094#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1095
1096
1097#define TG3_CPMU_HST_ACC 0x0000361c
1098#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1099#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1100
1101
1102#define TG3_CPMU_CLCK_ORIDE 0x00003624
1103#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1104
1105#define TG3_CPMU_STATUS 0x0000362c
1106#define TG3_CPMU_STATUS_FMSK_5717 0x20000000
1107#define TG3_CPMU_STATUS_FMSK_5719 0xc0000000
1108#define TG3_CPMU_STATUS_FSHFT_5719 30
1109
1110#define TG3_CPMU_CLCK_STAT 0x00003630
1111#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1112#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1113#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1114#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1115
1116
1117#define TG3_CPMU_MUTEX_REQ 0x0000365c
1118#define CPMU_MUTEX_REQ_DRIVER 0x00001000
1119#define TG3_CPMU_MUTEX_GNT 0x00003660
1120#define CPMU_MUTEX_GNT_DRIVER 0x00001000
1121#define TG3_CPMU_PHY_STRAP 0x00003664
1122#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1123
1124
1125#define TG3_CPMU_EEE_MODE 0x000036b0
1126#define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004
1127#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008
1128#define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040
1129#define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080
1130#define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100
1131#define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200
1132#define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000
1133#define TG3_CPMU_EEE_DBTMR1 0x000036b4
1134#define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
1135#define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff
1136#define TG3_CPMU_EEE_DBTMR2 0x000036b8
1137#define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
1138#define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff
1139#define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
1140#define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
1141#define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004
1142
1143
1144#define TG3_CPMU_EEE_CTRL 0x000036d0
1145#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d
1146#define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384
1147#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8
1148
1149
1150
1151#define MBFREE_MODE 0x00003800
1152#define MBFREE_MODE_RESET 0x00000001
1153#define MBFREE_MODE_ENABLE 0x00000002
1154#define MBFREE_STATUS 0x00003804
1155
1156
1157
1158#define HOSTCC_MODE 0x00003c00
1159#define HOSTCC_MODE_RESET 0x00000001
1160#define HOSTCC_MODE_ENABLE 0x00000002
1161#define HOSTCC_MODE_ATTN 0x00000004
1162#define HOSTCC_MODE_NOW 0x00000008
1163#define HOSTCC_MODE_FULL_STATUS 0x00000000
1164#define HOSTCC_MODE_64BYTE 0x00000080
1165#define HOSTCC_MODE_32BYTE 0x00000100
1166#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1167#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1168#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1169#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1170#define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1171#define HOSTCC_STATUS 0x00003c04
1172#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1173#define HOSTCC_RXCOL_TICKS 0x00003c08
1174#define LOW_RXCOL_TICKS 0x00000032
1175#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1176#define DEFAULT_RXCOL_TICKS 0x00000048
1177#define HIGH_RXCOL_TICKS 0x00000096
1178#define MAX_RXCOL_TICKS 0x000003ff
1179#define HOSTCC_TXCOL_TICKS 0x00003c0c
1180#define LOW_TXCOL_TICKS 0x00000096
1181#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1182#define DEFAULT_TXCOL_TICKS 0x0000012c
1183#define HIGH_TXCOL_TICKS 0x00000145
1184#define MAX_TXCOL_TICKS 0x000003ff
1185#define HOSTCC_RXMAX_FRAMES 0x00003c10
1186#define LOW_RXMAX_FRAMES 0x00000005
1187#define DEFAULT_RXMAX_FRAMES 0x00000008
1188#define HIGH_RXMAX_FRAMES 0x00000012
1189#define MAX_RXMAX_FRAMES 0x000000ff
1190#define HOSTCC_TXMAX_FRAMES 0x00003c14
1191#define LOW_TXMAX_FRAMES 0x00000035
1192#define DEFAULT_TXMAX_FRAMES 0x0000004b
1193#define HIGH_TXMAX_FRAMES 0x00000052
1194#define MAX_TXMAX_FRAMES 0x000000ff
1195#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1196#define DEFAULT_RXCOAL_TICK_INT 0x00000019
1197#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1198#define MAX_RXCOAL_TICK_INT 0x000003ff
1199#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1200#define DEFAULT_TXCOAL_TICK_INT 0x00000019
1201#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1202#define MAX_TXCOAL_TICK_INT 0x000003ff
1203#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1204#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1205#define MAX_RXCOAL_MAXF_INT 0x000000ff
1206#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1207#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1208#define MAX_TXCOAL_MAXF_INT 0x000000ff
1209#define HOSTCC_STAT_COAL_TICKS 0x00003c28
1210#define DEFAULT_STAT_COAL_TICKS 0x000f4240
1211#define MAX_STAT_COAL_TICKS 0xd693d400
1212#define MIN_STAT_COAL_TICKS 0x00000064
1213
1214#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30
1215#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38
1216#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1217#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1218#define HOSTCC_FLOW_ATTN 0x00003c48
1219#define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
1220
1221#define HOSTCC_JUMBO_CON_IDX 0x00003c50
1222#define HOSTCC_STD_CON_IDX 0x00003c54
1223#define HOSTCC_MINI_CON_IDX 0x00003c58
1224
1225#define HOSTCC_RET_PROD_IDX_0 0x00003c80
1226#define HOSTCC_RET_PROD_IDX_1 0x00003c84
1227#define HOSTCC_RET_PROD_IDX_2 0x00003c88
1228#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1229#define HOSTCC_RET_PROD_IDX_4 0x00003c90
1230#define HOSTCC_RET_PROD_IDX_5 0x00003c94
1231#define HOSTCC_RET_PROD_IDX_6 0x00003c98
1232#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1233#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1234#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1235#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1236#define HOSTCC_RET_PROD_IDX_11 0x00003cac
1237#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1238#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1239#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1240#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1241#define HOSTCC_SND_CON_IDX_0 0x00003cc0
1242#define HOSTCC_SND_CON_IDX_1 0x00003cc4
1243#define HOSTCC_SND_CON_IDX_2 0x00003cc8
1244#define HOSTCC_SND_CON_IDX_3 0x00003ccc
1245#define HOSTCC_SND_CON_IDX_4 0x00003cd0
1246#define HOSTCC_SND_CON_IDX_5 0x00003cd4
1247#define HOSTCC_SND_CON_IDX_6 0x00003cd8
1248#define HOSTCC_SND_CON_IDX_7 0x00003cdc
1249#define HOSTCC_SND_CON_IDX_8 0x00003ce0
1250#define HOSTCC_SND_CON_IDX_9 0x00003ce4
1251#define HOSTCC_SND_CON_IDX_10 0x00003ce8
1252#define HOSTCC_SND_CON_IDX_11 0x00003cec
1253#define HOSTCC_SND_CON_IDX_12 0x00003cf0
1254#define HOSTCC_SND_CON_IDX_13 0x00003cf4
1255#define HOSTCC_SND_CON_IDX_14 0x00003cf8
1256#define HOSTCC_SND_CON_IDX_15 0x00003cfc
1257#define HOSTCC_STATBLCK_RING1 0x00003d00
1258
1259
1260#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1261#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1262#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1263#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1264#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1265#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1266
1267
1268
1269#define MEMARB_MODE 0x00004000
1270#define MEMARB_MODE_RESET 0x00000001
1271#define MEMARB_MODE_ENABLE 0x00000002
1272#define MEMARB_STATUS 0x00004004
1273#define MEMARB_TRAP_ADDR_LOW 0x00004008
1274#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1275
1276
1277
1278#define BUFMGR_MODE 0x00004400
1279#define BUFMGR_MODE_RESET 0x00000001
1280#define BUFMGR_MODE_ENABLE 0x00000002
1281#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1282#define BUFMGR_MODE_BM_TEST 0x00000008
1283#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1284#define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000
1285#define BUFMGR_STATUS 0x00004404
1286#define BUFMGR_STATUS_ERROR 0x00000004
1287#define BUFMGR_STATUS_MBLOW 0x00000010
1288#define BUFMGR_MB_POOL_ADDR 0x00004408
1289#define BUFMGR_MB_POOL_SIZE 0x0000440c
1290#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1291#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1292#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1293#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1294#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1295#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1296#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1297#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1298#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1299#define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1300#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1301#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1302#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1303#define BUFMGR_MB_HIGH_WATER 0x00004418
1304#define DEFAULT_MB_HIGH_WATER 0x00000060
1305#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1306#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1307#define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1308#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1309#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1310#define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1311#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1312#define BUFMGR_MB_ALLOC_BIT 0x10000000
1313#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1314#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1315#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1316#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1317#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1318#define BUFMGR_DMA_LOW_WATER 0x00004434
1319#define DEFAULT_DMA_LOW_WATER 0x00000005
1320#define BUFMGR_DMA_HIGH_WATER 0x00004438
1321#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1322#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1323#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1324#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1325#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1326#define BUFMGR_HWDIAG_0 0x0000444c
1327#define BUFMGR_HWDIAG_1 0x00004450
1328#define BUFMGR_HWDIAG_2 0x00004454
1329
1330
1331
1332#define RDMAC_MODE 0x00004800
1333#define RDMAC_MODE_RESET 0x00000001
1334#define RDMAC_MODE_ENABLE 0x00000002
1335#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1336#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1337#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1338#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1339#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1340#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1341#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1342#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1343#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1344#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1345#define RDMAC_MODE_SPLIT_RESET 0x00001000
1346#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1347#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1348#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1349#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1350#define RDMAC_MODE_JMB_2K_MMRR 0x00800000
1351#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
1352#define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1353#define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1354#define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
1355#define RDMAC_STATUS 0x00004804
1356#define RDMAC_STATUS_TGTABORT 0x00000004
1357#define RDMAC_STATUS_MSTABORT 0x00000008
1358#define RDMAC_STATUS_PARITYERR 0x00000010
1359#define RDMAC_STATUS_ADDROFLOW 0x00000020
1360#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1361#define RDMAC_STATUS_FIFOURUN 0x00000080
1362#define RDMAC_STATUS_FIFOOREAD 0x00000100
1363#define RDMAC_STATUS_LNGREAD 0x00000200
1364
1365
1366#define TG3_RDMA_RSRVCTRL_REG 0x00004900
1367#define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1368#define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1369#define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1370#define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1371#define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1372#define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1373#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1374
1375
1376#define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910
1377#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1378#define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000
1379
1380
1381
1382#define WDMAC_MODE 0x00004c00
1383#define WDMAC_MODE_RESET 0x00000001
1384#define WDMAC_MODE_ENABLE 0x00000002
1385#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1386#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1387#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1388#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1389#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1390#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1391#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1392#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1393#define WDMAC_MODE_RX_ACCEL 0x00000400
1394#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1395#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1396#define WDMAC_STATUS 0x00004c04
1397#define WDMAC_STATUS_TGTABORT 0x00000004
1398#define WDMAC_STATUS_MSTABORT 0x00000008
1399#define WDMAC_STATUS_PARITYERR 0x00000010
1400#define WDMAC_STATUS_ADDROFLOW 0x00000020
1401#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1402#define WDMAC_STATUS_FIFOURUN 0x00000080
1403#define WDMAC_STATUS_FIFOOREAD 0x00000100
1404#define WDMAC_STATUS_LNGREAD 0x00000200
1405
1406
1407
1408#define CPU_MODE 0x00000000
1409#define CPU_MODE_RESET 0x00000001
1410#define CPU_MODE_HALT 0x00000400
1411#define CPU_STATE 0x00000004
1412#define CPU_EVTMASK 0x00000008
1413
1414#define CPU_PC 0x0000001c
1415#define CPU_INSN 0x00000020
1416#define CPU_SPAD_UFLOW 0x00000024
1417#define CPU_WDOG_CLEAR 0x00000028
1418#define CPU_WDOG_VECTOR 0x0000002c
1419#define CPU_WDOG_PC 0x00000030
1420#define CPU_HW_BP 0x00000034
1421
1422#define CPU_WDOG_SAVED_STATE 0x00000044
1423#define CPU_LAST_BRANCH_ADDR 0x00000048
1424#define CPU_SPAD_UFLOW_SET 0x0000004c
1425
1426#define CPU_R0 0x00000200
1427#define CPU_R1 0x00000204
1428#define CPU_R2 0x00000208
1429#define CPU_R3 0x0000020c
1430#define CPU_R4 0x00000210
1431#define CPU_R5 0x00000214
1432#define CPU_R6 0x00000218
1433#define CPU_R7 0x0000021c
1434#define CPU_R8 0x00000220
1435#define CPU_R9 0x00000224
1436#define CPU_R10 0x00000228
1437#define CPU_R11 0x0000022c
1438#define CPU_R12 0x00000230
1439#define CPU_R13 0x00000234
1440#define CPU_R14 0x00000238
1441#define CPU_R15 0x0000023c
1442#define CPU_R16 0x00000240
1443#define CPU_R17 0x00000244
1444#define CPU_R18 0x00000248
1445#define CPU_R19 0x0000024c
1446#define CPU_R20 0x00000250
1447#define CPU_R21 0x00000254
1448#define CPU_R22 0x00000258
1449#define CPU_R23 0x0000025c
1450#define CPU_R24 0x00000260
1451#define CPU_R25 0x00000264
1452#define CPU_R26 0x00000268
1453#define CPU_R27 0x0000026c
1454#define CPU_R28 0x00000270
1455#define CPU_R29 0x00000274
1456#define CPU_R30 0x00000278
1457#define CPU_R31 0x0000027c
1458
1459
1460#define RX_CPU_BASE 0x00005000
1461#define RX_CPU_MODE 0x00005000
1462#define RX_CPU_STATE 0x00005004
1463#define RX_CPU_PGMCTR 0x0000501c
1464#define RX_CPU_HWBKPT 0x00005034
1465#define TX_CPU_BASE 0x00005400
1466#define TX_CPU_MODE 0x00005400
1467#define TX_CPU_STATE 0x00005404
1468#define TX_CPU_PGMCTR 0x0000541c
1469
1470#define VCPU_STATUS 0x00005100
1471#define VCPU_STATUS_INIT_DONE 0x04000000
1472#define VCPU_STATUS_DRV_RESET 0x08000000
1473
1474#define VCPU_CFGSHDW 0x00005104
1475#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1476#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1477#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1478
1479
1480#define GRCMBOX_BASE 0x00005600
1481#define GRCMBOX_INTERRUPT_0 0x00005800
1482#define GRCMBOX_INTERRUPT_1 0x00005808
1483#define GRCMBOX_INTERRUPT_2 0x00005810
1484#define GRCMBOX_INTERRUPT_3 0x00005818
1485#define GRCMBOX_GENERAL_0 0x00005820
1486#define GRCMBOX_GENERAL_1 0x00005828
1487#define GRCMBOX_GENERAL_2 0x00005830
1488#define GRCMBOX_GENERAL_3 0x00005838
1489#define GRCMBOX_GENERAL_4 0x00005840
1490#define GRCMBOX_GENERAL_5 0x00005848
1491#define GRCMBOX_GENERAL_6 0x00005850
1492#define GRCMBOX_GENERAL_7 0x00005858
1493#define GRCMBOX_RELOAD_STAT 0x00005860
1494#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868
1495#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870
1496#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878
1497#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880
1498#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888
1499#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890
1500#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898
1501#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0
1502#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8
1503#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0
1504#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8
1505#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0
1506#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8
1507#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0
1508#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8
1509#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0
1510#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8
1511#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0
1512#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8
1513#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900
1514#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908
1515#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910
1516#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918
1517#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920
1518#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928
1519#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930
1520#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938
1521#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940
1522#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948
1523#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950
1524#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958
1525#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960
1526#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968
1527#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970
1528#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978
1529#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980
1530#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988
1531#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990
1532#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998
1533#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0
1534#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8
1535#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0
1536#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8
1537#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0
1538#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8
1539#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0
1540#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8
1541#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0
1542#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8
1543#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0
1544#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8
1545#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1546#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1547#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1548#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1549
1550
1551
1552#define FTQ_RESET 0x00005c00
1553
1554#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1555#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1556#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1557#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1558#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1559#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1560#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1561#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1562#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1563#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1564#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1565#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1566#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1567#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1568#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1569#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1570#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1571#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1572#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1573#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1574#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1575#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1576#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1577#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1578#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1579#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1580#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1581#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1582#define FTQ_SWTYPE1_CTL 0x00005c80
1583#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1584#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1585#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1586#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1587#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1588#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1589#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1590#define FTQ_HOST_COAL_CTL 0x00005ca0
1591#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1592#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1593#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1594#define FTQ_MAC_TX_CTL 0x00005cb0
1595#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1596#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1597#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1598#define FTQ_MB_FREE_CTL 0x00005cc0
1599#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1600#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1601#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1602#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1603#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1604#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1605#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1606#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1607#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1608#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1609#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1610#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1611#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1612#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1613#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1614#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1615#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1616#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1617#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1618#define FTQ_SWTYPE2_CTL 0x00005d10
1619#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1620#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1621#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1622
1623
1624
1625#define MSGINT_MODE 0x00006000
1626#define MSGINT_MODE_RESET 0x00000001
1627#define MSGINT_MODE_ENABLE 0x00000002
1628#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1629#define MSGINT_MODE_MULTIVEC_EN 0x00000080
1630#define MSGINT_STATUS 0x00006004
1631#define MSGINT_STATUS_MSI_REQ 0x00000001
1632#define MSGINT_FIFO 0x00006008
1633
1634
1635
1636#define DMAC_MODE 0x00006400
1637#define DMAC_MODE_RESET 0x00000001
1638#define DMAC_MODE_ENABLE 0x00000002
1639
1640
1641
1642#define GRC_MODE 0x00006800
1643#define GRC_MODE_UPD_ON_COAL 0x00000001
1644#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1645#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1646#define GRC_MODE_BSWAP_DATA 0x00000010
1647#define GRC_MODE_WSWAP_DATA 0x00000020
1648#define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1649#define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1650#define GRC_MODE_SPLITHDR 0x00000100
1651#define GRC_MODE_NOFRM_CRACKING 0x00000200
1652#define GRC_MODE_INCL_CRC 0x00000400
1653#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1654#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1655#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1656#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1657#define GRC_MODE_B2HRX_ENABLE 0x00008000
1658#define GRC_MODE_HOST_STACKUP 0x00010000
1659#define GRC_MODE_HOST_SENDBDS 0x00020000
1660#define GRC_MODE_HTX2B_ENABLE 0x00040000
1661#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1662#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1663#define GRC_MODE_PCIE_TL_SEL 0x00000000
1664#define GRC_MODE_PCIE_PL_SEL 0x00400000
1665#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1666#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1667#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1668#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1669#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1670#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1671#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1672#define GRC_MODE_PCIE_DL_SEL 0x20000000
1673#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1674#define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1675#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1676 GRC_MODE_PCIE_PL_SEL | \
1677 GRC_MODE_PCIE_DL_SEL | \
1678 GRC_MODE_PCIE_HI_1K_EN)
1679#define GRC_MISC_CFG 0x00006804
1680#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1681#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1682#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1683#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1684#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1685#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1686#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1687#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1688#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1689#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1690#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1691#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1692#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1693#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1694#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1695#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1696#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1697#define GRC_LOCAL_CTRL 0x00006808
1698#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1699#define GRC_LCLCTRL_CLEARINT 0x00000002
1700#define GRC_LCLCTRL_SETINT 0x00000004
1701#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1702#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010
1703#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010
1704#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020
1705#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1706#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1707#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1708#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1709#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1710#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1711#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1712#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1713#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1714#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1715#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1716#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1717#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1718#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1719#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1720#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1721#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1722#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1723#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1724#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1725#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1726#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1727#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1728#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1729#define GRC_TIMER 0x0000680c
1730#define GRC_RX_CPU_EVENT 0x00006810
1731#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1732#define GRC_RX_TIMER_REF 0x00006814
1733#define GRC_RX_CPU_SEM 0x00006818
1734#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1735#define GRC_TX_CPU_EVENT 0x00006820
1736#define GRC_TX_TIMER_REF 0x00006824
1737#define GRC_TX_CPU_SEM 0x00006828
1738#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1739#define GRC_MEM_POWER_UP 0x00006830
1740#define GRC_EEPROM_ADDR 0x00006838
1741#define EEPROM_ADDR_WRITE 0x00000000
1742#define EEPROM_ADDR_READ 0x80000000
1743#define EEPROM_ADDR_COMPLETE 0x40000000
1744#define EEPROM_ADDR_FSM_RESET 0x20000000
1745#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1746#define EEPROM_ADDR_DEVID_SHIFT 26
1747#define EEPROM_ADDR_START 0x02000000
1748#define EEPROM_ADDR_CLKPERD_SHIFT 16
1749#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1750#define EEPROM_ADDR_ADDR_SHIFT 0
1751#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1752#define EEPROM_CHIP_SIZE (64 * 1024)
1753#define GRC_EEPROM_DATA 0x0000683c
1754#define GRC_EEPROM_CTRL 0x00006840
1755#define GRC_MDI_CTRL 0x00006844
1756#define GRC_SEEPROM_DELAY 0x00006848
1757
1758#define GRC_VCPU_EXT_CTRL 0x00006890
1759#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1760#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1761#define GRC_FASTBOOT_PC 0x00006894
1762
1763
1764
1765
1766#define NVRAM_CMD 0x00007000
1767#define NVRAM_CMD_RESET 0x00000001
1768#define NVRAM_CMD_DONE 0x00000008
1769#define NVRAM_CMD_GO 0x00000010
1770#define NVRAM_CMD_WR 0x00000020
1771#define NVRAM_CMD_RD 0x00000000
1772#define NVRAM_CMD_ERASE 0x00000040
1773#define NVRAM_CMD_FIRST 0x00000080
1774#define NVRAM_CMD_LAST 0x00000100
1775#define NVRAM_CMD_WREN 0x00010000
1776#define NVRAM_CMD_WRDI 0x00020000
1777#define NVRAM_STAT 0x00007004
1778#define NVRAM_WRDATA 0x00007008
1779#define NVRAM_ADDR 0x0000700c
1780#define NVRAM_ADDR_MSK 0x00ffffff
1781#define NVRAM_RDDATA 0x00007010
1782#define NVRAM_CFG1 0x00007014
1783#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1784#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1785#define NVRAM_CFG1_PASS_THRU 0x00000004
1786#define NVRAM_CFG1_STATUS_BITS 0x00000070
1787#define NVRAM_CFG1_BIT_BANG 0x00000008
1788#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1789#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1790#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1791#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1792#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1793#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1794#define FLASH_VENDOR_ST 0x03000001
1795#define FLASH_VENDOR_SAIFUN 0x01000003
1796#define FLASH_VENDOR_SST_SMALL 0x00000001
1797#define FLASH_VENDOR_SST_LARGE 0x02000001
1798#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1799#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1800#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1801#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1802#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1803#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1804#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1805#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1806#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1807#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1808#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1809#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1810#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1811#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1812#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1813#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1814#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1815#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1816#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1817#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1818#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1819#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1820#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1821#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1822#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1823#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1824#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1825#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1826#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1827#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1828#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1829#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1830#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1831#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1832#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1833#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1834#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1835#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1836#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1837#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1838#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1839#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1840#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1841#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1842#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1843#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1844#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1845#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1846#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1847#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1848#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1849#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1850#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1851#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1852#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1853#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1854#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1855#define FLASH_5717VENDOR_ST_25USPT 0x03400002
1856#define FLASH_5717VENDOR_ST_45USPT 0x03400001
1857#define FLASH_5720_EEPROM_HD 0x00000001
1858#define FLASH_5720_EEPROM_LD 0x00000003
1859#define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
1860#define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
1861#define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
1862#define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
1863#define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
1864#define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
1865#define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
1866#define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
1867#define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
1868#define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
1869#define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
1870#define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
1871#define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
1872#define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
1873#define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
1874#define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
1875#define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
1876#define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
1877#define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
1878#define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
1879#define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
1880#define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
1881#define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
1882#define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
1883#define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
1884#define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
1885#define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
1886#define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
1887#define FLASH_5720VENDOR_ST_25USPT 0x03c00002
1888#define FLASH_5720VENDOR_ST_45USPT 0x03c00001
1889#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1890#define FLASH_5752PAGE_SIZE_256 0x00000000
1891#define FLASH_5752PAGE_SIZE_512 0x10000000
1892#define FLASH_5752PAGE_SIZE_1K 0x20000000
1893#define FLASH_5752PAGE_SIZE_2K 0x30000000
1894#define FLASH_5752PAGE_SIZE_4K 0x40000000
1895#define FLASH_5752PAGE_SIZE_264 0x50000000
1896#define FLASH_5752PAGE_SIZE_528 0x60000000
1897#define NVRAM_CFG2 0x00007018
1898#define NVRAM_CFG3 0x0000701c
1899#define NVRAM_SWARB 0x00007020
1900#define SWARB_REQ_SET0 0x00000001
1901#define SWARB_REQ_SET1 0x00000002
1902#define SWARB_REQ_SET2 0x00000004
1903#define SWARB_REQ_SET3 0x00000008
1904#define SWARB_REQ_CLR0 0x00000010
1905#define SWARB_REQ_CLR1 0x00000020
1906#define SWARB_REQ_CLR2 0x00000040
1907#define SWARB_REQ_CLR3 0x00000080
1908#define SWARB_GNT0 0x00000100
1909#define SWARB_GNT1 0x00000200
1910#define SWARB_GNT2 0x00000400
1911#define SWARB_GNT3 0x00000800
1912#define SWARB_REQ0 0x00001000
1913#define SWARB_REQ1 0x00002000
1914#define SWARB_REQ2 0x00004000
1915#define SWARB_REQ3 0x00008000
1916#define NVRAM_ACCESS 0x00007024
1917#define ACCESS_ENABLE 0x00000001
1918#define ACCESS_WR_ENABLE 0x00000002
1919#define NVRAM_WRITE1 0x00007028
1920
1921
1922#define NVRAM_ADDR_LOCKOUT 0x00007030
1923
1924
1925#define OTP_MODE 0x00007500
1926#define OTP_MODE_OTP_THRU_GRC 0x00000001
1927#define OTP_CTRL 0x00007504
1928#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
1929#define OTP_CTRL_OTP_CMD_READ 0x00000000
1930#define OTP_CTRL_OTP_CMD_INIT 0x00000008
1931#define OTP_CTRL_OTP_CMD_START 0x00000001
1932#define OTP_STATUS 0x00007508
1933#define OTP_STATUS_CMD_DONE 0x00000001
1934#define OTP_ADDRESS 0x0000750c
1935#define OTP_ADDRESS_MAGIC1 0x000000a0
1936#define OTP_ADDRESS_MAGIC2 0x00000080
1937
1938
1939#define OTP_READ_DATA 0x00007514
1940
1941
1942#define PCIE_TRANSACTION_CFG 0x00007c04
1943#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1944#define PCIE_TRANS_CFG_LOM 0x00000020
1945
1946
1947#define PCIE_PWR_MGMT_THRESH 0x00007d28
1948#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
1949#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
1950#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
1951
1952
1953#define TG3_PCIE_LNKCTL 0x00007d54
1954#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
1955#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
1956
1957
1958#define TG3_PCIE_PHY_TSTCTL 0x00007e2c
1959#define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
1960#define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
1961
1962#define TG3_PCIE_EIDLE_DELAY 0x00007e70
1963#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
1964#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
1965
1966
1967
1968
1969#define TG3_PCIE_TLDLPL_PORT 0x00007c00
1970#define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
1971#define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
1972#define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
1973#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
1974#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
1975#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
1976#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
1977
1978#define TG3_REG_BLK_SIZE 0x00008000
1979
1980
1981#define TG3_OTP_AGCTGT_MASK 0x000000e0
1982#define TG3_OTP_AGCTGT_SHIFT 1
1983#define TG3_OTP_HPFFLTR_MASK 0x00000300
1984#define TG3_OTP_HPFFLTR_SHIFT 1
1985#define TG3_OTP_HPFOVER_MASK 0x00000400
1986#define TG3_OTP_HPFOVER_SHIFT 1
1987#define TG3_OTP_LPFDIS_MASK 0x00000800
1988#define TG3_OTP_LPFDIS_SHIFT 11
1989#define TG3_OTP_VDAC_MASK 0xff000000
1990#define TG3_OTP_VDAC_SHIFT 24
1991#define TG3_OTP_10BTAMP_MASK 0x0000f000
1992#define TG3_OTP_10BTAMP_SHIFT 8
1993#define TG3_OTP_ROFF_MASK 0x00e00000
1994#define TG3_OTP_ROFF_SHIFT 11
1995#define TG3_OTP_RCOFF_MASK 0x001c0000
1996#define TG3_OTP_RCOFF_SHIFT 16
1997
1998#define TG3_OTP_DEFAULT 0x286c1640
1999
2000
2001
2002#define TG3_NVM_VPD_OFF 0x100
2003#define TG3_NVM_VPD_LEN 256
2004
2005
2006#define TG3_NVM_HWSB_CFG1 0x00000004
2007#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
2008#define TG3_NVM_HWSB_CFG1_MAJSFT 27
2009#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
2010#define TG3_NVM_HWSB_CFG1_MINSFT 22
2011
2012#define TG3_EEPROM_MAGIC 0x669955aa
2013#define TG3_EEPROM_MAGIC_FW 0xa5000000
2014#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
2015#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
2016#define TG3_EEPROM_SB_FORMAT_1 0x00200000
2017#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
2018#define TG3_EEPROM_SB_REVISION_0 0x00000000
2019#define TG3_EEPROM_SB_REVISION_2 0x00020000
2020#define TG3_EEPROM_SB_REVISION_3 0x00030000
2021#define TG3_EEPROM_SB_REVISION_4 0x00040000
2022#define TG3_EEPROM_SB_REVISION_5 0x00050000
2023#define TG3_EEPROM_SB_REVISION_6 0x00060000
2024#define TG3_EEPROM_MAGIC_HW 0xabcd
2025#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
2026
2027#define TG3_NVM_DIR_START 0x18
2028#define TG3_NVM_DIR_END 0x78
2029#define TG3_NVM_DIRENT_SIZE 0xc
2030#define TG3_NVM_DIRTYPE_SHIFT 24
2031#define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
2032#define TG3_NVM_DIRTYPE_ASFINI 1
2033#define TG3_NVM_DIRTYPE_EXTVPD 20
2034#define TG3_NVM_PTREV_BCVER 0x94
2035#define TG3_NVM_BCVER_MAJMSK 0x0000ff00
2036#define TG3_NVM_BCVER_MAJSFT 8
2037#define TG3_NVM_BCVER_MINMSK 0x000000ff
2038
2039#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
2040#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
2041#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2042#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
2043#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
2044#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
2045#define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
2046#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
2047#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
2048#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
2049#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
2050#define TG3_EEPROM_SB_EDH_BLD_SHFT 11
2051
2052
2053
2054#define NIC_SRAM_WIN_BASE 0x00008000
2055
2056
2057#define NIC_SRAM_PAGE_ZERO 0x00000000
2058#define NIC_SRAM_SEND_RCB 0x00000100
2059#define NIC_SRAM_RCV_RET_RCB 0x00000200
2060#define NIC_SRAM_STATS_BLK 0x00000300
2061#define NIC_SRAM_STATUS_BLK 0x00000b00
2062
2063#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
2064#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
2065#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b
2066
2067#define NIC_SRAM_DATA_SIG 0x00000b54
2068#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654
2069
2070#define NIC_SRAM_DATA_CFG 0x00000b58
2071#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
2072#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
2073#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
2074#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
2075#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
2076#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
2077#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
2078#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
2079#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
2080#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
2081#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
2082#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
2083#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
2084#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
2085#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
2086
2087#define NIC_SRAM_DATA_VER 0x00000b5c
2088#define NIC_SRAM_DATA_VER_SHIFT 16
2089
2090#define NIC_SRAM_DATA_PHY_ID 0x00000b74
2091#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
2092#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
2093
2094#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
2095#define FWCMD_NICDRV_ALIVE 0x00000001
2096#define FWCMD_NICDRV_PAUSE_FW 0x00000002
2097#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
2098#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
2099#define FWCMD_NICDRV_FIX_DMAR 0x00000005
2100#define FWCMD_NICDRV_FIX_DMAW 0x00000006
2101#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
2102#define FWCMD_NICDRV_ALIVE2 0x0000000d
2103#define FWCMD_NICDRV_ALIVE3 0x0000000e
2104#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
2105#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
2106#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
2107#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
2108#define DRV_STATE_START 0x00000001
2109#define DRV_STATE_START_DONE 0x80000001
2110#define DRV_STATE_UNLOAD 0x00000002
2111#define DRV_STATE_UNLOAD_DONE 0x80000002
2112#define DRV_STATE_WOL 0x00000003
2113#define DRV_STATE_SUSPEND 0x00000004
2114
2115#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
2116
2117#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
2118#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
2119
2120#define NIC_SRAM_WOL_MBOX 0x00000d30
2121#define WOL_SIGNATURE 0x474c0000
2122#define WOL_DRV_STATE_SHUTDOWN 0x00000001
2123#define WOL_DRV_WOL 0x00000002
2124#define WOL_SET_MAGIC_PKT 0x00000004
2125
2126#define NIC_SRAM_DATA_CFG_2 0x00000d38
2127
2128#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
2129#define SHASTA_EXT_LED_MODE_MASK 0x00018000
2130#define SHASTA_EXT_LED_LEGACY 0x00000000
2131#define SHASTA_EXT_LED_SHARED 0x00008000
2132#define SHASTA_EXT_LED_MAC 0x00010000
2133#define SHASTA_EXT_LED_COMBO 0x00018000
2134
2135#define NIC_SRAM_DATA_CFG_3 0x00000d3c
2136#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2137
2138#define NIC_SRAM_DATA_CFG_4 0x00000d60
2139#define NIC_SRAM_GMII_MODE 0x00000002
2140#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
2141#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2142#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2143
2144#define NIC_SRAM_CPMU_STATUS 0x00000e00
2145#define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
2146#define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
2147
2148#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2149
2150#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2151#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2152#define NIC_SRAM_TX_BUFFER_DESC 0x00004000
2153#define NIC_SRAM_RX_BUFFER_DESC 0x00006000
2154#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000
2155#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2156#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2157#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2158#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2159#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2160
2161#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
2162#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
2163#define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
2164
2165#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
2166#define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
2167
2168
2169
2170#define TG3_PHY_MII_ADDR 0x01
2171
2172
2173
2174#define MII_TG3_MMD_CTRL 0x0d
2175#define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2176#define MII_TG3_MMD_ADDRESS 0x0e
2177
2178#define MII_TG3_EXT_CTRL 0x10
2179#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2180#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2181#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2182#define MII_TG3_EXT_CTRL_TBI 0x8000
2183
2184#define MII_TG3_EXT_STAT 0x11
2185#define MII_TG3_EXT_STAT_MDIX 0x2000
2186#define MII_TG3_EXT_STAT_LPASS 0x0100
2187
2188#define MII_TG3_RXR_COUNTERS 0x14
2189#define MII_TG3_DSP_RW_PORT 0x15
2190#define MII_TG3_DSP_CONTROL 0x16
2191#define MII_TG3_DSP_ADDRESS 0x17
2192
2193#define MII_TG3_DSP_TAP1 0x0001
2194#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2195#define MII_TG3_DSP_TAP26 0x001a
2196#define MII_TG3_DSP_TAP26_ALNOKO 0x0001
2197#define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
2198#define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
2199#define MII_TG3_DSP_AADJ1CH0 0x001f
2200#define MII_TG3_DSP_CH34TP2 0x4022
2201#define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff
2202#define MII_TG3_DSP_AADJ1CH3 0x601f
2203#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2204#define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2205#define MII_TG3_DSP_EXP8 0x0f08
2206#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2207#define MII_TG3_DSP_EXP8_AEDW 0x0200
2208#define MII_TG3_DSP_EXP75 0x0f75
2209#define MII_TG3_DSP_EXP96 0x0f96
2210#define MII_TG3_DSP_EXP97 0x0f97
2211
2212#define MII_TG3_AUX_CTRL 0x18
2213
2214#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2215#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2216#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2217#define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
2218#define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000
2219
2220#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2221#define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
2222#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2223#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2224#define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2225#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2226
2227#define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2228
2229#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2230#define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
2231#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2232#define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2233#define MII_TG3_AUXCTL_MISC_WREN 0x8000
2234
2235
2236#define MII_TG3_AUX_STAT 0x19
2237#define MII_TG3_AUX_STAT_LPASS 0x0004
2238#define MII_TG3_AUX_STAT_SPDMASK 0x0700
2239#define MII_TG3_AUX_STAT_10HALF 0x0100
2240#define MII_TG3_AUX_STAT_10FULL 0x0200
2241#define MII_TG3_AUX_STAT_100HALF 0x0300
2242#define MII_TG3_AUX_STAT_100_4 0x0400
2243#define MII_TG3_AUX_STAT_100FULL 0x0500
2244#define MII_TG3_AUX_STAT_1000HALF 0x0600
2245#define MII_TG3_AUX_STAT_1000FULL 0x0700
2246#define MII_TG3_AUX_STAT_100 0x0008
2247#define MII_TG3_AUX_STAT_FULL 0x0001
2248
2249#define MII_TG3_ISTAT 0x1a
2250#define MII_TG3_IMASK 0x1b
2251
2252
2253#define MII_TG3_INT_LINKCHG 0x0002
2254#define MII_TG3_INT_SPEEDCHG 0x0004
2255#define MII_TG3_INT_DUPLEXCHG 0x0008
2256#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2257
2258#define MII_TG3_MISC_SHDW 0x1c
2259#define MII_TG3_MISC_SHDW_WREN 0x8000
2260
2261#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2262#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2263#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2264
2265#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2266#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2267#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2268#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2269#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2270#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2271
2272#define MII_TG3_TEST1 0x1e
2273#define MII_TG3_TEST1_TRIM_EN 0x0010
2274#define MII_TG3_TEST1_CRC_EN 0x8000
2275
2276
2277#define TG3_CL45_D7_EEERES_STAT 0x803e
2278#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2279#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
2280
2281
2282
2283#define MII_TG3_FET_PTEST 0x17
2284#define MII_TG3_FET_PTEST_TRIM_SEL 0x0010
2285#define MII_TG3_FET_PTEST_TRIM_2 0x0002
2286#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2287#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2288
2289#define MII_TG3_FET_GEN_STAT 0x1c
2290#define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000
2291
2292#define MII_TG3_FET_TEST 0x1f
2293#define MII_TG3_FET_SHADOW_EN 0x0080
2294
2295#define MII_TG3_FET_SHDW_MISCCTRL 0x10
2296#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2297
2298#define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2299#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2300
2301#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2302#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2303
2304
2305
2306#define TG3_APE_GPIO_MSG 0x0008
2307#define TG3_APE_GPIO_MSG_SHIFT 4
2308#define TG3_APE_EVENT 0x000c
2309#define APE_EVENT_1 0x00000001
2310#define TG3_APE_LOCK_REQ 0x002c
2311#define APE_LOCK_REQ_DRIVER 0x00001000
2312#define TG3_APE_LOCK_GRANT 0x004c
2313#define APE_LOCK_GRANT_DRIVER 0x00001000
2314#define TG3_APE_SEG_SIG 0x4000
2315#define APE_SEG_SIG_MAGIC 0x41504521
2316
2317
2318#define TG3_APE_FW_STATUS 0x400c
2319#define APE_FW_STATUS_READY 0x00000100
2320#define TG3_APE_FW_FEATURES 0x4010
2321#define TG3_APE_FW_FEATURE_NCSI 0x00000002
2322#define TG3_APE_FW_VERSION 0x4018
2323#define APE_FW_VERSION_MAJMSK 0xff000000
2324#define APE_FW_VERSION_MAJSFT 24
2325#define APE_FW_VERSION_MINMSK 0x00ff0000
2326#define APE_FW_VERSION_MINSFT 16
2327#define APE_FW_VERSION_REVMSK 0x0000ff00
2328#define APE_FW_VERSION_REVSFT 8
2329#define APE_FW_VERSION_BLDMSK 0x000000ff
2330#define TG3_APE_HOST_SEG_SIG 0x4200
2331#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2332#define TG3_APE_HOST_SEG_LEN 0x4204
2333#define APE_HOST_SEG_LEN_MAGIC 0x00000020
2334#define TG3_APE_HOST_INIT_COUNT 0x4208
2335#define TG3_APE_HOST_DRIVER_ID 0x420c
2336#define APE_HOST_DRIVER_ID_LINUX 0xf0000000
2337#define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2338 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2339#define TG3_APE_HOST_BEHAVIOR 0x4210
2340#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2341#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2342#define APE_HOST_HEARTBEAT_INT_DISABLE 0
2343#define APE_HOST_HEARTBEAT_INT_5SEC 5000
2344#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2345#define TG3_APE_HOST_DRVR_STATE 0x421c
2346#define TG3_APE_HOST_DRVR_STATE_START 0x00000001
2347#define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2348#define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
2349#define TG3_APE_HOST_WOL_SPEED 0x4224
2350#define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
2351
2352#define TG3_APE_EVENT_STATUS 0x4300
2353
2354#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2355#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2356#define APE_EVENT_STATUS_STATE_START 0x00010000
2357#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2358#define APE_EVENT_STATUS_STATE_WOL 0x00030000
2359#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2360#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2361
2362#define TG3_APE_PER_LOCK_REQ 0x8400
2363#define APE_LOCK_PER_REQ_DRIVER 0x00001000
2364#define TG3_APE_PER_LOCK_GRANT 0x8420
2365#define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2366
2367
2368#define TG3_APE_LOCK_PHY0 0
2369#define TG3_APE_LOCK_GRC 1
2370#define TG3_APE_LOCK_PHY1 2
2371#define TG3_APE_LOCK_PHY2 3
2372#define TG3_APE_LOCK_MEM 4
2373#define TG3_APE_LOCK_PHY3 5
2374#define TG3_APE_LOCK_GPIO 7
2375
2376#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415struct tg3_tx_buffer_desc {
2416 u32 addr_hi;
2417 u32 addr_lo;
2418
2419 u32 len_flags;
2420#define TXD_FLAG_TCPUDP_CSUM 0x0001
2421#define TXD_FLAG_IP_CSUM 0x0002
2422#define TXD_FLAG_END 0x0004
2423#define TXD_FLAG_IP_FRAG 0x0008
2424#define TXD_FLAG_JMB_PKT 0x0008
2425#define TXD_FLAG_IP_FRAG_END 0x0010
2426#define TXD_FLAG_VLAN 0x0040
2427#define TXD_FLAG_COAL_NOW 0x0080
2428#define TXD_FLAG_CPU_PRE_DMA 0x0100
2429#define TXD_FLAG_CPU_POST_DMA 0x0200
2430#define TXD_FLAG_ADD_SRC_ADDR 0x1000
2431#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2432#define TXD_FLAG_NO_CRC 0x8000
2433#define TXD_LEN_SHIFT 16
2434
2435 u32 vlan_tag;
2436#define TXD_VLAN_TAG_SHIFT 0
2437#define TXD_MSS_SHIFT 16
2438};
2439
2440#define TXD_ADDR 0x00UL
2441#define TXD_LEN_FLAGS 0x08UL
2442#define TXD_VLAN_TAG 0x0cUL
2443#define TXD_SIZE 0x10UL
2444
2445struct tg3_rx_buffer_desc {
2446 u32 addr_hi;
2447 u32 addr_lo;
2448
2449 u32 idx_len;
2450#define RXD_IDX_MASK 0xffff0000
2451#define RXD_IDX_SHIFT 16
2452#define RXD_LEN_MASK 0x0000ffff
2453#define RXD_LEN_SHIFT 0
2454
2455 u32 type_flags;
2456#define RXD_TYPE_SHIFT 16
2457#define RXD_FLAGS_SHIFT 0
2458
2459#define RXD_FLAG_END 0x0004
2460#define RXD_FLAG_MINI 0x0800
2461#define RXD_FLAG_JUMBO 0x0020
2462#define RXD_FLAG_VLAN 0x0040
2463#define RXD_FLAG_ERROR 0x0400
2464#define RXD_FLAG_IP_CSUM 0x1000
2465#define RXD_FLAG_TCPUDP_CSUM 0x2000
2466#define RXD_FLAG_IS_TCP 0x4000
2467
2468 u32 ip_tcp_csum;
2469#define RXD_IPCSUM_MASK 0xffff0000
2470#define RXD_IPCSUM_SHIFT 16
2471#define RXD_TCPCSUM_MASK 0x0000ffff
2472#define RXD_TCPCSUM_SHIFT 0
2473
2474 u32 err_vlan;
2475
2476#define RXD_VLAN_MASK 0x0000ffff
2477
2478#define RXD_ERR_BAD_CRC 0x00010000
2479#define RXD_ERR_COLLISION 0x00020000
2480#define RXD_ERR_LINK_LOST 0x00040000
2481#define RXD_ERR_PHY_DECODE 0x00080000
2482#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2483#define RXD_ERR_MAC_ABRT 0x00200000
2484#define RXD_ERR_TOO_SMALL 0x00400000
2485#define RXD_ERR_NO_RESOURCES 0x00800000
2486#define RXD_ERR_HUGE_FRAME 0x01000000
2487#define RXD_ERR_MASK 0xffff0000
2488
2489 u32 reserved;
2490 u32 opaque;
2491#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2492#define RXD_OPAQUE_INDEX_SHIFT 0
2493#define RXD_OPAQUE_RING_STD 0x00010000
2494#define RXD_OPAQUE_RING_JUMBO 0x00020000
2495#define RXD_OPAQUE_RING_MINI 0x00040000
2496#define RXD_OPAQUE_RING_MASK 0x00070000
2497};
2498
2499struct tg3_ext_rx_buffer_desc {
2500 struct {
2501 u32 addr_hi;
2502 u32 addr_lo;
2503 } addrlist[3];
2504 u32 len2_len1;
2505 u32 resv_len3;
2506 struct tg3_rx_buffer_desc std;
2507};
2508
2509
2510
2511
2512
2513struct tg3_internal_buffer_desc {
2514 u32 addr_hi;
2515 u32 addr_lo;
2516 u32 nic_mbuf;
2517
2518#ifdef __BIG_ENDIAN
2519 u16 cqid_sqid;
2520 u16 len;
2521#else
2522 u16 len;
2523 u16 cqid_sqid;
2524#endif
2525 u32 flags;
2526 u32 __cookie1;
2527 u32 __cookie2;
2528 u32 __cookie3;
2529};
2530
2531#define TG3_HW_STATUS_SIZE 0x50
2532struct tg3_hw_status {
2533 u32 status;
2534#define SD_STATUS_UPDATED 0x00000001
2535#define SD_STATUS_LINK_CHG 0x00000002
2536#define SD_STATUS_ERROR 0x00000004
2537
2538 u32 status_tag;
2539
2540#ifdef __BIG_ENDIAN
2541 u16 rx_consumer;
2542 u16 rx_jumbo_consumer;
2543#else
2544 u16 rx_jumbo_consumer;
2545 u16 rx_consumer;
2546#endif
2547
2548#ifdef __BIG_ENDIAN
2549 u16 reserved;
2550 u16 rx_mini_consumer;
2551#else
2552 u16 rx_mini_consumer;
2553 u16 reserved;
2554#endif
2555 struct {
2556#ifdef __BIG_ENDIAN
2557 u16 tx_consumer;
2558 u16 rx_producer;
2559#else
2560 u16 rx_producer;
2561 u16 tx_consumer;
2562#endif
2563 } idx[16];
2564};
2565
2566typedef struct {
2567 u32 high, low;
2568} tg3_stat64_t;
2569
2570struct tg3_hw_stats {
2571 u8 __reserved0[0x400-0x300];
2572
2573
2574 tg3_stat64_t rx_octets;
2575 u64 __reserved1;
2576 tg3_stat64_t rx_fragments;
2577 tg3_stat64_t rx_ucast_packets;
2578 tg3_stat64_t rx_mcast_packets;
2579 tg3_stat64_t rx_bcast_packets;
2580 tg3_stat64_t rx_fcs_errors;
2581 tg3_stat64_t rx_align_errors;
2582 tg3_stat64_t rx_xon_pause_rcvd;
2583 tg3_stat64_t rx_xoff_pause_rcvd;
2584 tg3_stat64_t rx_mac_ctrl_rcvd;
2585 tg3_stat64_t rx_xoff_entered;
2586 tg3_stat64_t rx_frame_too_long_errors;
2587 tg3_stat64_t rx_jabbers;
2588 tg3_stat64_t rx_undersize_packets;
2589 tg3_stat64_t rx_in_length_errors;
2590 tg3_stat64_t rx_out_length_errors;
2591 tg3_stat64_t rx_64_or_less_octet_packets;
2592 tg3_stat64_t rx_65_to_127_octet_packets;
2593 tg3_stat64_t rx_128_to_255_octet_packets;
2594 tg3_stat64_t rx_256_to_511_octet_packets;
2595 tg3_stat64_t rx_512_to_1023_octet_packets;
2596 tg3_stat64_t rx_1024_to_1522_octet_packets;
2597 tg3_stat64_t rx_1523_to_2047_octet_packets;
2598 tg3_stat64_t rx_2048_to_4095_octet_packets;
2599 tg3_stat64_t rx_4096_to_8191_octet_packets;
2600 tg3_stat64_t rx_8192_to_9022_octet_packets;
2601
2602 u64 __unused0[37];
2603
2604
2605 tg3_stat64_t tx_octets;
2606 u64 __reserved2;
2607 tg3_stat64_t tx_collisions;
2608 tg3_stat64_t tx_xon_sent;
2609 tg3_stat64_t tx_xoff_sent;
2610 tg3_stat64_t tx_flow_control;
2611 tg3_stat64_t tx_mac_errors;
2612 tg3_stat64_t tx_single_collisions;
2613 tg3_stat64_t tx_mult_collisions;
2614 tg3_stat64_t tx_deferred;
2615 u64 __reserved3;
2616 tg3_stat64_t tx_excessive_collisions;
2617 tg3_stat64_t tx_late_collisions;
2618 tg3_stat64_t tx_collide_2times;
2619 tg3_stat64_t tx_collide_3times;
2620 tg3_stat64_t tx_collide_4times;
2621 tg3_stat64_t tx_collide_5times;
2622 tg3_stat64_t tx_collide_6times;
2623 tg3_stat64_t tx_collide_7times;
2624 tg3_stat64_t tx_collide_8times;
2625 tg3_stat64_t tx_collide_9times;
2626 tg3_stat64_t tx_collide_10times;
2627 tg3_stat64_t tx_collide_11times;
2628 tg3_stat64_t tx_collide_12times;
2629 tg3_stat64_t tx_collide_13times;
2630 tg3_stat64_t tx_collide_14times;
2631 tg3_stat64_t tx_collide_15times;
2632 tg3_stat64_t tx_ucast_packets;
2633 tg3_stat64_t tx_mcast_packets;
2634 tg3_stat64_t tx_bcast_packets;
2635 tg3_stat64_t tx_carrier_sense_errors;
2636 tg3_stat64_t tx_discards;
2637 tg3_stat64_t tx_errors;
2638
2639 u64 __unused1[31];
2640
2641
2642 tg3_stat64_t COS_rx_packets[16];
2643 tg3_stat64_t COS_rx_filter_dropped;
2644 tg3_stat64_t dma_writeq_full;
2645 tg3_stat64_t dma_write_prioq_full;
2646 tg3_stat64_t rxbds_empty;
2647 tg3_stat64_t rx_discards;
2648 tg3_stat64_t rx_errors;
2649 tg3_stat64_t rx_threshold_hit;
2650
2651 u64 __unused2[9];
2652
2653
2654 tg3_stat64_t COS_out_packets[16];
2655 tg3_stat64_t dma_readq_full;
2656 tg3_stat64_t dma_read_prioq_full;
2657 tg3_stat64_t tx_comp_queue_full;
2658
2659
2660 tg3_stat64_t ring_set_send_prod_index;
2661 tg3_stat64_t ring_status_update;
2662 tg3_stat64_t nic_irqs;
2663 tg3_stat64_t nic_avoided_irqs;
2664 tg3_stat64_t nic_tx_threshold_hit;
2665
2666
2667
2668
2669 tg3_stat64_t mbuf_lwm_thresh_hit;
2670
2671 u8 __reserved4[0xb00-0x9c8];
2672};
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682struct ring_info {
2683 u8 *data;
2684 DEFINE_DMA_UNMAP_ADDR(mapping);
2685};
2686
2687struct tg3_tx_ring_info {
2688 struct sk_buff *skb;
2689 DEFINE_DMA_UNMAP_ADDR(mapping);
2690 bool fragmented;
2691};
2692
2693struct tg3_link_config {
2694
2695 u32 advertising;
2696 u16 speed;
2697 u8 duplex;
2698 u8 autoneg;
2699 u8 flowctrl;
2700
2701
2702 u8 active_flowctrl;
2703
2704 u8 active_duplex;
2705 u16 active_speed;
2706 u32 rmt_adv;
2707};
2708
2709struct tg3_bufmgr_config {
2710 u32 mbuf_read_dma_low_water;
2711 u32 mbuf_mac_rx_low_water;
2712 u32 mbuf_high_water;
2713
2714 u32 mbuf_read_dma_low_water_jumbo;
2715 u32 mbuf_mac_rx_low_water_jumbo;
2716 u32 mbuf_high_water_jumbo;
2717
2718 u32 dma_low_water;
2719 u32 dma_high_water;
2720};
2721
2722struct tg3_ethtool_stats {
2723
2724 u64 rx_octets;
2725 u64 rx_fragments;
2726 u64 rx_ucast_packets;
2727 u64 rx_mcast_packets;
2728 u64 rx_bcast_packets;
2729 u64 rx_fcs_errors;
2730 u64 rx_align_errors;
2731 u64 rx_xon_pause_rcvd;
2732 u64 rx_xoff_pause_rcvd;
2733 u64 rx_mac_ctrl_rcvd;
2734 u64 rx_xoff_entered;
2735 u64 rx_frame_too_long_errors;
2736 u64 rx_jabbers;
2737 u64 rx_undersize_packets;
2738 u64 rx_in_length_errors;
2739 u64 rx_out_length_errors;
2740 u64 rx_64_or_less_octet_packets;
2741 u64 rx_65_to_127_octet_packets;
2742 u64 rx_128_to_255_octet_packets;
2743 u64 rx_256_to_511_octet_packets;
2744 u64 rx_512_to_1023_octet_packets;
2745 u64 rx_1024_to_1522_octet_packets;
2746 u64 rx_1523_to_2047_octet_packets;
2747 u64 rx_2048_to_4095_octet_packets;
2748 u64 rx_4096_to_8191_octet_packets;
2749 u64 rx_8192_to_9022_octet_packets;
2750
2751
2752 u64 tx_octets;
2753 u64 tx_collisions;
2754 u64 tx_xon_sent;
2755 u64 tx_xoff_sent;
2756 u64 tx_flow_control;
2757 u64 tx_mac_errors;
2758 u64 tx_single_collisions;
2759 u64 tx_mult_collisions;
2760 u64 tx_deferred;
2761 u64 tx_excessive_collisions;
2762 u64 tx_late_collisions;
2763 u64 tx_collide_2times;
2764 u64 tx_collide_3times;
2765 u64 tx_collide_4times;
2766 u64 tx_collide_5times;
2767 u64 tx_collide_6times;
2768 u64 tx_collide_7times;
2769 u64 tx_collide_8times;
2770 u64 tx_collide_9times;
2771 u64 tx_collide_10times;
2772 u64 tx_collide_11times;
2773 u64 tx_collide_12times;
2774 u64 tx_collide_13times;
2775 u64 tx_collide_14times;
2776 u64 tx_collide_15times;
2777 u64 tx_ucast_packets;
2778 u64 tx_mcast_packets;
2779 u64 tx_bcast_packets;
2780 u64 tx_carrier_sense_errors;
2781 u64 tx_discards;
2782 u64 tx_errors;
2783
2784
2785 u64 dma_writeq_full;
2786 u64 dma_write_prioq_full;
2787 u64 rxbds_empty;
2788 u64 rx_discards;
2789 u64 rx_errors;
2790 u64 rx_threshold_hit;
2791
2792
2793 u64 dma_readq_full;
2794 u64 dma_read_prioq_full;
2795 u64 tx_comp_queue_full;
2796
2797
2798 u64 ring_set_send_prod_index;
2799 u64 ring_status_update;
2800 u64 nic_irqs;
2801 u64 nic_avoided_irqs;
2802 u64 nic_tx_threshold_hit;
2803
2804 u64 mbuf_lwm_thresh_hit;
2805};
2806
2807struct tg3_rx_prodring_set {
2808 u32 rx_std_prod_idx;
2809 u32 rx_std_cons_idx;
2810 u32 rx_jmb_prod_idx;
2811 u32 rx_jmb_cons_idx;
2812 struct tg3_rx_buffer_desc *rx_std;
2813 struct tg3_ext_rx_buffer_desc *rx_jmb;
2814 struct ring_info *rx_std_buffers;
2815 struct ring_info *rx_jmb_buffers;
2816 dma_addr_t rx_std_mapping;
2817 dma_addr_t rx_jmb_mapping;
2818};
2819
2820#define TG3_IRQ_MAX_VECS_RSS 5
2821#define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
2822
2823struct tg3_napi {
2824 struct napi_struct napi ____cacheline_aligned;
2825 struct tg3 *tp;
2826 struct tg3_hw_status *hw_status;
2827
2828 u32 chk_msi_cnt;
2829 u32 last_tag;
2830 u32 last_irq_tag;
2831 u32 int_mbox;
2832 u32 coal_now;
2833
2834 u32 consmbox ____cacheline_aligned;
2835 u32 rx_rcb_ptr;
2836 u32 last_rx_cons;
2837 u16 *rx_rcb_prod_idx;
2838 struct tg3_rx_prodring_set prodring;
2839 struct tg3_rx_buffer_desc *rx_rcb;
2840
2841 u32 tx_prod ____cacheline_aligned;
2842 u32 tx_cons;
2843 u32 tx_pending;
2844 u32 last_tx_cons;
2845 u32 prodmbox;
2846 struct tg3_tx_buffer_desc *tx_ring;
2847 struct tg3_tx_ring_info *tx_buffers;
2848
2849 dma_addr_t status_mapping;
2850 dma_addr_t rx_rcb_mapping;
2851 dma_addr_t tx_desc_mapping;
2852
2853 char irq_lbl[IFNAMSIZ];
2854 unsigned int irq_vec;
2855};
2856
2857enum TG3_FLAGS {
2858 TG3_FLAG_TAGGED_STATUS = 0,
2859 TG3_FLAG_TXD_MBOX_HWBUG,
2860 TG3_FLAG_USE_LINKCHG_REG,
2861 TG3_FLAG_ERROR_PROCESSED,
2862 TG3_FLAG_ENABLE_ASF,
2863 TG3_FLAG_ASPM_WORKAROUND,
2864 TG3_FLAG_POLL_SERDES,
2865 TG3_FLAG_MBOX_WRITE_REORDER,
2866 TG3_FLAG_PCIX_TARGET_HWBUG,
2867 TG3_FLAG_WOL_SPEED_100MB,
2868 TG3_FLAG_WOL_ENABLE,
2869 TG3_FLAG_EEPROM_WRITE_PROT,
2870 TG3_FLAG_NVRAM,
2871 TG3_FLAG_NVRAM_BUFFERED,
2872 TG3_FLAG_SUPPORT_MSI,
2873 TG3_FLAG_SUPPORT_MSIX,
2874 TG3_FLAG_USING_MSI,
2875 TG3_FLAG_USING_MSIX,
2876 TG3_FLAG_PCIX_MODE,
2877 TG3_FLAG_PCI_HIGH_SPEED,
2878 TG3_FLAG_PCI_32BIT,
2879 TG3_FLAG_SRAM_USE_CONFIG,
2880 TG3_FLAG_TX_RECOVERY_PENDING,
2881 TG3_FLAG_WOL_CAP,
2882 TG3_FLAG_JUMBO_RING_ENABLE,
2883 TG3_FLAG_PAUSE_AUTONEG,
2884 TG3_FLAG_CPMU_PRESENT,
2885 TG3_FLAG_40BIT_DMA_BUG,
2886 TG3_FLAG_BROKEN_CHECKSUMS,
2887 TG3_FLAG_JUMBO_CAPABLE,
2888 TG3_FLAG_CHIP_RESETTING,
2889 TG3_FLAG_INIT_COMPLETE,
2890 TG3_FLAG_TSO_BUG,
2891 TG3_FLAG_MAX_RXPEND_64,
2892 TG3_FLAG_TSO_CAPABLE,
2893 TG3_FLAG_PCI_EXPRESS,
2894 TG3_FLAG_ASF_NEW_HANDSHAKE,
2895 TG3_FLAG_HW_AUTONEG,
2896 TG3_FLAG_IS_NIC,
2897 TG3_FLAG_FLASH,
2898 TG3_FLAG_HW_TSO_1,
2899 TG3_FLAG_HW_TSO_2,
2900 TG3_FLAG_HW_TSO_3,
2901 TG3_FLAG_ICH_WORKAROUND,
2902 TG3_FLAG_1SHOT_MSI,
2903 TG3_FLAG_NO_FWARE_REPORTED,
2904 TG3_FLAG_NO_NVRAM_ADDR_TRANS,
2905 TG3_FLAG_ENABLE_APE,
2906 TG3_FLAG_PROTECTED_NVRAM,
2907 TG3_FLAG_5701_DMA_BUG,
2908 TG3_FLAG_USE_PHYLIB,
2909 TG3_FLAG_MDIOBUS_INITED,
2910 TG3_FLAG_LRG_PROD_RING_CAP,
2911 TG3_FLAG_RGMII_INBAND_DISABLE,
2912 TG3_FLAG_RGMII_EXT_IBND_RX_EN,
2913 TG3_FLAG_RGMII_EXT_IBND_TX_EN,
2914 TG3_FLAG_CLKREQ_BUG,
2915 TG3_FLAG_NO_NVRAM,
2916 TG3_FLAG_ENABLE_RSS,
2917 TG3_FLAG_ENABLE_TSS,
2918 TG3_FLAG_SHORT_DMA_BUG,
2919 TG3_FLAG_USE_JUMBO_BDFLAG,
2920 TG3_FLAG_L1PLLPD_EN,
2921 TG3_FLAG_APE_HAS_NCSI,
2922 TG3_FLAG_4K_FIFO_LIMIT,
2923 TG3_FLAG_RESET_TASK_PENDING,
2924 TG3_FLAG_5705_PLUS,
2925 TG3_FLAG_IS_5788,
2926 TG3_FLAG_5750_PLUS,
2927 TG3_FLAG_5780_CLASS,
2928 TG3_FLAG_5755_PLUS,
2929 TG3_FLAG_57765_PLUS,
2930 TG3_FLAG_57765_CLASS,
2931 TG3_FLAG_5717_PLUS,
2932
2933
2934 TG3_FLAG_NUMBER_OF_FLAGS,
2935};
2936
2937struct tg3 {
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955 unsigned int irq_sync;
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976 spinlock_t lock;
2977 spinlock_t indirect_lock;
2978
2979 u32 (*read32) (struct tg3 *, u32);
2980 void (*write32) (struct tg3 *, u32, u32);
2981 u32 (*read32_mbox) (struct tg3 *, u32);
2982 void (*write32_mbox) (struct tg3 *, u32,
2983 u32);
2984 void __iomem *regs;
2985 void __iomem *aperegs;
2986 struct net_device *dev;
2987 struct pci_dev *pdev;
2988
2989 u32 coal_now;
2990 u32 msg_enable;
2991
2992
2993 void (*write32_tx_mbox) (struct tg3 *, u32,
2994 u32);
2995 u32 dma_limit;
2996
2997
2998 struct tg3_napi napi[TG3_IRQ_MAX_VECS];
2999 void (*write32_rx_mbox) (struct tg3 *, u32,
3000 u32);
3001 u32 rx_copy_thresh;
3002 u32 rx_std_ring_mask;
3003 u32 rx_jmb_ring_mask;
3004 u32 rx_ret_ring_mask;
3005 u32 rx_pending;
3006 u32 rx_jumbo_pending;
3007 u32 rx_std_max_post;
3008 u32 rx_offset;
3009 u32 rx_pkt_map_sz;
3010 bool rx_refill;
3011
3012
3013
3014 unsigned long rx_dropped;
3015 unsigned long tx_dropped;
3016 struct rtnl_link_stats64 net_stats_prev;
3017 struct tg3_ethtool_stats estats_prev;
3018
3019 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
3020
3021 union {
3022 unsigned long phy_crc_errors;
3023 unsigned long last_event_jiffies;
3024 };
3025
3026 struct timer_list timer;
3027 u16 timer_counter;
3028 u16 timer_multiplier;
3029 u32 timer_offset;
3030 u16 asf_counter;
3031 u16 asf_multiplier;
3032
3033
3034 u32 serdes_counter;
3035#define SERDES_AN_TIMEOUT_5704S 2
3036#define SERDES_PARALLEL_DET_TIMEOUT 1
3037#define SERDES_AN_TIMEOUT_5714S 1
3038
3039 struct tg3_link_config link_config;
3040 struct tg3_bufmgr_config bufmgr_config;
3041
3042
3043 u32 rx_mode;
3044 u32 tx_mode;
3045 u32 mac_mode;
3046 u32 mi_mode;
3047 u32 misc_host_ctrl;
3048 u32 grc_mode;
3049 u32 grc_local_ctrl;
3050 u32 dma_rwctrl;
3051 u32 coalesce_mode;
3052 u32 pwrmgmt_thresh;
3053
3054
3055 u32 pci_chip_rev_id;
3056 u16 pci_cmd;
3057 u8 pci_cacheline_sz;
3058 u8 pci_lat_timer;
3059
3060 int pci_fn;
3061 int pm_cap;
3062 int msi_cap;
3063 int pcix_cap;
3064 int pcie_readrq;
3065
3066 struct mii_bus *mdio_bus;
3067 int mdio_irq[PHY_MAX_ADDR];
3068 int old_link;
3069
3070 u8 phy_addr;
3071
3072
3073 u32 phy_id;
3074#define TG3_PHY_ID_MASK 0xfffffff0
3075#define TG3_PHY_ID_BCM5400 0x60008040
3076#define TG3_PHY_ID_BCM5401 0x60008050
3077#define TG3_PHY_ID_BCM5411 0x60008070
3078#define TG3_PHY_ID_BCM5701 0x60008110
3079#define TG3_PHY_ID_BCM5703 0x60008160
3080#define TG3_PHY_ID_BCM5704 0x60008190
3081#define TG3_PHY_ID_BCM5705 0x600081a0
3082#define TG3_PHY_ID_BCM5750 0x60008180
3083#define TG3_PHY_ID_BCM5752 0x60008100
3084#define TG3_PHY_ID_BCM5714 0x60008340
3085#define TG3_PHY_ID_BCM5780 0x60008350
3086#define TG3_PHY_ID_BCM5755 0xbc050cc0
3087#define TG3_PHY_ID_BCM5787 0xbc050ce0
3088#define TG3_PHY_ID_BCM5756 0xbc050ed0
3089#define TG3_PHY_ID_BCM5784 0xbc050fa0
3090#define TG3_PHY_ID_BCM5761 0xbc050fd0
3091#define TG3_PHY_ID_BCM5718C 0x5c0d8a00
3092#define TG3_PHY_ID_BCM5718S 0xbc050ff0
3093#define TG3_PHY_ID_BCM57765 0x5c0d8a40
3094#define TG3_PHY_ID_BCM5719C 0x5c0d8a20
3095#define TG3_PHY_ID_BCM5720C 0x5c0d8b60
3096#define TG3_PHY_ID_BCM5906 0xdc00ac40
3097#define TG3_PHY_ID_BCM8002 0x60010140
3098#define TG3_PHY_ID_INVALID 0xffffffff
3099
3100#define PHY_ID_RTL8211C 0x001cc910
3101#define PHY_ID_RTL8201E 0x00008200
3102
3103#define TG3_PHY_ID_REV_MASK 0x0000000f
3104#define TG3_PHY_REV_BCM5401_B0 0x1
3105
3106
3107
3108
3109#define TG3_KNOWN_PHY_ID(X) \
3110 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3111 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3112 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3113 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3114 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3115 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3116 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3117 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3118 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3119 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3120 (X) == TG3_PHY_ID_BCM8002)
3121
3122 u32 phy_flags;
3123#define TG3_PHYFLG_IS_LOW_POWER 0x00000001
3124#define TG3_PHYFLG_IS_CONNECTED 0x00000002
3125#define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
3126#define TG3_PHYFLG_PHY_SERDES 0x00000010
3127#define TG3_PHYFLG_MII_SERDES 0x00000020
3128#define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
3129 TG3_PHYFLG_MII_SERDES)
3130#define TG3_PHYFLG_IS_FET 0x00000040
3131#define TG3_PHYFLG_10_100_ONLY 0x00000080
3132#define TG3_PHYFLG_ENABLE_APD 0x00000100
3133#define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
3134#define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
3135#define TG3_PHYFLG_JITTER_BUG 0x00000800
3136#define TG3_PHYFLG_ADJUST_TRIM 0x00001000
3137#define TG3_PHYFLG_ADC_BUG 0x00002000
3138#define TG3_PHYFLG_5704_A0_BUG 0x00004000
3139#define TG3_PHYFLG_BER_BUG 0x00008000
3140#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3141#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3142#define TG3_PHYFLG_EEE_CAP 0x00040000
3143#define TG3_PHYFLG_MDIX_STATE 0x00200000
3144
3145 u32 led_ctrl;
3146 u32 phy_otp;
3147 u32 setlpicnt;
3148 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE];
3149
3150#define TG3_BPN_SIZE 24
3151 char board_part_number[TG3_BPN_SIZE];
3152#define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
3153 char fw_ver[TG3_VER_SIZE];
3154 u32 nic_sram_data_cfg;
3155 u32 pci_clock_ctrl;
3156 struct pci_dev *pdev_peer;
3157
3158 struct tg3_hw_stats *hw_stats;
3159 dma_addr_t stats_mapping;
3160 struct work_struct reset_task;
3161
3162 int nvram_lock_cnt;
3163 u32 nvram_size;
3164#define TG3_NVRAM_SIZE_2KB 0x00000800
3165#define TG3_NVRAM_SIZE_64KB 0x00010000
3166#define TG3_NVRAM_SIZE_128KB 0x00020000
3167#define TG3_NVRAM_SIZE_256KB 0x00040000
3168#define TG3_NVRAM_SIZE_512KB 0x00080000
3169#define TG3_NVRAM_SIZE_1MB 0x00100000
3170#define TG3_NVRAM_SIZE_2MB 0x00200000
3171
3172 u32 nvram_pagesize;
3173 u32 nvram_jedecnum;
3174
3175#define JEDEC_ATMEL 0x1f
3176#define JEDEC_ST 0x20
3177#define JEDEC_SAIFUN 0x4f
3178#define JEDEC_SST 0xbf
3179
3180#define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
3181#define ATMEL_AT24C02_PAGE_SIZE (8)
3182
3183#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
3184#define ATMEL_AT24C64_PAGE_SIZE (32)
3185
3186#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
3187#define ATMEL_AT24C512_PAGE_SIZE (128)
3188
3189#define ATMEL_AT45DB0X1B_PAGE_POS 9
3190#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3191
3192#define ATMEL_AT25F512_PAGE_SIZE 256
3193
3194#define ST_M45PEX0_PAGE_SIZE 256
3195
3196#define SAIFUN_SA25F0XX_PAGE_SIZE 256
3197
3198#define SST_25VF0X0_PAGE_SIZE 4098
3199
3200 unsigned int irq_max;
3201 unsigned int irq_cnt;
3202
3203 struct ethtool_coalesce coal;
3204
3205
3206 const char *fw_needed;
3207 const struct firmware *fw;
3208 u32 fw_len;
3209};
3210
3211#endif
3212