1
2
3
4#ifndef _SKGE_H
5#define _SKGE_H
6#include <linux/interrupt.h>
7
8
9#define PCI_DEV_REG1 0x40
10#define PCI_PHY_COMA 0x8000000
11#define PCI_VIO 0x2000000
12
13#define PCI_DEV_REG2 0x44
14#define PCI_VPD_ROM_SZ 7L<<14
15#define PCI_REV_DESC 1<<2
16
17#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
18 PCI_STATUS_SIG_SYSTEM_ERROR | \
19 PCI_STATUS_REC_MASTER_ABORT | \
20 PCI_STATUS_REC_TARGET_ABORT | \
21 PCI_STATUS_PARITY)
22
23enum csr_regs {
24 B0_RAP = 0x0000,
25 B0_CTST = 0x0004,
26 B0_LED = 0x0006,
27 B0_POWER_CTRL = 0x0007,
28 B0_ISRC = 0x0008,
29 B0_IMSK = 0x000c,
30 B0_HWE_ISRC = 0x0010,
31 B0_HWE_IMSK = 0x0014,
32 B0_SP_ISRC = 0x0018,
33 B0_XM1_IMSK = 0x0020,
34 B0_XM1_ISRC = 0x0028,
35 B0_XM1_PHY_ADDR = 0x0030,
36 B0_XM1_PHY_DATA = 0x0034,
37 B0_XM2_IMSK = 0x0040,
38 B0_XM2_ISRC = 0x0048,
39 B0_XM2_PHY_ADDR = 0x0050,
40 B0_XM2_PHY_DATA = 0x0054,
41 B0_R1_CSR = 0x0060,
42 B0_R2_CSR = 0x0064,
43 B0_XS1_CSR = 0x0068,
44 B0_XA1_CSR = 0x006c,
45 B0_XS2_CSR = 0x0070,
46 B0_XA2_CSR = 0x0074,
47
48 B2_MAC_1 = 0x0100,
49 B2_MAC_2 = 0x0108,
50 B2_MAC_3 = 0x0110,
51 B2_CONN_TYP = 0x0118,
52 B2_PMD_TYP = 0x0119,
53 B2_MAC_CFG = 0x011a,
54 B2_CHIP_ID = 0x011b,
55 B2_E_0 = 0x011c,
56 B2_E_1 = 0x011d,
57 B2_E_2 = 0x011e,
58 B2_E_3 = 0x011f,
59 B2_FAR = 0x0120,
60 B2_FDP = 0x0124,
61 B2_LD_CTRL = 0x0128,
62 B2_LD_TEST = 0x0129,
63 B2_TI_INI = 0x0130,
64 B2_TI_VAL = 0x0134,
65 B2_TI_CTRL = 0x0138,
66 B2_TI_TEST = 0x0139,
67 B2_IRQM_INI = 0x0140,
68 B2_IRQM_VAL = 0x0144,
69 B2_IRQM_CTRL = 0x0148,
70 B2_IRQM_TEST = 0x0149,
71 B2_IRQM_MSK = 0x014c,
72 B2_IRQM_HWE_MSK = 0x0150,
73 B2_TST_CTRL1 = 0x0158,
74 B2_TST_CTRL2 = 0x0159,
75 B2_GP_IO = 0x015c,
76 B2_I2C_CTRL = 0x0160,
77 B2_I2C_DATA = 0x0164,
78 B2_I2C_IRQ = 0x0168,
79 B2_I2C_SW = 0x016c,
80 B2_BSC_INI = 0x0170,
81 B2_BSC_VAL = 0x0174,
82 B2_BSC_CTRL = 0x0178,
83 B2_BSC_STAT = 0x0179,
84 B2_BSC_TST = 0x017a,
85
86 B3_RAM_ADDR = 0x0180,
87 B3_RAM_DATA_LO = 0x0184,
88 B3_RAM_DATA_HI = 0x0188,
89 B3_RI_WTO_R1 = 0x0190,
90 B3_RI_WTO_XA1 = 0x0191,
91 B3_RI_WTO_XS1 = 0x0192,
92 B3_RI_RTO_R1 = 0x0193,
93 B3_RI_RTO_XA1 = 0x0194,
94 B3_RI_RTO_XS1 = 0x0195,
95 B3_RI_WTO_R2 = 0x0196,
96 B3_RI_WTO_XA2 = 0x0197,
97 B3_RI_WTO_XS2 = 0x0198,
98 B3_RI_RTO_R2 = 0x0199,
99 B3_RI_RTO_XA2 = 0x019a,
100 B3_RI_RTO_XS2 = 0x019b,
101 B3_RI_TO_VAL = 0x019c,
102 B3_RI_CTRL = 0x01a0,
103 B3_RI_TEST = 0x01a2,
104 B3_MA_TOINI_RX1 = 0x01b0,
105 B3_MA_TOINI_RX2 = 0x01b1,
106 B3_MA_TOINI_TX1 = 0x01b2,
107 B3_MA_TOINI_TX2 = 0x01b3,
108 B3_MA_TOVAL_RX1 = 0x01b4,
109 B3_MA_TOVAL_RX2 = 0x01b5,
110 B3_MA_TOVAL_TX1 = 0x01b6,
111 B3_MA_TOVAL_TX2 = 0x01b7,
112 B3_MA_TO_CTRL = 0x01b8,
113 B3_MA_TO_TEST = 0x01ba,
114 B3_MA_RCINI_RX1 = 0x01c0,
115 B3_MA_RCINI_RX2 = 0x01c1,
116 B3_MA_RCINI_TX1 = 0x01c2,
117 B3_MA_RCINI_TX2 = 0x01c3,
118 B3_MA_RCVAL_RX1 = 0x01c4,
119 B3_MA_RCVAL_RX2 = 0x01c5,
120 B3_MA_RCVAL_TX1 = 0x01c6,
121 B3_MA_RCVAL_TX2 = 0x01c7,
122 B3_MA_RC_CTRL = 0x01c8,
123 B3_MA_RC_TEST = 0x01ca,
124 B3_PA_TOINI_RX1 = 0x01d0,
125 B3_PA_TOINI_RX2 = 0x01d4,
126 B3_PA_TOINI_TX1 = 0x01d8,
127 B3_PA_TOINI_TX2 = 0x01dc,
128 B3_PA_TOVAL_RX1 = 0x01e0,
129 B3_PA_TOVAL_RX2 = 0x01e4,
130 B3_PA_TOVAL_TX1 = 0x01e8,
131 B3_PA_TOVAL_TX2 = 0x01ec,
132 B3_PA_CTRL = 0x01f0,
133 B3_PA_TEST = 0x01f2,
134};
135
136
137enum {
138 CS_CLK_RUN_HOT = 1<<13,
139 CS_CLK_RUN_RST = 1<<12,
140 CS_CLK_RUN_ENA = 1<<11,
141 CS_VAUX_AVAIL = 1<<10,
142 CS_BUS_CLOCK = 1<<9,
143 CS_BUS_SLOT_SZ = 1<<8,
144 CS_ST_SW_IRQ = 1<<7,
145 CS_CL_SW_IRQ = 1<<6,
146 CS_STOP_DONE = 1<<5,
147 CS_STOP_MAST = 1<<4,
148 CS_MRST_CLR = 1<<3,
149 CS_MRST_SET = 1<<2,
150 CS_RST_CLR = 1<<1,
151 CS_RST_SET = 1,
152
153
154
155 LED_STAT_ON = 1<<1,
156 LED_STAT_OFF = 1,
157
158
159 PC_VAUX_ENA = 1<<7,
160 PC_VAUX_DIS = 1<<6,
161 PC_VCC_ENA = 1<<5,
162 PC_VCC_DIS = 1<<4,
163 PC_VAUX_ON = 1<<3,
164 PC_VAUX_OFF = 1<<2,
165 PC_VCC_ON = 1<<1,
166 PC_VCC_OFF = 1<<0,
167};
168
169
170enum {
171 IS_ALL_MSK = 0xbffffffful,
172 IS_HW_ERR = 1<<31,
173
174 IS_PA_TO_RX1 = 1<<29,
175 IS_PA_TO_RX2 = 1<<28,
176 IS_PA_TO_TX1 = 1<<27,
177 IS_PA_TO_TX2 = 1<<26,
178 IS_I2C_READY = 1<<25,
179 IS_IRQ_SW = 1<<24,
180 IS_EXT_REG = 1<<23,
181
182 IS_TIMINT = 1<<22,
183 IS_MAC1 = 1<<21,
184 IS_LNK_SYNC_M1 = 1<<20,
185 IS_MAC2 = 1<<19,
186 IS_LNK_SYNC_M2 = 1<<18,
187
188 IS_R1_B = 1<<17,
189 IS_R1_F = 1<<16,
190 IS_R1_C = 1<<15,
191
192 IS_R2_B = 1<<14,
193 IS_R2_F = 1<<13,
194 IS_R2_C = 1<<12,
195
196 IS_XS1_B = 1<<11,
197 IS_XS1_F = 1<<10,
198 IS_XS1_C = 1<<9,
199
200 IS_XA1_B = 1<<8,
201 IS_XA1_F = 1<<7,
202 IS_XA1_C = 1<<6,
203
204 IS_XS2_B = 1<<5,
205 IS_XS2_F = 1<<4,
206 IS_XS2_C = 1<<3,
207
208 IS_XA2_B = 1<<2,
209 IS_XA2_F = 1<<1,
210 IS_XA2_C = 1<<0,
211
212 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
213 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
214
215 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
216 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
217};
218
219
220
221enum {
222 IS_IRQ_TIST_OV = 1<<13,
223 IS_IRQ_SENSOR = 1<<12,
224 IS_IRQ_MST_ERR = 1<<11,
225 IS_IRQ_STAT = 1<<10,
226 IS_NO_STAT_M1 = 1<<9,
227 IS_NO_STAT_M2 = 1<<8,
228 IS_NO_TIST_M1 = 1<<7,
229 IS_NO_TIST_M2 = 1<<6,
230 IS_RAM_RD_PAR = 1<<5,
231 IS_RAM_WR_PAR = 1<<4,
232 IS_M1_PAR_ERR = 1<<3,
233 IS_M2_PAR_ERR = 1<<2,
234 IS_R1_PAR_ERR = 1<<1,
235 IS_R2_PAR_ERR = 1<<0,
236
237 IS_ERR_MSK = IS_IRQ_MST_ERR | IS_IRQ_STAT
238 | IS_RAM_RD_PAR | IS_RAM_WR_PAR
239 | IS_M1_PAR_ERR | IS_M2_PAR_ERR
240 | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
241};
242
243
244enum {
245 TST_FRC_DPERR_MR = 1<<7,
246 TST_FRC_DPERR_MW = 1<<6,
247 TST_FRC_DPERR_TR = 1<<5,
248 TST_FRC_DPERR_TW = 1<<4,
249 TST_FRC_APERR_M = 1<<3,
250 TST_FRC_APERR_T = 1<<2,
251 TST_CFG_WRITE_ON = 1<<1,
252 TST_CFG_WRITE_OFF= 1<<0,
253};
254
255
256enum {
257 CFG_CHIP_R_MSK = 0xf<<4,
258
259 CFG_DIS_M2_CLK = 1<<1,
260 CFG_SNG_MAC = 1<<0,
261};
262
263
264enum {
265 CHIP_ID_GENESIS = 0x0a,
266 CHIP_ID_YUKON = 0xb0,
267 CHIP_ID_YUKON_LITE = 0xb1,
268 CHIP_ID_YUKON_LP = 0xb2,
269 CHIP_ID_YUKON_XL = 0xb3,
270 CHIP_ID_YUKON_EC = 0xb6,
271 CHIP_ID_YUKON_FE = 0xb7,
272
273 CHIP_REV_YU_LITE_A1 = 3,
274 CHIP_REV_YU_LITE_A3 = 7,
275};
276
277
278
279enum {
280 TIM_START = 1<<2,
281 TIM_STOP = 1<<1,
282 TIM_CLR_IRQ = 1<<0,
283};
284
285
286
287
288enum {
289 TIM_T_ON = 1<<2,
290 TIM_T_OFF = 1<<1,
291 TIM_T_STEP = 1<<0,
292};
293
294
295enum {
296 GP_DIR_9 = 1<<25,
297 GP_DIR_8 = 1<<24,
298 GP_DIR_7 = 1<<23,
299 GP_DIR_6 = 1<<22,
300 GP_DIR_5 = 1<<21,
301 GP_DIR_4 = 1<<20,
302 GP_DIR_3 = 1<<19,
303 GP_DIR_2 = 1<<18,
304 GP_DIR_1 = 1<<17,
305 GP_DIR_0 = 1<<16,
306
307 GP_IO_9 = 1<<9,
308 GP_IO_8 = 1<<8,
309 GP_IO_7 = 1<<7,
310 GP_IO_6 = 1<<6,
311 GP_IO_5 = 1<<5,
312 GP_IO_4 = 1<<4,
313 GP_IO_3 = 1<<3,
314 GP_IO_2 = 1<<2,
315 GP_IO_1 = 1<<1,
316 GP_IO_0 = 1<<0,
317};
318
319
320
321
322enum {
323 BMU_OWN = 1<<31,
324 BMU_STF = 1<<30,
325 BMU_EOF = 1<<29,
326 BMU_IRQ_EOB = 1<<28,
327 BMU_IRQ_EOF = 1<<27,
328
329 BMU_STFWD = 1<<26,
330 BMU_NO_FCS = 1<<25,
331 BMU_SW = 1<<24,
332
333 BMU_DEV_0 = 1<<26,
334 BMU_STAT_VAL = 1<<25,
335 BMU_TIST_VAL = 1<<24,
336
337 BMU_CHECK = 0x55<<16,
338 BMU_TCP_CHECK = 0x56<<16,
339 BMU_UDP_CHECK = 0x57<<16,
340 BMU_BBC = 0xffffL,
341};
342
343
344enum {
345 BSC_START = 1<<1,
346 BSC_STOP = 1<<0,
347};
348
349
350enum {
351 BSC_SRC = 1<<0,
352};
353
354
355enum {
356 BSC_T_ON = 1<<2,
357 BSC_T_OFF = 1<<1,
358 BSC_T_STEP = 1<<0,
359};
360
361
362
363#define RAM_ADR_RAN 0x0007ffffL
364
365
366
367enum {
368 RI_CLR_RD_PERR = 1<<9,
369 RI_CLR_WR_PERR = 1<<8,
370
371 RI_RST_CLR = 1<<1,
372 RI_RST_SET = 1<<0,
373};
374
375
376
377enum {
378 MA_FOE_ON = 1<<3,
379 MA_FOE_OFF = 1<<2,
380 MA_RST_CLR = 1<<1,
381 MA_RST_SET = 1<<0,
382
383};
384
385
386#define SK_MAC_TO_53 72
387#define SK_PKT_TO_53 0x2000
388#define SK_PKT_TO_MAX 0xffff
389#define SK_RI_TO_53 36
390
391
392
393enum {
394 PA_CLR_TO_TX2 = 1<<13,
395 PA_CLR_TO_TX1 = 1<<12,
396 PA_CLR_TO_RX2 = 1<<11,
397 PA_CLR_TO_RX1 = 1<<10,
398 PA_ENA_TO_TX2 = 1<<9,
399 PA_DIS_TO_TX2 = 1<<8,
400 PA_ENA_TO_TX1 = 1<<7,
401 PA_DIS_TO_TX1 = 1<<6,
402 PA_ENA_TO_RX2 = 1<<5,
403 PA_DIS_TO_RX2 = 1<<4,
404 PA_ENA_TO_RX1 = 1<<3,
405 PA_DIS_TO_RX1 = 1<<2,
406 PA_RST_CLR = 1<<1,
407 PA_RST_SET = 1<<0,
408};
409
410#define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
411 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
412
413
414
415
416
417
418
419
420#define TXA_MAX_VAL 0x00ffffffUL
421
422
423enum {
424 TXA_ENA_FSYNC = 1<<7,
425 TXA_DIS_FSYNC = 1<<6,
426 TXA_ENA_ALLOC = 1<<5,
427 TXA_DIS_ALLOC = 1<<4,
428 TXA_START_RC = 1<<3,
429 TXA_STOP_RC = 1<<2,
430 TXA_ENA_ARB = 1<<1,
431 TXA_DIS_ARB = 1<<0,
432};
433
434
435
436
437
438enum {
439 TXA_ITI_INI = 0x0200,
440 TXA_ITI_VAL = 0x0204,
441 TXA_LIM_INI = 0x0208,
442 TXA_LIM_VAL = 0x020c,
443 TXA_CTRL = 0x0210,
444 TXA_TEST = 0x0211,
445 TXA_STAT = 0x0212,
446};
447
448
449enum {
450 B6_EXT_REG = 0x0300,
451 B7_CFG_SPC = 0x0380,
452 B8_RQ1_REGS = 0x0400,
453 B8_RQ2_REGS = 0x0480,
454 B8_TS1_REGS = 0x0600,
455 B8_TA1_REGS = 0x0680,
456 B8_TS2_REGS = 0x0700,
457 B8_TA2_REGS = 0x0780,
458 B16_RAM_REGS = 0x0800,
459};
460
461
462enum {
463 B8_Q_REGS = 0x0400,
464 Q_D = 0x00,
465 Q_DA_L = 0x20,
466 Q_DA_H = 0x24,
467 Q_AC_L = 0x28,
468 Q_AC_H = 0x2c,
469 Q_BC = 0x30,
470 Q_CSR = 0x34,
471 Q_F = 0x38,
472 Q_T1 = 0x3c,
473 Q_T1_TR = 0x3c,
474 Q_T1_WR = 0x3d,
475 Q_T1_RD = 0x3e,
476 Q_T1_SV = 0x3f,
477 Q_T2 = 0x40,
478 Q_T3 = 0x44,
479
480};
481#define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
482
483
484enum {
485
486 RB_START= 0x00,
487 RB_END = 0x04,
488 RB_WP = 0x08,
489 RB_RP = 0x0c,
490 RB_RX_UTPP= 0x10,
491 RB_RX_LTPP= 0x14,
492 RB_RX_UTHP= 0x18,
493 RB_RX_LTHP= 0x1c,
494
495 RB_PC = 0x20,
496 RB_LEV = 0x24,
497 RB_CTRL = 0x28,
498 RB_TST1 = 0x29,
499 RB_TST2 = 0x2a,
500};
501
502
503enum {
504 Q_R1 = 0x0000,
505 Q_R2 = 0x0080,
506 Q_XS1 = 0x0200,
507 Q_XA1 = 0x0280,
508 Q_XS2 = 0x0300,
509 Q_XA2 = 0x0380,
510};
511
512
513enum {
514 SK_MAC_XMAC = 0,
515 SK_MAC_GMAC = 1,
516};
517
518
519enum {
520 SK_PHY_XMAC = 0,
521 SK_PHY_BCOM = 1,
522 SK_PHY_LONE = 2,
523 SK_PHY_NAT = 3,
524 SK_PHY_MARV_COPPER= 4,
525 SK_PHY_MARV_FIBER = 5,
526};
527
528
529enum {
530 PHY_ADDR_XMAC = 0<<8,
531 PHY_ADDR_BCOM = 1<<8,
532
533
534 PHY_ADDR_MARV = 0,
535};
536
537#define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
538
539
540enum {
541 RX_MFF_EA = 0x0c00,
542 RX_MFF_WP = 0x0c04,
543
544 RX_MFF_RP = 0x0c0c,
545 RX_MFF_PC = 0x0c10,
546 RX_MFF_LEV = 0x0c14,
547 RX_MFF_CTRL1 = 0x0c18,
548 RX_MFF_STAT_TO = 0x0c1a,
549 RX_MFF_TIST_TO = 0x0c1b,
550 RX_MFF_CTRL2 = 0x0c1c,
551 RX_MFF_TST1 = 0x0c1d,
552 RX_MFF_TST2 = 0x0c1e,
553
554 RX_LED_INI = 0x0c20,
555 RX_LED_VAL = 0x0c24,
556 RX_LED_CTRL = 0x0c28,
557 RX_LED_TST = 0x0c29,
558
559 LNK_SYNC_INI = 0x0c30,
560 LNK_SYNC_VAL = 0x0c34,
561 LNK_SYNC_CTRL = 0x0c38,
562 LNK_SYNC_TST = 0x0c39,
563 LNK_LED_REG = 0x0c3c,
564};
565
566
567
568enum {
569 MFF_ENA_RDY_PAT = 1<<13,
570 MFF_DIS_RDY_PAT = 1<<12,
571 MFF_ENA_TIM_PAT = 1<<11,
572 MFF_DIS_TIM_PAT = 1<<10,
573 MFF_ENA_ALM_FUL = 1<<9,
574 MFF_DIS_ALM_FUL = 1<<8,
575 MFF_ENA_PAUSE = 1<<7,
576 MFF_DIS_PAUSE = 1<<6,
577 MFF_ENA_FLUSH = 1<<5,
578 MFF_DIS_FLUSH = 1<<4,
579 MFF_ENA_TIST = 1<<3,
580 MFF_DIS_TIST = 1<<2,
581 MFF_CLR_INTIST = 1<<1,
582 MFF_CLR_INSTAT = 1<<0,
583 MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
584};
585
586
587enum {
588 MFF_CLR_PERR = 1<<15,
589
590 MFF_ENA_PKT_REC = 1<<13,
591 MFF_DIS_PKT_REC = 1<<12,
592
593 MFF_ENA_W4E = 1<<7,
594 MFF_DIS_W4E = 1<<6,
595
596 MFF_ENA_LOOPB = 1<<3,
597 MFF_DIS_LOOPB = 1<<2,
598 MFF_CLR_MAC_RST = 1<<1,
599 MFF_SET_MAC_RST = 1<<0,
600
601 MFF_TX_CTRL_DEF = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
602};
603
604
605
606
607enum {
608 MFF_WSP_T_ON = 1<<6,
609 MFF_WSP_T_OFF = 1<<5,
610 MFF_WSP_INC = 1<<4,
611 MFF_PC_DEC = 1<<3,
612 MFF_PC_T_ON = 1<<2,
613 MFF_PC_T_OFF = 1<<1,
614 MFF_PC_INC = 1<<0,
615};
616
617
618
619enum {
620 MFF_WP_T_ON = 1<<6,
621 MFF_WP_T_OFF = 1<<5,
622 MFF_WP_INC = 1<<4,
623
624 MFF_RP_T_ON = 1<<2,
625 MFF_RP_T_OFF = 1<<1,
626 MFF_RP_DEC = 1<<0,
627};
628
629
630
631enum {
632 MFF_ENA_OP_MD = 1<<3,
633 MFF_DIS_OP_MD = 1<<2,
634 MFF_RST_CLR = 1<<1,
635 MFF_RST_SET = 1<<0,
636};
637
638
639
640
641
642
643
644enum {
645 LED_START = 1<<2,
646 LED_STOP = 1<<1,
647 LED_STATE = 1<<0,
648};
649
650
651
652
653enum {
654 LED_T_ON = 1<<2,
655 LED_T_OFF = 1<<1,
656 LED_T_STEP = 1<<0,
657};
658
659
660enum {
661 LED_BLK_ON = 1<<5,
662 LED_BLK_OFF = 1<<4,
663 LED_SYNC_ON = 1<<3,
664 LED_SYNC_OFF = 1<<2,
665 LED_ON = 1<<1,
666 LED_OFF = 1<<0,
667};
668
669
670enum {
671 RX_GMF_EA = 0x0c40,
672 RX_GMF_AF_THR = 0x0c44,
673 RX_GMF_CTRL_T = 0x0c48,
674 RX_GMF_FL_MSK = 0x0c4c,
675 RX_GMF_FL_THR = 0x0c50,
676 RX_GMF_WP = 0x0c60,
677 RX_GMF_WLEV = 0x0c68,
678 RX_GMF_RP = 0x0c70,
679 RX_GMF_RLEV = 0x0c78,
680};
681
682
683
684enum {
685 TXA_INT_T_ON = 1<<5,
686 TXA_INT_T_OFF = 1<<4,
687 TXA_INT_T_STEP = 1<<3,
688 TXA_LIM_T_ON = 1<<2,
689 TXA_LIM_T_OFF = 1<<1,
690 TXA_LIM_T_STEP = 1<<0,
691};
692
693
694enum {
695 TXA_PRIO_XS = 1<<0,
696};
697
698
699
700
701
702
703
704
705
706
707
708
709
710enum {
711 CSR_SV_IDLE = 1<<24,
712
713 CSR_DESC_CLR = 1<<21,
714 CSR_DESC_SET = 1<<20,
715 CSR_FIFO_CLR = 1<<19,
716 CSR_FIFO_SET = 1<<18,
717 CSR_HPI_RUN = 1<<17,
718 CSR_HPI_RST = 1<<16,
719 CSR_SV_RUN = 1<<15,
720 CSR_SV_RST = 1<<14,
721 CSR_DREAD_RUN = 1<<13,
722 CSR_DREAD_RST = 1<<12,
723 CSR_DWRITE_RUN = 1<<11,
724 CSR_DWRITE_RST = 1<<10,
725 CSR_TRANS_RUN = 1<<9,
726 CSR_TRANS_RST = 1<<8,
727 CSR_ENA_POL = 1<<7,
728 CSR_DIS_POL = 1<<6,
729 CSR_STOP = 1<<5,
730 CSR_START = 1<<4,
731 CSR_IRQ_CL_P = 1<<3,
732 CSR_IRQ_CL_B = 1<<2,
733 CSR_IRQ_CL_F = 1<<1,
734 CSR_IRQ_CL_C = 1<<0,
735};
736
737#define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
738 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
739 CSR_TRANS_RST)
740#define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
741 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
742 CSR_TRANS_RUN)
743
744
745enum {
746 F_ALM_FULL = 1<<27,
747 F_EMPTY = 1<<27,
748 F_FIFO_EOF = 1<<26,
749 F_WM_REACHED = 1<<25,
750
751 F_FIFO_LEVEL = 0x1fL<<16,
752 F_WATER_MARK = 0x0007ffL,
753};
754
755
756
757
758
759
760
761
762
763
764
765
766
767#define RB_MSK 0x0007ffff
768
769
770
771
772enum {
773 RB_ENA_STFWD = 1<<5,
774 RB_DIS_STFWD = 1<<4,
775 RB_ENA_OP_MD = 1<<3,
776 RB_DIS_OP_MD = 1<<2,
777 RB_RST_CLR = 1<<1,
778 RB_RST_SET = 1<<0,
779};
780
781
782enum {
783 TX_MFF_EA = 0x0d00,
784 TX_MFF_WP = 0x0d04,
785 TX_MFF_WSP = 0x0d08,
786 TX_MFF_RP = 0x0d0c,
787 TX_MFF_PC = 0x0d10,
788 TX_MFF_LEV = 0x0d14,
789 TX_MFF_CTRL1 = 0x0d18,
790 TX_MFF_WAF = 0x0d1a,
791
792 TX_MFF_CTRL2 = 0x0d1c,
793 TX_MFF_TST1 = 0x0d1d,
794 TX_MFF_TST2 = 0x0d1e,
795
796 TX_LED_INI = 0x0d20,
797 TX_LED_VAL = 0x0d24,
798 TX_LED_CTRL = 0x0d28,
799 TX_LED_TST = 0x0d29,
800};
801
802
803#define SK_XMIT_DUR 0x002faf08UL
804#define SK_BLK_DUR 0x01dcd650UL
805
806#define SK_DPOLL_DEF 0x00ee6b28UL
807
808#define SK_DPOLL_MAX 0x00ffffffUL
809
810
811#define SK_FACT_62 100
812#define SK_FACT_53 85
813#define SK_FACT_78 125
814
815
816
817enum {
818 TX_GMF_EA = 0x0d40,
819 TX_GMF_AE_THR = 0x0d44,
820 TX_GMF_CTRL_T = 0x0d48,
821
822 TX_GMF_WP = 0x0d60,
823 TX_GMF_WSP = 0x0d64,
824 TX_GMF_WLEV = 0x0d68,
825
826 TX_GMF_RP = 0x0d70,
827 TX_GMF_RSTP = 0x0d74,
828 TX_GMF_RLEV = 0x0d78,
829
830
831 B28_DPT_INI = 0x0e00,
832 B28_DPT_VAL = 0x0e04,
833 B28_DPT_CTRL = 0x0e08,
834
835 B28_DPT_TST = 0x0e0a,
836
837
838 GMAC_TI_ST_VAL = 0x0e14,
839 GMAC_TI_ST_CTRL = 0x0e18,
840 GMAC_TI_ST_TST = 0x0e1a,
841};
842
843
844enum {
845 LINKLED_OFF = 0x01,
846 LINKLED_ON = 0x02,
847 LINKLED_LINKSYNC_OFF = 0x04,
848 LINKLED_LINKSYNC_ON = 0x08,
849 LINKLED_BLINK_OFF = 0x10,
850 LINKLED_BLINK_ON = 0x20,
851};
852
853
854enum {
855 GMAC_CTRL = 0x0f00,
856 GPHY_CTRL = 0x0f04,
857 GMAC_IRQ_SRC = 0x0f08,
858 GMAC_IRQ_MSK = 0x0f0c,
859 GMAC_LINK_CTRL = 0x0f10,
860
861
862
863 WOL_REG_OFFS = 0x20,
864
865 WOL_CTRL_STAT = 0x0f20,
866 WOL_MATCH_CTL = 0x0f22,
867 WOL_MATCH_RES = 0x0f23,
868 WOL_MAC_ADDR = 0x0f24,
869 WOL_PATT_RPTR = 0x0f2c,
870
871
872
873 WOL_PATT_LEN_LO = 0x0f30,
874 WOL_PATT_LEN_HI = 0x0f34,
875
876
877
878 WOL_PATT_CNT_0 = 0x0f38,
879 WOL_PATT_CNT_4 = 0x0f3c,
880};
881#define WOL_REGS(port, x) (x + (port)*0x80)
882
883enum {
884 WOL_PATT_RAM_1 = 0x1000,
885 WOL_PATT_RAM_2 = 0x1400,
886};
887#define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
888
889enum {
890 BASE_XMAC_1 = 0x2000,
891 BASE_GMAC_1 = 0x2800,
892 BASE_XMAC_2 = 0x3000,
893 BASE_GMAC_2 = 0x3800,
894};
895
896
897
898
899enum {
900 XMR_FS_LEN = 0x3fff<<18,
901 XMR_FS_LEN_SHIFT = 18,
902 XMR_FS_2L_VLAN = 1<<17,
903 XMR_FS_1_VLAN = 1<<16,
904 XMR_FS_BC = 1<<15,
905 XMR_FS_MC = 1<<14,
906 XMR_FS_UC = 1<<13,
907
908 XMR_FS_BURST = 1<<11,
909 XMR_FS_CEX_ERR = 1<<10,
910 XMR_FS_802_3 = 1<<9,
911 XMR_FS_COL_ERR = 1<<8,
912 XMR_FS_CAR_ERR = 1<<7,
913 XMR_FS_LEN_ERR = 1<<6,
914 XMR_FS_FRA_ERR = 1<<5,
915 XMR_FS_RUNT = 1<<4,
916 XMR_FS_LNG_ERR = 1<<3,
917 XMR_FS_FCS_ERR = 1<<2,
918 XMR_FS_ERR = 1<<1,
919 XMR_FS_MCTRL = 1<<0,
920
921
922
923
924
925
926
927
928
929};
930
931
932
933
934enum {
935 PHY_XMAC_CTRL = 0x00,
936 PHY_XMAC_STAT = 0x01,
937 PHY_XMAC_ID0 = 0x02,
938 PHY_XMAC_ID1 = 0x03,
939 PHY_XMAC_AUNE_ADV = 0x04,
940 PHY_XMAC_AUNE_LP = 0x05,
941 PHY_XMAC_AUNE_EXP = 0x06,
942 PHY_XMAC_NEPG = 0x07,
943 PHY_XMAC_NEPG_LP = 0x08,
944
945 PHY_XMAC_EXT_STAT = 0x0f,
946 PHY_XMAC_RES_ABI = 0x10,
947};
948
949
950
951enum {
952 PHY_BCOM_CTRL = 0x00,
953 PHY_BCOM_STAT = 0x01,
954 PHY_BCOM_ID0 = 0x02,
955 PHY_BCOM_ID1 = 0x03,
956 PHY_BCOM_AUNE_ADV = 0x04,
957 PHY_BCOM_AUNE_LP = 0x05,
958 PHY_BCOM_AUNE_EXP = 0x06,
959 PHY_BCOM_NEPG = 0x07,
960 PHY_BCOM_NEPG_LP = 0x08,
961
962 PHY_BCOM_1000T_CTRL = 0x09,
963 PHY_BCOM_1000T_STAT = 0x0a,
964 PHY_BCOM_EXT_STAT = 0x0f,
965 PHY_BCOM_P_EXT_CTRL = 0x10,
966 PHY_BCOM_P_EXT_STAT = 0x11,
967 PHY_BCOM_RE_CTR = 0x12,
968 PHY_BCOM_FC_CTR = 0x13,
969 PHY_BCOM_RNO_CTR = 0x14,
970
971 PHY_BCOM_AUX_CTRL = 0x18,
972 PHY_BCOM_AUX_STAT = 0x19,
973 PHY_BCOM_INT_STAT = 0x1a,
974 PHY_BCOM_INT_MASK = 0x1b,
975};
976
977
978
979
980enum {
981 PHY_MARV_CTRL = 0x00,
982 PHY_MARV_STAT = 0x01,
983 PHY_MARV_ID0 = 0x02,
984 PHY_MARV_ID1 = 0x03,
985 PHY_MARV_AUNE_ADV = 0x04,
986 PHY_MARV_AUNE_LP = 0x05,
987 PHY_MARV_AUNE_EXP = 0x06,
988 PHY_MARV_NEPG = 0x07,
989 PHY_MARV_NEPG_LP = 0x08,
990
991 PHY_MARV_1000T_CTRL = 0x09,
992 PHY_MARV_1000T_STAT = 0x0a,
993 PHY_MARV_EXT_STAT = 0x0f,
994 PHY_MARV_PHY_CTRL = 0x10,
995 PHY_MARV_PHY_STAT = 0x11,
996 PHY_MARV_INT_MASK = 0x12,
997 PHY_MARV_INT_STAT = 0x13,
998 PHY_MARV_EXT_CTRL = 0x14,
999 PHY_MARV_RXE_CNT = 0x15,
1000 PHY_MARV_EXT_ADR = 0x16,
1001 PHY_MARV_PORT_IRQ = 0x17,
1002 PHY_MARV_LED_CTRL = 0x18,
1003 PHY_MARV_LED_OVER = 0x19,
1004 PHY_MARV_EXT_CTRL_2 = 0x1a,
1005 PHY_MARV_EXT_P_STAT = 0x1b,
1006 PHY_MARV_CABLE_DIAG = 0x1c,
1007 PHY_MARV_PAGE_ADDR = 0x1d,
1008 PHY_MARV_PAGE_DATA = 0x1e,
1009
1010
1011 PHY_MARV_FE_LED_PAR = 0x16,
1012 PHY_MARV_FE_LED_SER = 0x17,
1013 PHY_MARV_FE_VCT_TX = 0x1a,
1014 PHY_MARV_FE_VCT_RX = 0x1b,
1015 PHY_MARV_FE_SPEC_2 = 0x1c,
1016};
1017
1018enum {
1019 PHY_CT_RESET = 1<<15,
1020 PHY_CT_LOOP = 1<<14,
1021 PHY_CT_SPS_LSB = 1<<13,
1022 PHY_CT_ANE = 1<<12,
1023 PHY_CT_PDOWN = 1<<11,
1024 PHY_CT_ISOL = 1<<10,
1025 PHY_CT_RE_CFG = 1<<9,
1026 PHY_CT_DUP_MD = 1<<8,
1027 PHY_CT_COL_TST = 1<<7,
1028 PHY_CT_SPS_MSB = 1<<6,
1029};
1030
1031enum {
1032 PHY_CT_SP1000 = PHY_CT_SPS_MSB,
1033 PHY_CT_SP100 = PHY_CT_SPS_LSB,
1034 PHY_CT_SP10 = 0,
1035};
1036
1037enum {
1038 PHY_ST_EXT_ST = 1<<8,
1039
1040 PHY_ST_PRE_SUP = 1<<6,
1041 PHY_ST_AN_OVER = 1<<5,
1042 PHY_ST_REM_FLT = 1<<4,
1043 PHY_ST_AN_CAP = 1<<3,
1044 PHY_ST_LSYNC = 1<<2,
1045 PHY_ST_JAB_DET = 1<<1,
1046 PHY_ST_EXT_REG = 1<<0,
1047};
1048
1049enum {
1050 PHY_I1_OUI_MSK = 0x3f<<10,
1051 PHY_I1_MOD_NUM = 0x3f<<4,
1052 PHY_I1_REV_MSK = 0xf,
1053};
1054
1055
1056enum {
1057 PHY_BCOM_ID1_A1 = 0x6041,
1058 PHY_BCOM_ID1_B2 = 0x6043,
1059 PHY_BCOM_ID1_C0 = 0x6044,
1060 PHY_BCOM_ID1_C5 = 0x6047,
1061};
1062
1063
1064enum {
1065 PHY_MARV_ID0_VAL= 0x0141,
1066 PHY_MARV_ID1_B0 = 0x0C23,
1067 PHY_MARV_ID1_B2 = 0x0C25,
1068 PHY_MARV_ID1_C2 = 0x0CC2,
1069 PHY_MARV_ID1_Y2 = 0x0C91,
1070};
1071
1072
1073enum {
1074 PHY_AN_NXT_PG = 1<<15,
1075 PHY_AN_ACK = 1<<14,
1076 PHY_AN_RF = 1<<13,
1077
1078 PHY_AN_PAUSE_ASYM = 1<<11,
1079 PHY_AN_PAUSE_CAP = 1<<10,
1080 PHY_AN_100BASE4 = 1<<9,
1081 PHY_AN_100FULL = 1<<8,
1082 PHY_AN_100HALF = 1<<7,
1083 PHY_AN_10FULL = 1<<6,
1084 PHY_AN_10HALF = 1<<5,
1085 PHY_AN_CSMA = 1<<0,
1086 PHY_AN_SEL = 0x1f,
1087 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1088 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1089 PHY_AN_100HALF | PHY_AN_100FULL,
1090};
1091
1092
1093enum {
1094 PHY_X_AN_NXT_PG = 1<<15,
1095 PHY_X_AN_ACK = 1<<14,
1096 PHY_X_AN_RFB = 3<<12,
1097
1098 PHY_X_AN_PAUSE = 3<<7,
1099 PHY_X_AN_HD = 1<<6,
1100 PHY_X_AN_FD = 1<<5,
1101};
1102
1103
1104enum {
1105 PHY_X_P_NO_PAUSE= 0<<7,
1106 PHY_X_P_SYM_MD = 1<<7,
1107 PHY_X_P_ASYM_MD = 2<<7,
1108 PHY_X_P_BOTH_MD = 3<<7,
1109};
1110
1111
1112
1113enum {
1114 PHY_X_EX_FD = 1<<15,
1115 PHY_X_EX_HD = 1<<14,
1116};
1117
1118
1119enum {
1120 PHY_X_RS_PAUSE = 3<<7,
1121 PHY_X_RS_HD = 1<<6,
1122 PHY_X_RS_FD = 1<<5,
1123 PHY_X_RS_ABLMIS = 1<<4,
1124 PHY_X_RS_PAUMIS = 1<<3,
1125};
1126
1127
1128enum {
1129 X_RFB_OK = 0<<12,
1130 X_RFB_LF = 1<<12,
1131 X_RFB_OFF = 2<<12,
1132 X_RFB_AN_ERR = 3<<12,
1133};
1134
1135
1136
1137enum {
1138 PHY_B_1000C_TEST = 7<<13,
1139 PHY_B_1000C_MSE = 1<<12,
1140 PHY_B_1000C_MSC = 1<<11,
1141 PHY_B_1000C_RD = 1<<10,
1142 PHY_B_1000C_AFD = 1<<9,
1143 PHY_B_1000C_AHD = 1<<8,
1144};
1145
1146
1147
1148enum {
1149 PHY_B_1000S_MSF = 1<<15,
1150 PHY_B_1000S_MSR = 1<<14,
1151 PHY_B_1000S_LRS = 1<<13,
1152 PHY_B_1000S_RRS = 1<<12,
1153 PHY_B_1000S_LP_FD = 1<<11,
1154 PHY_B_1000S_LP_HD = 1<<10,
1155
1156 PHY_B_1000S_IEC = 0xff,
1157};
1158
1159
1160enum {
1161 PHY_B_ES_X_FD_CAP = 1<<15,
1162 PHY_B_ES_X_HD_CAP = 1<<14,
1163 PHY_B_ES_T_FD_CAP = 1<<13,
1164 PHY_B_ES_T_HD_CAP = 1<<12,
1165};
1166
1167
1168enum {
1169 PHY_B_PEC_MAC_PHY = 1<<15,
1170 PHY_B_PEC_DIS_CROSS = 1<<14,
1171 PHY_B_PEC_TX_DIS = 1<<13,
1172 PHY_B_PEC_INT_DIS = 1<<12,
1173 PHY_B_PEC_F_INT = 1<<11,
1174 PHY_B_PEC_BY_45 = 1<<10,
1175 PHY_B_PEC_BY_SCR = 1<<9,
1176 PHY_B_PEC_BY_MLT3 = 1<<8,
1177 PHY_B_PEC_BY_RXA = 1<<7,
1178 PHY_B_PEC_RES_SCR = 1<<6,
1179 PHY_B_PEC_EN_LTR = 1<<5,
1180 PHY_B_PEC_LED_ON = 1<<4,
1181 PHY_B_PEC_LED_OFF = 1<<3,
1182 PHY_B_PEC_EX_IPG = 1<<2,
1183 PHY_B_PEC_3_LED = 1<<1,
1184 PHY_B_PEC_HIGH_LA = 1<<0,
1185};
1186
1187
1188enum {
1189 PHY_B_PES_CROSS_STAT = 1<<13,
1190 PHY_B_PES_INT_STAT = 1<<12,
1191 PHY_B_PES_RRS = 1<<11,
1192 PHY_B_PES_LRS = 1<<10,
1193 PHY_B_PES_LOCKED = 1<<9,
1194 PHY_B_PES_LS = 1<<8,
1195 PHY_B_PES_RF = 1<<7,
1196 PHY_B_PES_CE_ER = 1<<6,
1197 PHY_B_PES_BAD_SSD = 1<<5,
1198 PHY_B_PES_BAD_ESD = 1<<4,
1199 PHY_B_PES_RX_ER = 1<<3,
1200 PHY_B_PES_TX_ER = 1<<2,
1201 PHY_B_PES_LOCK_ER = 1<<1,
1202 PHY_B_PES_MLT3_ER = 1<<0,
1203};
1204
1205
1206
1207enum {
1208 PHY_B_AN_RF = 1<<13,
1209
1210 PHY_B_AN_ASP = 1<<11,
1211 PHY_B_AN_PC = 1<<10,
1212};
1213
1214
1215
1216enum {
1217 PHY_B_FC_CTR = 0xff,
1218
1219
1220 PHY_B_RC_LOC_MSK = 0xff00,
1221 PHY_B_RC_REM_MSK = 0x00ff,
1222
1223
1224 PHY_B_AC_L_SQE = 1<<15,
1225 PHY_B_AC_LONG_PACK = 1<<14,
1226 PHY_B_AC_ER_CTRL = 3<<12,
1227
1228 PHY_B_AC_TX_TST = 1<<10,
1229
1230 PHY_B_AC_DIS_PRF = 1<<7,
1231
1232 PHY_B_AC_DIS_PM = 1<<5,
1233
1234 PHY_B_AC_DIAG = 1<<3,
1235};
1236
1237
1238enum {
1239 PHY_B_AS_AN_C = 1<<15,
1240 PHY_B_AS_AN_CA = 1<<14,
1241 PHY_B_AS_ANACK_D = 1<<13,
1242 PHY_B_AS_ANAB_D = 1<<12,
1243 PHY_B_AS_NPW = 1<<11,
1244 PHY_B_AS_AN_RES_MSK = 7<<8,
1245 PHY_B_AS_PDF = 1<<7,
1246 PHY_B_AS_RF = 1<<6,
1247 PHY_B_AS_ANP_R = 1<<5,
1248 PHY_B_AS_LP_ANAB = 1<<4,
1249 PHY_B_AS_LP_NPAB = 1<<3,
1250 PHY_B_AS_LS = 1<<2,
1251 PHY_B_AS_PRR = 1<<1,
1252 PHY_B_AS_PRT = 1<<0,
1253};
1254#define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1255
1256
1257
1258enum {
1259 PHY_B_IS_PSE = 1<<14,
1260 PHY_B_IS_MDXI_SC = 1<<13,
1261 PHY_B_IS_HCT = 1<<12,
1262 PHY_B_IS_LCT = 1<<11,
1263 PHY_B_IS_AN_PR = 1<<10,
1264 PHY_B_IS_NO_HDCL = 1<<9,
1265 PHY_B_IS_NO_HDC = 1<<8,
1266 PHY_B_IS_NEG_USHDC = 1<<7,
1267 PHY_B_IS_SCR_S_ER = 1<<6,
1268 PHY_B_IS_RRS_CHANGE = 1<<5,
1269 PHY_B_IS_LRS_CHANGE = 1<<4,
1270 PHY_B_IS_DUP_CHANGE = 1<<3,
1271 PHY_B_IS_LSP_CHANGE = 1<<2,
1272 PHY_B_IS_LST_CHANGE = 1<<1,
1273 PHY_B_IS_CRC_ER = 1<<0,
1274};
1275#define PHY_B_DEF_MSK \
1276 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1277 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1278
1279
1280enum {
1281 PHY_B_P_NO_PAUSE = 0<<10,
1282 PHY_B_P_SYM_MD = 1<<10,
1283 PHY_B_P_ASYM_MD = 2<<10,
1284 PHY_B_P_BOTH_MD = 3<<10,
1285};
1286
1287
1288
1289enum {
1290 PHY_B_RES_1000FD = 7<<8,
1291 PHY_B_RES_1000HD = 6<<8,
1292};
1293
1294
1295enum {
1296 PHY_M_AN_NXT_PG = 1<<15,
1297 PHY_M_AN_ACK = 1<<14,
1298 PHY_M_AN_RF = 1<<13,
1299
1300 PHY_M_AN_ASP = 1<<11,
1301 PHY_M_AN_PC = 1<<10,
1302 PHY_M_AN_100_T4 = 1<<9,
1303 PHY_M_AN_100_FD = 1<<8,
1304 PHY_M_AN_100_HD = 1<<7,
1305 PHY_M_AN_10_FD = 1<<6,
1306 PHY_M_AN_10_HD = 1<<5,
1307 PHY_M_AN_SEL_MSK =0x1f<<4,
1308};
1309
1310
1311enum {
1312 PHY_M_AN_ASP_X = 1<<8,
1313 PHY_M_AN_PC_X = 1<<7,
1314 PHY_M_AN_1000X_AHD = 1<<6,
1315 PHY_M_AN_1000X_AFD = 1<<5,
1316};
1317
1318
1319enum {
1320 PHY_M_P_NO_PAUSE_X = 0<<7,
1321 PHY_M_P_SYM_MD_X = 1<<7,
1322 PHY_M_P_ASYM_MD_X = 2<<7,
1323 PHY_M_P_BOTH_MD_X = 3<<7,
1324};
1325
1326
1327enum {
1328 PHY_M_1000C_TEST= 7<<13,
1329 PHY_M_1000C_MSE = 1<<12,
1330 PHY_M_1000C_MSC = 1<<11,
1331 PHY_M_1000C_MPD = 1<<10,
1332 PHY_M_1000C_AFD = 1<<9,
1333 PHY_M_1000C_AHD = 1<<8,
1334};
1335
1336
1337enum {
1338 PHY_M_PC_TX_FFD_MSK = 3<<14,
1339 PHY_M_PC_RX_FFD_MSK = 3<<12,
1340 PHY_M_PC_ASS_CRS_TX = 1<<11,
1341 PHY_M_PC_FL_GOOD = 1<<10,
1342 PHY_M_PC_EN_DET_MSK = 3<<8,
1343 PHY_M_PC_ENA_EXT_D = 1<<7,
1344 PHY_M_PC_MDIX_MSK = 3<<5,
1345 PHY_M_PC_DIS_125CLK = 1<<4,
1346 PHY_M_PC_MAC_POW_UP = 1<<3,
1347 PHY_M_PC_SQE_T_ENA = 1<<2,
1348 PHY_M_PC_POL_R_DIS = 1<<1,
1349 PHY_M_PC_DIS_JABBER = 1<<0,
1350};
1351
1352enum {
1353 PHY_M_PC_EN_DET = 2<<8,
1354 PHY_M_PC_EN_DET_PLUS = 3<<8,
1355};
1356
1357enum {
1358 PHY_M_PC_MAN_MDI = 0,
1359 PHY_M_PC_MAN_MDIX = 1,
1360 PHY_M_PC_ENA_AUTO = 3,
1361};
1362
1363
1364enum {
1365 PHY_M_PC_ENA_DTE_DT = 1<<15,
1366 PHY_M_PC_ENA_ENE_DT = 1<<14,
1367 PHY_M_PC_DIS_NLP_CK = 1<<13,
1368 PHY_M_PC_ENA_LIP_NP = 1<<12,
1369 PHY_M_PC_DIS_NLP_GN = 1<<11,
1370
1371 PHY_M_PC_DIS_SCRAMB = 1<<9,
1372 PHY_M_PC_DIS_FEFI = 1<<8,
1373
1374 PHY_M_PC_SH_TP_SEL = 1<<6,
1375 PHY_M_PC_RX_FD_MSK = 3<<2,
1376};
1377
1378
1379enum {
1380 PHY_M_PS_SPEED_MSK = 3<<14,
1381 PHY_M_PS_SPEED_1000 = 1<<15,
1382 PHY_M_PS_SPEED_100 = 1<<14,
1383 PHY_M_PS_SPEED_10 = 0,
1384 PHY_M_PS_FULL_DUP = 1<<13,
1385 PHY_M_PS_PAGE_REC = 1<<12,
1386 PHY_M_PS_SPDUP_RES = 1<<11,
1387 PHY_M_PS_LINK_UP = 1<<10,
1388 PHY_M_PS_CABLE_MSK = 7<<7,
1389 PHY_M_PS_MDI_X_STAT = 1<<6,
1390 PHY_M_PS_DOWNS_STAT = 1<<5,
1391 PHY_M_PS_ENDET_STAT = 1<<4,
1392 PHY_M_PS_TX_P_EN = 1<<3,
1393 PHY_M_PS_RX_P_EN = 1<<2,
1394 PHY_M_PS_POL_REV = 1<<1,
1395 PHY_M_PS_JABBER = 1<<0,
1396};
1397
1398#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1399
1400
1401enum {
1402 PHY_M_PS_DTE_DETECT = 1<<15,
1403 PHY_M_PS_RES_SPEED = 1<<14,
1404};
1405
1406enum {
1407 PHY_M_IS_AN_ERROR = 1<<15,
1408 PHY_M_IS_LSP_CHANGE = 1<<14,
1409 PHY_M_IS_DUP_CHANGE = 1<<13,
1410 PHY_M_IS_AN_PR = 1<<12,
1411 PHY_M_IS_AN_COMPL = 1<<11,
1412 PHY_M_IS_LST_CHANGE = 1<<10,
1413 PHY_M_IS_SYMB_ERROR = 1<<9,
1414 PHY_M_IS_FALSE_CARR = 1<<8,
1415 PHY_M_IS_FIFO_ERROR = 1<<7,
1416 PHY_M_IS_MDI_CHANGE = 1<<6,
1417 PHY_M_IS_DOWNSH_DET = 1<<5,
1418 PHY_M_IS_END_CHANGE = 1<<4,
1419
1420 PHY_M_IS_DTE_CHANGE = 1<<2,
1421 PHY_M_IS_POL_CHANGE = 1<<1,
1422 PHY_M_IS_JABBER = 1<<0,
1423
1424 PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1425 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1426
1427 PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1428};
1429
1430
1431enum {
1432 PHY_M_EC_ENA_BC_EXT = 1<<15,
1433 PHY_M_EC_ENA_LIN_LB = 1<<14,
1434
1435 PHY_M_EC_DIS_LINK_P = 1<<12,
1436 PHY_M_EC_M_DSC_MSK = 3<<10,
1437
1438 PHY_M_EC_S_DSC_MSK = 3<<8,
1439
1440 PHY_M_EC_M_DSC_MSK2 = 7<<9,
1441
1442 PHY_M_EC_DOWN_S_ENA = 1<<8,
1443
1444 PHY_M_EC_RX_TIM_CT = 1<<7,
1445 PHY_M_EC_MAC_S_MSK = 7<<4,
1446 PHY_M_EC_FIB_AN_ENA = 1<<3,
1447 PHY_M_EC_DTE_D_ENA = 1<<2,
1448 PHY_M_EC_TX_TIM_CT = 1<<1,
1449 PHY_M_EC_TRANS_DIS = 1<<0, };
1450
1451#define PHY_M_EC_M_DSC(x) ((u16)(x)<<10)
1452#define PHY_M_EC_S_DSC(x) ((u16)(x)<<8)
1453#define PHY_M_EC_MAC_S(x) ((u16)(x)<<4)
1454
1455#define PHY_M_EC_M_DSC_2(x) ((u16)(x)<<9)
1456
1457enum {
1458 MAC_TX_CLK_0_MHZ = 2,
1459 MAC_TX_CLK_2_5_MHZ = 6,
1460 MAC_TX_CLK_25_MHZ = 7,
1461};
1462
1463
1464enum {
1465 PHY_M_LEDC_DIS_LED = 1<<15,
1466 PHY_M_LEDC_PULS_MSK = 7<<12,
1467 PHY_M_LEDC_F_INT = 1<<11,
1468 PHY_M_LEDC_BL_R_MSK = 7<<8,
1469 PHY_M_LEDC_DP_C_LSB = 1<<7,
1470 PHY_M_LEDC_TX_C_LSB = 1<<6,
1471 PHY_M_LEDC_LK_C_MSK = 7<<3,
1472
1473};
1474#define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1475#define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1476
1477enum {
1478 PHY_M_LEDC_LINK_MSK = 3<<3,
1479
1480 PHY_M_LEDC_DP_CTRL = 1<<2,
1481 PHY_M_LEDC_DP_C_MSB = 1<<2,
1482 PHY_M_LEDC_RX_CTRL = 1<<1,
1483 PHY_M_LEDC_TX_CTRL = 1<<0,
1484 PHY_M_LEDC_TX_C_MSB = 1<<0,
1485};
1486
1487enum {
1488 PULS_NO_STR = 0,
1489 PULS_21MS = 1,
1490 PULS_42MS = 2,
1491 PULS_84MS = 3,
1492 PULS_170MS = 4,
1493 PULS_340MS = 5,
1494 PULS_670MS = 6,
1495 PULS_1300MS = 7,
1496};
1497
1498
1499enum {
1500 BLINK_42MS = 0,
1501 BLINK_84MS = 1,
1502 BLINK_170MS = 2,
1503 BLINK_340MS = 3,
1504 BLINK_670MS = 4,
1505};
1506
1507
1508#define PHY_M_LED_MO_SGMII(x) ((x)<<14)
1509
1510#define PHY_M_LED_MO_DUP(x) ((x)<<10)
1511#define PHY_M_LED_MO_10(x) ((x)<<8)
1512#define PHY_M_LED_MO_100(x) ((x)<<6)
1513#define PHY_M_LED_MO_1000(x) ((x)<<4)
1514#define PHY_M_LED_MO_RX(x) ((x)<<2)
1515#define PHY_M_LED_MO_TX(x) ((x)<<0)
1516
1517enum {
1518 MO_LED_NORM = 0,
1519 MO_LED_BLINK = 1,
1520 MO_LED_OFF = 2,
1521 MO_LED_ON = 3,
1522};
1523
1524
1525enum {
1526 PHY_M_EC2_FI_IMPED = 1<<6,
1527 PHY_M_EC2_FO_IMPED = 1<<5,
1528 PHY_M_EC2_FO_M_CLK = 1<<4,
1529 PHY_M_EC2_FO_BOOST = 1<<3,
1530 PHY_M_EC2_FO_AM_MSK = 7,
1531};
1532
1533
1534enum {
1535 PHY_M_FC_AUTO_SEL = 1<<15,
1536 PHY_M_FC_AN_REG_ACC = 1<<14,
1537 PHY_M_FC_RESOLUTION = 1<<13,
1538 PHY_M_SER_IF_AN_BP = 1<<12,
1539 PHY_M_SER_IF_BP_ST = 1<<11,
1540 PHY_M_IRQ_POLARITY = 1<<10,
1541 PHY_M_DIS_AUT_MED = 1<<9,
1542
1543
1544 PHY_M_UNDOC1 = 1<<7,
1545 PHY_M_DTE_POW_STAT = 1<<4,
1546 PHY_M_MODE_MASK = 0xf,
1547};
1548
1549
1550enum {
1551 PHY_M_CABD_ENA_TEST = 1<<15,
1552 PHY_M_CABD_DIS_WAIT = 1<<15,
1553
1554 PHY_M_CABD_STAT_MSK = 3<<13,
1555 PHY_M_CABD_AMPL_MSK = 0x1f<<8,
1556
1557 PHY_M_CABD_DIST_MSK = 0xff,
1558};
1559
1560
1561enum {
1562 CABD_STAT_NORMAL= 0,
1563 CABD_STAT_SHORT = 1,
1564 CABD_STAT_OPEN = 2,
1565 CABD_STAT_FAIL = 3,
1566};
1567
1568
1569
1570
1571enum {
1572 PHY_M_FELP_LED2_MSK = 0xf<<8,
1573 PHY_M_FELP_LED1_MSK = 0xf<<4,
1574 PHY_M_FELP_LED0_MSK = 0xf,
1575};
1576
1577#define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1578#define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1579#define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1580
1581enum {
1582 LED_PAR_CTRL_COLX = 0x00,
1583 LED_PAR_CTRL_ERROR = 0x01,
1584 LED_PAR_CTRL_DUPLEX = 0x02,
1585 LED_PAR_CTRL_DP_COL = 0x03,
1586 LED_PAR_CTRL_SPEED = 0x04,
1587 LED_PAR_CTRL_LINK = 0x05,
1588 LED_PAR_CTRL_TX = 0x06,
1589 LED_PAR_CTRL_RX = 0x07,
1590 LED_PAR_CTRL_ACT = 0x08,
1591 LED_PAR_CTRL_LNK_RX = 0x09,
1592 LED_PAR_CTRL_LNK_AC = 0x0a,
1593 LED_PAR_CTRL_ACT_BL = 0x0b,
1594 LED_PAR_CTRL_TX_BL = 0x0c,
1595 LED_PAR_CTRL_RX_BL = 0x0d,
1596 LED_PAR_CTRL_COL_BL = 0x0e,
1597 LED_PAR_CTRL_INACT = 0x0f
1598};
1599
1600
1601enum {
1602 PHY_M_FESC_DIS_WAIT = 1<<2,
1603 PHY_M_FESC_ENA_MCLK = 1<<1,
1604 PHY_M_FESC_SEL_CL_A = 1<<0,
1605};
1606
1607
1608
1609enum {
1610 PHY_M_LEDC_LOS_MSK = 0xf<<12,
1611 PHY_M_LEDC_INIT_MSK = 0xf<<8,
1612 PHY_M_LEDC_STA1_MSK = 0xf<<4,
1613 PHY_M_LEDC_STA0_MSK = 0xf,
1614};
1615
1616#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1617#define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1618#define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1619#define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1620
1621
1622
1623enum {
1624 GM_GP_STAT = 0x0000,
1625 GM_GP_CTRL = 0x0004,
1626 GM_TX_CTRL = 0x0008,
1627 GM_RX_CTRL = 0x000c,
1628 GM_TX_FLOW_CTRL = 0x0010,
1629 GM_TX_PARAM = 0x0014,
1630 GM_SERIAL_MODE = 0x0018,
1631
1632 GM_SRC_ADDR_1L = 0x001c,
1633 GM_SRC_ADDR_1M = 0x0020,
1634 GM_SRC_ADDR_1H = 0x0024,
1635 GM_SRC_ADDR_2L = 0x0028,
1636 GM_SRC_ADDR_2M = 0x002c,
1637 GM_SRC_ADDR_2H = 0x0030,
1638
1639
1640 GM_MC_ADDR_H1 = 0x0034,
1641 GM_MC_ADDR_H2 = 0x0038,
1642 GM_MC_ADDR_H3 = 0x003c,
1643 GM_MC_ADDR_H4 = 0x0040,
1644
1645
1646 GM_TX_IRQ_SRC = 0x0044,
1647 GM_RX_IRQ_SRC = 0x0048,
1648 GM_TR_IRQ_SRC = 0x004c,
1649
1650
1651 GM_TX_IRQ_MSK = 0x0050,
1652 GM_RX_IRQ_MSK = 0x0054,
1653 GM_TR_IRQ_MSK = 0x0058,
1654
1655
1656 GM_SMI_CTRL = 0x0080,
1657 GM_SMI_DATA = 0x0084,
1658 GM_PHY_ADDR = 0x0088,
1659};
1660
1661
1662#define GM_MIB_CNT_BASE 0x0100
1663#define GM_MIB_CNT_SIZE 44
1664
1665
1666
1667
1668
1669enum {
1670 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0,
1671 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8,
1672 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16,
1673 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24,
1674 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32,
1675
1676 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48,
1677 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56,
1678 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64,
1679 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72,
1680 GM_RXF_SHT = GM_MIB_CNT_BASE + 80,
1681 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88,
1682 GM_RXF_64B = GM_MIB_CNT_BASE + 96,
1683 GM_RXF_127B = GM_MIB_CNT_BASE + 104,
1684 GM_RXF_255B = GM_MIB_CNT_BASE + 112,
1685 GM_RXF_511B = GM_MIB_CNT_BASE + 120,
1686 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,
1687 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,
1688 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,
1689 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,
1690 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,
1691
1692 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,
1693
1694 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,
1695 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,
1696 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,
1697 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,
1698 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,
1699 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,
1700 GM_TXF_64B = GM_MIB_CNT_BASE + 240,
1701 GM_TXF_127B = GM_MIB_CNT_BASE + 248,
1702 GM_TXF_255B = GM_MIB_CNT_BASE + 256,
1703 GM_TXF_511B = GM_MIB_CNT_BASE + 264,
1704 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,
1705 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,
1706 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,
1707
1708 GM_TXF_COL = GM_MIB_CNT_BASE + 304,
1709 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,
1710 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,
1711 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,
1712 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,
1713 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,
1714};
1715
1716
1717
1718enum {
1719 GM_GPSR_SPEED = 1<<15,
1720 GM_GPSR_DUPLEX = 1<<14,
1721 GM_GPSR_FC_TX_DIS = 1<<13,
1722 GM_GPSR_LINK_UP = 1<<12,
1723 GM_GPSR_PAUSE = 1<<11,
1724 GM_GPSR_TX_ACTIVE = 1<<10,
1725 GM_GPSR_EXC_COL = 1<<9,
1726 GM_GPSR_LAT_COL = 1<<8,
1727
1728 GM_GPSR_PHY_ST_CH = 1<<5,
1729 GM_GPSR_GIG_SPEED = 1<<4,
1730 GM_GPSR_PART_MODE = 1<<3,
1731 GM_GPSR_FC_RX_DIS = 1<<2,
1732 GM_GPSR_PROM_EN = 1<<1,
1733};
1734
1735
1736enum {
1737 GM_GPCR_PROM_ENA = 1<<14,
1738 GM_GPCR_FC_TX_DIS = 1<<13,
1739 GM_GPCR_TX_ENA = 1<<12,
1740 GM_GPCR_RX_ENA = 1<<11,
1741 GM_GPCR_BURST_ENA = 1<<10,
1742 GM_GPCR_LOOP_ENA = 1<<9,
1743 GM_GPCR_PART_ENA = 1<<8,
1744 GM_GPCR_GIGS_ENA = 1<<7,
1745 GM_GPCR_FL_PASS = 1<<6,
1746 GM_GPCR_DUP_FULL = 1<<5,
1747 GM_GPCR_FC_RX_DIS = 1<<4,
1748 GM_GPCR_SPEED_100 = 1<<3,
1749 GM_GPCR_AU_DUP_DIS = 1<<2,
1750 GM_GPCR_AU_FCT_DIS = 1<<1,
1751 GM_GPCR_AU_SPD_DIS = 1<<0,
1752};
1753
1754#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1755#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1756
1757
1758enum {
1759 GM_TXCR_FORCE_JAM = 1<<15,
1760 GM_TXCR_CRC_DIS = 1<<14,
1761 GM_TXCR_PAD_DIS = 1<<13,
1762 GM_TXCR_COL_THR_MSK = 7<<10,
1763};
1764
1765#define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1766#define TX_COL_DEF 0x04
1767
1768
1769enum {
1770 GM_RXCR_UCF_ENA = 1<<15,
1771 GM_RXCR_MCF_ENA = 1<<14,
1772 GM_RXCR_CRC_DIS = 1<<13,
1773 GM_RXCR_PASS_FC = 1<<12,
1774};
1775
1776
1777enum {
1778 GM_TXPA_JAMLEN_MSK = 0x03<<14,
1779 GM_TXPA_JAMIPG_MSK = 0x1f<<9,
1780 GM_TXPA_JAMDAT_MSK = 0x1f<<4,
1781
1782 TX_JAM_LEN_DEF = 0x03,
1783 TX_JAM_IPG_DEF = 0x0b,
1784 TX_IPG_JAM_DEF = 0x1c,
1785};
1786
1787#define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1788#define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1789#define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1790
1791
1792
1793enum {
1794 GM_SMOD_DATABL_MSK = 0x1f<<11,
1795 GM_SMOD_LIMIT_4 = 1<<10,
1796 GM_SMOD_VLAN_ENA = 1<<9,
1797 GM_SMOD_JUMBO_ENA = 1<<8,
1798 GM_SMOD_IPG_MSK = 0x1f
1799};
1800
1801#define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1802#define DATA_BLIND_DEF 0x04
1803
1804#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1805#define IPG_DATA_DEF 0x1e
1806
1807
1808enum {
1809 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,
1810 GM_SMI_CT_REG_A_MSK = 0x1f<<6,
1811 GM_SMI_CT_OP_RD = 1<<5,
1812 GM_SMI_CT_RD_VAL = 1<<4,
1813 GM_SMI_CT_BUSY = 1<<3,
1814};
1815
1816#define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1817#define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1818
1819
1820enum {
1821 GM_PAR_MIB_CLR = 1<<5,
1822 GM_PAR_MIB_TST = 1<<4,
1823};
1824
1825
1826enum {
1827 GMR_FS_LEN = 0xffff<<16,
1828 GMR_FS_LEN_SHIFT = 16,
1829 GMR_FS_VLAN = 1<<13,
1830 GMR_FS_JABBER = 1<<12,
1831 GMR_FS_UN_SIZE = 1<<11,
1832 GMR_FS_MC = 1<<10,
1833 GMR_FS_BC = 1<<9,
1834 GMR_FS_RX_OK = 1<<8,
1835 GMR_FS_GOOD_FC = 1<<7,
1836 GMR_FS_BAD_FC = 1<<6,
1837 GMR_FS_MII_ERR = 1<<5,
1838 GMR_FS_LONG_ERR = 1<<4,
1839 GMR_FS_FRAGMENT = 1<<3,
1840
1841 GMR_FS_CRC_ERR = 1<<1,
1842 GMR_FS_RX_FF_OV = 1<<0,
1843
1844
1845
1846
1847 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1848 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1849 GMR_FS_JABBER,
1850
1851 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1852 GMR_FS_BAD_FC | GMR_FS_UN_SIZE | GMR_FS_JABBER,
1853};
1854
1855
1856enum {
1857 GMF_WP_TST_ON = 1<<14,
1858 GMF_WP_TST_OFF = 1<<13,
1859 GMF_WP_STEP = 1<<12,
1860
1861 GMF_RP_TST_ON = 1<<10,
1862 GMF_RP_TST_OFF = 1<<9,
1863 GMF_RP_STEP = 1<<8,
1864 GMF_RX_F_FL_ON = 1<<7,
1865 GMF_RX_F_FL_OFF = 1<<6,
1866 GMF_CLI_RX_FO = 1<<5,
1867 GMF_CLI_RX_FC = 1<<4,
1868 GMF_OPER_ON = 1<<3,
1869 GMF_OPER_OFF = 1<<2,
1870 GMF_RST_CLR = 1<<1,
1871 GMF_RST_SET = 1<<0,
1872
1873 RX_GMF_FL_THR_DEF = 0xa,
1874};
1875
1876
1877
1878enum {
1879 GMF_WSP_TST_ON = 1<<18,
1880 GMF_WSP_TST_OFF = 1<<17,
1881 GMF_WSP_STEP = 1<<16,
1882
1883 GMF_CLI_TX_FU = 1<<6,
1884 GMF_CLI_TX_FC = 1<<5,
1885 GMF_CLI_TX_PE = 1<<4,
1886};
1887
1888
1889enum {
1890 GMT_ST_START = 1<<2,
1891 GMT_ST_STOP = 1<<1,
1892 GMT_ST_CLR_IRQ = 1<<0,
1893};
1894
1895
1896enum {
1897 GMC_H_BURST_ON = 1<<7,
1898 GMC_H_BURST_OFF = 1<<6,
1899 GMC_F_LOOPB_ON = 1<<5,
1900 GMC_F_LOOPB_OFF = 1<<4,
1901 GMC_PAUSE_ON = 1<<3,
1902 GMC_PAUSE_OFF = 1<<2,
1903 GMC_RST_CLR = 1<<1,
1904 GMC_RST_SET = 1<<0,
1905};
1906
1907
1908enum {
1909 GPC_SEL_BDT = 1<<28,
1910 GPC_INT_POL_HI = 1<<27,
1911 GPC_75_OHM = 1<<26,
1912 GPC_DIS_FC = 1<<25,
1913 GPC_DIS_SLEEP = 1<<24,
1914 GPC_HWCFG_M_3 = 1<<23,
1915 GPC_HWCFG_M_2 = 1<<22,
1916 GPC_HWCFG_M_1 = 1<<21,
1917 GPC_HWCFG_M_0 = 1<<20,
1918 GPC_ANEG_0 = 1<<19,
1919 GPC_ENA_XC = 1<<18,
1920 GPC_DIS_125 = 1<<17,
1921 GPC_ANEG_3 = 1<<16,
1922 GPC_ANEG_2 = 1<<15,
1923 GPC_ANEG_1 = 1<<14,
1924 GPC_ENA_PAUSE = 1<<13,
1925 GPC_PHYADDR_4 = 1<<12,
1926 GPC_PHYADDR_3 = 1<<11,
1927 GPC_PHYADDR_2 = 1<<10,
1928 GPC_PHYADDR_1 = 1<<9,
1929 GPC_PHYADDR_0 = 1<<8,
1930
1931 GPC_RST_CLR = 1<<1,
1932 GPC_RST_SET = 1<<0,
1933};
1934
1935#define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1936#define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1937#define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1938
1939
1940#define GPC_FRC10MBIT_HALF 0
1941#define GPC_FRC10MBIT_FULL GPC_ANEG_0
1942#define GPC_FRC100MBIT_HALF GPC_ANEG_1
1943#define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
1944
1945
1946
1947#define GPC_ADV_1000_HALF GPC_ANEG_2
1948#define GPC_ADV_1000_FULL GPC_ANEG_3
1949#define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
1950
1951
1952
1953#define GPC_FORCE_MASTER 0
1954#define GPC_FORCE_SLAVE GPC_ANEG_0
1955#define GPC_PREF_MASTER GPC_ANEG_1
1956#define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
1957
1958
1959
1960enum {
1961 GM_IS_TX_CO_OV = 1<<5,
1962 GM_IS_RX_CO_OV = 1<<4,
1963 GM_IS_TX_FF_UR = 1<<3,
1964 GM_IS_TX_COMPL = 1<<2,
1965 GM_IS_RX_FF_OR = 1<<1,
1966 GM_IS_RX_COMPL = 1<<0,
1967
1968#define GMAC_DEF_MSK (GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
1969
1970
1971
1972 GMLC_RST_CLR = 1<<1,
1973 GMLC_RST_SET = 1<<0,
1974
1975
1976
1977 WOL_CTL_LINK_CHG_OCC = 1<<15,
1978 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1979 WOL_CTL_PATTERN_OCC = 1<<13,
1980 WOL_CTL_CLEAR_RESULT = 1<<12,
1981 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1982 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1983 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1984 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1985 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1986 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1987 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1988 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1989 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1990 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1991 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1992 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1993};
1994
1995#define WOL_CTL_DEFAULT \
1996 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1997 WOL_CTL_DIS_PME_ON_PATTERN | \
1998 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1999 WOL_CTL_DIS_LINK_CHG_UNIT | \
2000 WOL_CTL_DIS_PATTERN_UNIT | \
2001 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2002
2003
2004#define WOL_CTL_PATT_ENA(x) (1 << (x))
2005
2006
2007
2008enum {
2009 XM_MMU_CMD = 0x0000,
2010 XM_POFF = 0x0008,
2011 XM_BURST = 0x000c,
2012 XM_1L_VLAN_TAG = 0x0010,
2013 XM_2L_VLAN_TAG = 0x0014,
2014 XM_TX_CMD = 0x0020,
2015 XM_TX_RT_LIM = 0x0024,
2016 XM_TX_STIME = 0x0028,
2017 XM_TX_IPG = 0x002c,
2018 XM_RX_CMD = 0x0030,
2019 XM_PHY_ADDR = 0x0034,
2020 XM_PHY_DATA = 0x0038,
2021 XM_GP_PORT = 0x0040,
2022 XM_IMSK = 0x0044,
2023 XM_ISRC = 0x0048,
2024 XM_HW_CFG = 0x004c,
2025 XM_TX_LO_WM = 0x0060,
2026 XM_TX_HI_WM = 0x0062,
2027 XM_TX_THR = 0x0064,
2028 XM_HT_THR = 0x0066,
2029 XM_PAUSE_DA = 0x0068,
2030 XM_CTL_PARA = 0x0070,
2031 XM_MAC_OPCODE = 0x0074,
2032 XM_MAC_PTIME = 0x0076,
2033 XM_TX_STAT = 0x0078,
2034
2035 XM_EXM_START = 0x0080,
2036#define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2037};
2038
2039enum {
2040 XM_SRC_CHK = 0x0100,
2041 XM_SA = 0x0108,
2042 XM_HSM = 0x0110,
2043 XM_RX_LO_WM = 0x0118,
2044 XM_RX_HI_WM = 0x011a,
2045 XM_RX_THR = 0x011c,
2046 XM_DEV_ID = 0x0120,
2047 XM_MODE = 0x0124,
2048 XM_LSA = 0x0128,
2049 XM_TS_READ = 0x0130,
2050 XM_TS_LOAD = 0x0134,
2051 XM_STAT_CMD = 0x0200,
2052 XM_RX_CNT_EV = 0x0204,
2053 XM_TX_CNT_EV = 0x0208,
2054 XM_RX_EV_MSK = 0x020c,
2055 XM_TX_EV_MSK = 0x0210,
2056 XM_TXF_OK = 0x0280,
2057 XM_TXO_OK_HI = 0x0284,
2058 XM_TXO_OK_LO = 0x0288,
2059 XM_TXF_BC_OK = 0x028c,
2060 XM_TXF_MC_OK = 0x0290,
2061 XM_TXF_UC_OK = 0x0294,
2062 XM_TXF_LONG = 0x0298,
2063 XM_TXE_BURST = 0x029c,
2064 XM_TXF_MPAUSE = 0x02a0,
2065 XM_TXF_MCTRL = 0x02a4,
2066 XM_TXF_SNG_COL = 0x02a8,
2067 XM_TXF_MUL_COL = 0x02ac,
2068 XM_TXF_ABO_COL = 0x02b0,
2069 XM_TXF_LAT_COL = 0x02b4,
2070 XM_TXF_DEF = 0x02b8,
2071 XM_TXF_EX_DEF = 0x02bc,
2072 XM_TXE_FIFO_UR = 0x02c0,
2073 XM_TXE_CS_ERR = 0x02c4,
2074 XM_TXP_UTIL = 0x02c8,
2075 XM_TXF_64B = 0x02d0,
2076 XM_TXF_127B = 0x02d4,
2077 XM_TXF_255B = 0x02d8,
2078 XM_TXF_511B = 0x02dc,
2079 XM_TXF_1023B = 0x02e0,
2080 XM_TXF_MAX_SZ = 0x02e4,
2081 XM_RXF_OK = 0x0300,
2082 XM_RXO_OK_HI = 0x0304,
2083 XM_RXO_OK_LO = 0x0308,
2084 XM_RXF_BC_OK = 0x030c,
2085 XM_RXF_MC_OK = 0x0310,
2086 XM_RXF_UC_OK = 0x0314,
2087 XM_RXF_MPAUSE = 0x0318,
2088 XM_RXF_MCTRL = 0x031c,
2089 XM_RXF_INV_MP = 0x0320,
2090 XM_RXF_INV_MOC = 0x0324,
2091 XM_RXE_BURST = 0x0328,
2092 XM_RXE_FMISS = 0x032c,
2093 XM_RXF_FRA_ERR = 0x0330,
2094 XM_RXE_FIFO_OV = 0x0334,
2095 XM_RXF_JAB_PKT = 0x0338,
2096 XM_RXE_CAR_ERR = 0x033c,
2097 XM_RXF_LEN_ERR = 0x0340,
2098 XM_RXE_SYM_ERR = 0x0344,
2099 XM_RXE_SHT_ERR = 0x0348,
2100 XM_RXE_RUNT = 0x034c,
2101 XM_RXF_LNG_ERR = 0x0350,
2102 XM_RXF_FCS_ERR = 0x0354,
2103 XM_RXF_CEX_ERR = 0x035c,
2104 XM_RXP_UTIL = 0x0360,
2105 XM_RXF_64B = 0x0368,
2106 XM_RXF_127B = 0x036c,
2107 XM_RXF_255B = 0x0370,
2108 XM_RXF_511B = 0x0374,
2109 XM_RXF_1023B = 0x0378,
2110 XM_RXF_MAX_SZ = 0x037c,
2111};
2112
2113
2114enum {
2115 XM_MMU_PHY_RDY = 1<<12,
2116 XM_MMU_PHY_BUSY = 1<<11,
2117 XM_MMU_IGN_PF = 1<<10,
2118 XM_MMU_MAC_LB = 1<<9,
2119 XM_MMU_FRC_COL = 1<<7,
2120 XM_MMU_SIM_COL = 1<<6,
2121 XM_MMU_NO_PRE = 1<<5,
2122 XM_MMU_GMII_FD = 1<<4,
2123 XM_MMU_RAT_CTRL = 1<<3,
2124 XM_MMU_GMII_LOOP= 1<<2,
2125 XM_MMU_ENA_RX = 1<<1,
2126 XM_MMU_ENA_TX = 1<<0,
2127};
2128
2129
2130
2131enum {
2132 XM_TX_BK2BK = 1<<6,
2133 XM_TX_ENC_BYP = 1<<5,
2134 XM_TX_SAM_LINE = 1<<4,
2135 XM_TX_NO_GIG_MD = 1<<3,
2136 XM_TX_NO_PRE = 1<<2,
2137 XM_TX_NO_CRC = 1<<1,
2138 XM_TX_AUTO_PAD = 1<<0,
2139};
2140
2141
2142#define XM_RT_LIM_MSK 0x1f
2143
2144
2145
2146#define XM_STIME_MSK 0x7f
2147
2148
2149
2150#define XM_IPG_MSK 0xff
2151
2152
2153
2154enum {
2155 XM_RX_LENERR_OK = 1<<8,
2156
2157 XM_RX_BIG_PK_OK = 1<<7,
2158
2159 XM_RX_IPG_CAP = 1<<6,
2160 XM_RX_TP_MD = 1<<5,
2161 XM_RX_STRIP_FCS = 1<<4,
2162 XM_RX_SELF_RX = 1<<3,
2163 XM_RX_SAM_LINE = 1<<2,
2164 XM_RX_STRIP_PAD = 1<<1,
2165 XM_RX_DIS_CEXT = 1<<0,
2166};
2167
2168
2169
2170enum {
2171 XM_GP_ANIP = 1<<6,
2172 XM_GP_FRC_INT = 1<<5,
2173 XM_GP_RES_MAC = 1<<3,
2174 XM_GP_RES_STAT = 1<<2,
2175 XM_GP_INP_ASS = 1<<0,
2176};
2177
2178
2179
2180
2181enum {
2182 XM_IS_LNK_AE = 1<<14,
2183 XM_IS_TX_ABORT = 1<<13,
2184 XM_IS_FRC_INT = 1<<12,
2185 XM_IS_INP_ASS = 1<<11,
2186 XM_IS_LIPA_RC = 1<<10,
2187 XM_IS_RX_PAGE = 1<<9,
2188 XM_IS_TX_PAGE = 1<<8,
2189 XM_IS_AND = 1<<7,
2190 XM_IS_TSC_OV = 1<<6,
2191 XM_IS_RXC_OV = 1<<5,
2192 XM_IS_TXC_OV = 1<<4,
2193 XM_IS_RXF_OV = 1<<3,
2194 XM_IS_TXF_UR = 1<<2,
2195 XM_IS_TX_COMP = 1<<1,
2196 XM_IS_RX_COMP = 1<<0,
2197
2198 XM_IMSK_DISABLE = 0xffff,
2199};
2200
2201
2202enum {
2203 XM_HW_GEN_EOP = 1<<3,
2204 XM_HW_COM4SIG = 1<<2,
2205 XM_HW_GMII_MD = 1<<0,
2206};
2207
2208
2209
2210
2211#define XM_TX_WM_MSK 0x01ff
2212
2213
2214
2215
2216#define XM_THR_MSK 0x03ff
2217
2218
2219
2220enum {
2221 XM_ST_VALID = (1UL<<31),
2222 XM_ST_BYTE_CNT = (0x3fffL<<17),
2223 XM_ST_RETRY_CNT = (0x1fL<<12),
2224 XM_ST_EX_COL = 1<<11,
2225 XM_ST_EX_DEF = 1<<10,
2226 XM_ST_BURST = 1<<9,
2227 XM_ST_DEFER = 1<<8,
2228 XM_ST_BC = 1<<7,
2229 XM_ST_MC = 1<<6,
2230 XM_ST_UC = 1<<5,
2231 XM_ST_TX_UR = 1<<4,
2232 XM_ST_CS_ERR = 1<<3,
2233 XM_ST_LAT_COL = 1<<2,
2234 XM_ST_MUL_COL = 1<<1,
2235 XM_ST_SGN_COL = 1<<0,
2236};
2237
2238
2239
2240#define XM_RX_WM_MSK 0x03ff
2241
2242
2243
2244#define XM_DEV_OUI (0x00ffffffUL<<8)
2245#define XM_DEV_REV (0x07L << 5)
2246
2247
2248
2249enum {
2250 XM_MD_ENA_REJ = 1<<26,
2251 XM_MD_SPOE_E = 1<<25,
2252
2253 XM_MD_TX_REP = 1<<24,
2254 XM_MD_SPOFF_I = 1<<23,
2255
2256 XM_MD_LE_STW = 1<<22,
2257 XM_MD_TX_CONT = 1<<21,
2258 XM_MD_TX_PAUSE = 1<<20,
2259 XM_MD_ATS = 1<<19,
2260 XM_MD_SPOL_I = 1<<18,
2261
2262 XM_MD_SPOH_I = 1<<17,
2263
2264 XM_MD_CAP = 1<<16,
2265 XM_MD_ENA_HASH = 1<<15,
2266 XM_MD_CSA = 1<<14,
2267 XM_MD_CAA = 1<<13,
2268 XM_MD_RX_MCTRL = 1<<12,
2269 XM_MD_RX_RUNT = 1<<11,
2270 XM_MD_RX_IRLE = 1<<10,
2271 XM_MD_RX_LONG = 1<<9,
2272 XM_MD_RX_CRCE = 1<<8,
2273 XM_MD_RX_ERR = 1<<7,
2274 XM_MD_DIS_UC = 1<<6,
2275 XM_MD_DIS_MC = 1<<5,
2276 XM_MD_DIS_BC = 1<<4,
2277 XM_MD_ENA_PROM = 1<<3,
2278 XM_MD_ENA_BE = 1<<2,
2279 XM_MD_FTF = 1<<1,
2280 XM_MD_FRF = 1<<0,
2281};
2282
2283#define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2284#define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2285 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2286
2287
2288enum {
2289 XM_SC_SNP_RXC = 1<<5,
2290 XM_SC_SNP_TXC = 1<<4,
2291 XM_SC_CP_RXC = 1<<3,
2292 XM_SC_CP_TXC = 1<<2,
2293 XM_SC_CLR_RXC = 1<<1,
2294 XM_SC_CLR_TXC = 1<<0,
2295};
2296
2297
2298
2299
2300enum {
2301 XMR_MAX_SZ_OV = 1<<31,
2302 XMR_1023B_OV = 1<<30,
2303 XMR_511B_OV = 1<<29,
2304 XMR_255B_OV = 1<<28,
2305 XMR_127B_OV = 1<<27,
2306 XMR_64B_OV = 1<<26,
2307 XMR_UTIL_OV = 1<<25,
2308 XMR_UTIL_UR = 1<<24,
2309 XMR_CEX_ERR_OV = 1<<23,
2310 XMR_FCS_ERR_OV = 1<<21,
2311 XMR_LNG_ERR_OV = 1<<20,
2312 XMR_RUNT_OV = 1<<19,
2313 XMR_SHT_ERR_OV = 1<<18,
2314 XMR_SYM_ERR_OV = 1<<17,
2315 XMR_CAR_ERR_OV = 1<<15,
2316 XMR_JAB_PKT_OV = 1<<14,
2317 XMR_FIFO_OV = 1<<13,
2318 XMR_FRA_ERR_OV = 1<<12,
2319 XMR_FMISS_OV = 1<<11,
2320 XMR_BURST = 1<<10,
2321 XMR_INV_MOC = 1<<9,
2322 XMR_INV_MP = 1<<8,
2323 XMR_MCTRL_OV = 1<<7,
2324 XMR_MPAUSE_OV = 1<<6,
2325 XMR_UC_OK_OV = 1<<5,
2326 XMR_MC_OK_OV = 1<<4,
2327 XMR_BC_OK_OV = 1<<3,
2328 XMR_OK_LO_OV = 1<<2,
2329 XMR_OK_HI_OV = 1<<1,
2330 XMR_OK_OV = 1<<0,
2331};
2332
2333#define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2334
2335
2336
2337enum {
2338 XMT_MAX_SZ_OV = 1<<25,
2339 XMT_1023B_OV = 1<<24,
2340 XMT_511B_OV = 1<<23,
2341 XMT_255B_OV = 1<<22,
2342 XMT_127B_OV = 1<<21,
2343 XMT_64B_OV = 1<<20,
2344 XMT_UTIL_OV = 1<<19,
2345 XMT_UTIL_UR = 1<<18,
2346 XMT_CS_ERR_OV = 1<<17,
2347 XMT_FIFO_UR_OV = 1<<16,
2348 XMT_EX_DEF_OV = 1<<15,
2349 XMT_DEF = 1<<14,
2350 XMT_LAT_COL_OV = 1<<13,
2351 XMT_ABO_COL_OV = 1<<12,
2352 XMT_MUL_COL_OV = 1<<11,
2353 XMT_SNG_COL = 1<<10,
2354 XMT_MCTRL_OV = 1<<9,
2355 XMT_MPAUSE = 1<<8,
2356 XMT_BURST = 1<<7,
2357 XMT_LONG = 1<<6,
2358 XMT_UC_OK_OV = 1<<5,
2359 XMT_MC_OK_OV = 1<<4,
2360 XMT_BC_OK_OV = 1<<3,
2361 XMT_OK_LO_OV = 1<<2,
2362 XMT_OK_HI_OV = 1<<1,
2363 XMT_OK_OV = 1<<0,
2364};
2365
2366#define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2367
2368struct skge_rx_desc {
2369 u32 control;
2370 u32 next_offset;
2371 u32 dma_lo;
2372 u32 dma_hi;
2373 u32 status;
2374 u32 timestamp;
2375 u16 csum2;
2376 u16 csum1;
2377 u16 csum2_start;
2378 u16 csum1_start;
2379};
2380
2381struct skge_tx_desc {
2382 u32 control;
2383 u32 next_offset;
2384 u32 dma_lo;
2385 u32 dma_hi;
2386 u32 status;
2387 u32 csum_offs;
2388 u16 csum_write;
2389 u16 csum_start;
2390 u32 rsvd;
2391};
2392
2393struct skge_element {
2394 struct skge_element *next;
2395 void *desc;
2396 struct sk_buff *skb;
2397 DEFINE_DMA_UNMAP_ADDR(mapaddr);
2398 DEFINE_DMA_UNMAP_LEN(maplen);
2399};
2400
2401struct skge_ring {
2402 struct skge_element *to_clean;
2403 struct skge_element *to_use;
2404 struct skge_element *start;
2405 unsigned long count;
2406};
2407
2408
2409struct skge_hw {
2410 void __iomem *regs;
2411 struct pci_dev *pdev;
2412 spinlock_t hw_lock;
2413 u32 intr_mask;
2414 struct net_device *dev[2];
2415
2416 u8 chip_id;
2417 u8 chip_rev;
2418 u8 copper;
2419 u8 ports;
2420 u8 phy_type;
2421
2422 u32 ram_size;
2423 u32 ram_offset;
2424 u16 phy_addr;
2425 spinlock_t phy_lock;
2426 struct tasklet_struct phy_task;
2427
2428 char irq_name[0];
2429};
2430
2431enum pause_control {
2432 FLOW_MODE_NONE = 1,
2433 FLOW_MODE_LOC_SEND = 2,
2434 FLOW_MODE_SYMMETRIC = 3,
2435 FLOW_MODE_SYM_OR_REM = 4,
2436
2437
2438};
2439
2440enum pause_status {
2441 FLOW_STAT_INDETERMINATED=0,
2442 FLOW_STAT_NONE,
2443 FLOW_STAT_REM_SEND,
2444 FLOW_STAT_LOC_SEND,
2445 FLOW_STAT_SYMMETRIC,
2446};
2447
2448
2449struct skge_port {
2450 struct skge_hw *hw;
2451 struct net_device *netdev;
2452 struct napi_struct napi;
2453 int port;
2454 u32 msg_enable;
2455
2456 struct skge_ring tx_ring;
2457
2458 struct skge_ring rx_ring ____cacheline_aligned_in_smp;
2459 unsigned int rx_buf_size;
2460
2461 struct timer_list link_timer;
2462 enum pause_control flow_control;
2463 enum pause_status flow_status;
2464 u8 blink_on;
2465 u8 wol;
2466 u8 autoneg;
2467 u8 duplex;
2468 u16 speed;
2469 u32 advertising;
2470
2471 void *mem;
2472 dma_addr_t dma;
2473 unsigned long mem_size;
2474#ifdef CONFIG_SKGE_DEBUG
2475 struct dentry *debugfs;
2476#endif
2477};
2478
2479
2480
2481static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2482{
2483 return readl(hw->regs + reg);
2484}
2485
2486static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2487{
2488 return readw(hw->regs + reg);
2489}
2490
2491static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2492{
2493 return readb(hw->regs + reg);
2494}
2495
2496static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2497{
2498 writel(val, hw->regs + reg);
2499}
2500
2501static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2502{
2503 writew(val, hw->regs + reg);
2504}
2505
2506static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2507{
2508 writeb(val, hw->regs + reg);
2509}
2510
2511
2512#define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
2513#define SK_XMAC_REG(port, reg) \
2514 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2515
2516static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2517{
2518 u32 v;
2519 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2520 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2521 return v;
2522}
2523
2524static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2525{
2526 return skge_read16(hw, SK_XMAC_REG(port,reg));
2527}
2528
2529static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2530{
2531 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2532 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2533}
2534
2535static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2536{
2537 skge_write16(hw, SK_XMAC_REG(port,r), v);
2538}
2539
2540static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2541 const u8 *hash)
2542{
2543 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2544 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2545 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2546 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2547}
2548
2549static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2550 const u8 *addr)
2551{
2552 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2553 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2554 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2555}
2556
2557#define SK_GMAC_REG(port,reg) \
2558 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2559
2560static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2561{
2562 return skge_read16(hw, SK_GMAC_REG(port,reg));
2563}
2564
2565static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2566{
2567 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2568 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2569}
2570
2571static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2572{
2573 skge_write16(hw, SK_GMAC_REG(port,r), v);
2574}
2575
2576static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2577 const u8 *addr)
2578{
2579 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2580 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2581 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2582}
2583
2584#endif
2585