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50#ifndef _3W_9XXX_H
51#define _3W_9XXX_H
52
53
54typedef struct TAG_twa_message_type {
55 unsigned int code;
56 char* text;
57} twa_message_type;
58
59
60static twa_message_type twa_aen_table[] = {
61 {0x0000, "AEN queue empty"},
62 {0x0001, "Controller reset occurred"},
63 {0x0002, "Degraded unit detected"},
64 {0x0003, "Controller error occurred"},
65 {0x0004, "Background rebuild failed"},
66 {0x0005, "Background rebuild done"},
67 {0x0006, "Incomplete unit detected"},
68 {0x0007, "Background initialize done"},
69 {0x0008, "Unclean shutdown detected"},
70 {0x0009, "Drive timeout detected"},
71 {0x000A, "Drive error detected"},
72 {0x000B, "Rebuild started"},
73 {0x000C, "Background initialize started"},
74 {0x000D, "Entire logical unit was deleted"},
75 {0x000E, "Background initialize failed"},
76 {0x000F, "SMART attribute exceeded threshold"},
77 {0x0010, "Power supply reported AC under range"},
78 {0x0011, "Power supply reported DC out of range"},
79 {0x0012, "Power supply reported a malfunction"},
80 {0x0013, "Power supply predicted malfunction"},
81 {0x0014, "Battery charge is below threshold"},
82 {0x0015, "Fan speed is below threshold"},
83 {0x0016, "Temperature sensor is above threshold"},
84 {0x0017, "Power supply was removed"},
85 {0x0018, "Power supply was inserted"},
86 {0x0019, "Drive was removed from a bay"},
87 {0x001A, "Drive was inserted into a bay"},
88 {0x001B, "Drive bay cover door was opened"},
89 {0x001C, "Drive bay cover door was closed"},
90 {0x001D, "Product case was opened"},
91 {0x0020, "Prepare for shutdown (power-off)"},
92 {0x0021, "Downgrade UDMA mode to lower speed"},
93 {0x0022, "Upgrade UDMA mode to higher speed"},
94 {0x0023, "Sector repair completed"},
95 {0x0024, "Sbuf memory test failed"},
96 {0x0025, "Error flushing cached write data to array"},
97 {0x0026, "Drive reported data ECC error"},
98 {0x0027, "DCB has checksum error"},
99 {0x0028, "DCB version is unsupported"},
100 {0x0029, "Background verify started"},
101 {0x002A, "Background verify failed"},
102 {0x002B, "Background verify done"},
103 {0x002C, "Bad sector overwritten during rebuild"},
104 {0x002D, "Background rebuild error on source drive"},
105 {0x002E, "Replace failed because replacement drive too small"},
106 {0x002F, "Verify failed because array was never initialized"},
107 {0x0030, "Unsupported ATA drive"},
108 {0x0031, "Synchronize host/controller time"},
109 {0x0032, "Spare capacity is inadequate for some units"},
110 {0x0033, "Background migration started"},
111 {0x0034, "Background migration failed"},
112 {0x0035, "Background migration done"},
113 {0x0036, "Verify detected and fixed data/parity mismatch"},
114 {0x0037, "SO-DIMM incompatible"},
115 {0x0038, "SO-DIMM not detected"},
116 {0x0039, "Corrected Sbuf ECC error"},
117 {0x003A, "Drive power on reset detected"},
118 {0x003B, "Background rebuild paused"},
119 {0x003C, "Background initialize paused"},
120 {0x003D, "Background verify paused"},
121 {0x003E, "Background migration paused"},
122 {0x003F, "Corrupt flash file system detected"},
123 {0x0040, "Flash file system repaired"},
124 {0x0041, "Unit number assignments were lost"},
125 {0x0042, "Error during read of primary DCB"},
126 {0x0043, "Latent error found in backup DCB"},
127 {0x00FC, "Recovered/finished array membership update"},
128 {0x00FD, "Handler lockup"},
129 {0x00FE, "Retrying PCI transfer"},
130 {0x00FF, "AEN queue is full"},
131 {0xFFFFFFFF, (char*) 0}
132};
133
134
135static char *twa_aen_severity_table[] =
136{
137 "None", "ERROR", "WARNING", "INFO", "DEBUG", (char*) 0
138};
139
140
141static twa_message_type twa_error_table[] = {
142 {0x0100, "SGL entry contains zero data"},
143 {0x0101, "Invalid command opcode"},
144 {0x0102, "SGL entry has unaligned address"},
145 {0x0103, "SGL size does not match command"},
146 {0x0104, "SGL entry has illegal length"},
147 {0x0105, "Command packet is not aligned"},
148 {0x0106, "Invalid request ID"},
149 {0x0107, "Duplicate request ID"},
150 {0x0108, "ID not locked"},
151 {0x0109, "LBA out of range"},
152 {0x010A, "Logical unit not supported"},
153 {0x010B, "Parameter table does not exist"},
154 {0x010C, "Parameter index does not exist"},
155 {0x010D, "Invalid field in CDB"},
156 {0x010E, "Specified port has invalid drive"},
157 {0x010F, "Parameter item size mismatch"},
158 {0x0110, "Failed memory allocation"},
159 {0x0111, "Memory request too large"},
160 {0x0112, "Out of memory segments"},
161 {0x0113, "Invalid address to deallocate"},
162 {0x0114, "Out of memory"},
163 {0x0115, "Out of heap"},
164 {0x0120, "Double degrade"},
165 {0x0121, "Drive not degraded"},
166 {0x0122, "Reconstruct error"},
167 {0x0123, "Replace not accepted"},
168 {0x0124, "Replace drive capacity too small"},
169 {0x0125, "Sector count not allowed"},
170 {0x0126, "No spares left"},
171 {0x0127, "Reconstruct error"},
172 {0x0128, "Unit is offline"},
173 {0x0129, "Cannot update status to DCB"},
174 {0x0130, "Invalid stripe handle"},
175 {0x0131, "Handle that was not locked"},
176 {0x0132, "Handle that was not empty"},
177 {0x0133, "Handle has different owner"},
178 {0x0140, "IPR has parent"},
179 {0x0150, "Illegal Pbuf address alignment"},
180 {0x0151, "Illegal Pbuf transfer length"},
181 {0x0152, "Illegal Sbuf address alignment"},
182 {0x0153, "Illegal Sbuf transfer length"},
183 {0x0160, "Command packet too large"},
184 {0x0161, "SGL exceeds maximum length"},
185 {0x0162, "SGL has too many entries"},
186 {0x0170, "Insufficient resources for rebuilder"},
187 {0x0171, "Verify error (data != parity)"},
188 {0x0180, "Requested segment not in directory of this DCB"},
189 {0x0181, "DCB segment has unsupported version"},
190 {0x0182, "DCB segment has checksum error"},
191 {0x0183, "DCB support (settings) segment invalid"},
192 {0x0184, "DCB UDB (unit descriptor block) segment invalid"},
193 {0x0185, "DCB GUID (globally unique identifier) segment invalid"},
194 {0x01A0, "Could not clear Sbuf"},
195 {0x01C0, "Flash identify failed"},
196 {0x01C1, "Flash out of bounds"},
197 {0x01C2, "Flash verify error"},
198 {0x01C3, "Flash file object not found"},
199 {0x01C4, "Flash file already present"},
200 {0x01C5, "Flash file system full"},
201 {0x01C6, "Flash file not present"},
202 {0x01C7, "Flash file size error"},
203 {0x01C8, "Bad flash file checksum"},
204 {0x01CA, "Corrupt flash file system detected"},
205 {0x01D0, "Invalid field in parameter list"},
206 {0x01D1, "Parameter list length error"},
207 {0x01D2, "Parameter item is not changeable"},
208 {0x01D3, "Parameter item is not saveable"},
209 {0x0200, "UDMA CRC error"},
210 {0x0201, "Internal CRC error"},
211 {0x0202, "Data ECC error"},
212 {0x0203, "ADP level 1 error"},
213 {0x0204, "Port timeout"},
214 {0x0205, "Drive power on reset"},
215 {0x0206, "ADP level 2 error"},
216 {0x0207, "Soft reset failed"},
217 {0x0208, "Drive not ready"},
218 {0x0209, "Unclassified port error"},
219 {0x020A, "Drive aborted command"},
220 {0x0210, "Internal CRC error"},
221 {0x0211, "PCI abort error"},
222 {0x0212, "PCI parity error"},
223 {0x0213, "Port handler error"},
224 {0x0214, "Token interrupt count error"},
225 {0x0215, "Timeout waiting for PCI transfer"},
226 {0x0216, "Corrected buffer ECC"},
227 {0x0217, "Uncorrected buffer ECC"},
228 {0x0230, "Unsupported command during flash recovery"},
229 {0x0231, "Next image buffer expected"},
230 {0x0232, "Binary image architecture incompatible"},
231 {0x0233, "Binary image has no signature"},
232 {0x0234, "Binary image has bad checksum"},
233 {0x0235, "Image downloaded overflowed buffer"},
234 {0x0240, "I2C device not found"},
235 {0x0241, "I2C transaction aborted"},
236 {0x0242, "SO-DIMM parameter(s) incompatible using defaults"},
237 {0x0243, "SO-DIMM unsupported"},
238 {0x0248, "SPI transfer status error"},
239 {0x0249, "SPI transfer timeout error"},
240 {0x0250, "Invalid unit descriptor size in CreateUnit"},
241 {0x0251, "Unit descriptor size exceeds data buffer in CreateUnit"},
242 {0x0252, "Invalid value in CreateUnit descriptor"},
243 {0x0253, "Inadequate disk space to support descriptor in CreateUnit"},
244 {0x0254, "Unable to create data channel for this unit descriptor"},
245 {0x0255, "CreateUnit descriptor specifies a drive already in use"},
246 {0x0256, "Unable to write configuration to all disks during CreateUnit"},
247 {0x0257, "CreateUnit does not support this descriptor version"},
248 {0x0258, "Invalid subunit for RAID 0 or 5 in CreateUnit"},
249 {0x0259, "Too many descriptors in CreateUnit"},
250 {0x025A, "Invalid configuration specified in CreateUnit descriptor"},
251 {0x025B, "Invalid LBA offset specified in CreateUnit descriptor"},
252 {0x025C, "Invalid stripelet size specified in CreateUnit descriptor"},
253 {0x0260, "SMART attribute exceeded threshold"},
254 {0xFFFFFFFF, (char*) 0}
255};
256
257
258#define TW_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
259#define TW_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
260#define TW_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
261#define TW_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
262#define TW_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
263#define TW_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
264#define TW_CONTROL_CLEAR_ERROR_STATUS 0x00000200
265#define TW_CONTROL_ISSUE_SOFT_RESET 0x00000100
266#define TW_CONTROL_ENABLE_INTERRUPTS 0x00000080
267#define TW_CONTROL_DISABLE_INTERRUPTS 0x00000040
268#define TW_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
269#define TW_CONTROL_CLEAR_PARITY_ERROR 0x00800000
270#define TW_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
271#define TW_CONTROL_CLEAR_PCI_ABORT 0x00100000
272
273
274#define TW_STATUS_MAJOR_VERSION_MASK 0xF0000000
275#define TW_STATUS_MINOR_VERSION_MASK 0x0F000000
276#define TW_STATUS_PCI_PARITY_ERROR 0x00800000
277#define TW_STATUS_QUEUE_ERROR 0x00400000
278#define TW_STATUS_MICROCONTROLLER_ERROR 0x00200000
279#define TW_STATUS_PCI_ABORT 0x00100000
280#define TW_STATUS_HOST_INTERRUPT 0x00080000
281#define TW_STATUS_ATTENTION_INTERRUPT 0x00040000
282#define TW_STATUS_COMMAND_INTERRUPT 0x00020000
283#define TW_STATUS_RESPONSE_INTERRUPT 0x00010000
284#define TW_STATUS_COMMAND_QUEUE_FULL 0x00008000
285#define TW_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
286#define TW_STATUS_MICROCONTROLLER_READY 0x00002000
287#define TW_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
288#define TW_STATUS_EXPECTED_BITS 0x00002000
289#define TW_STATUS_UNEXPECTED_BITS 0x00F00000
290#define TW_STATUS_VALID_INTERRUPT 0x00DF0000
291
292
293#define TW_PCI_CLEAR_PARITY_ERRORS 0xc100
294#define TW_PCI_CLEAR_PCI_ABORT 0x2000
295
296
297#define TW_OP_INIT_CONNECTION 0x1
298#define TW_OP_GET_PARAM 0x12
299#define TW_OP_SET_PARAM 0x13
300#define TW_OP_EXECUTE_SCSI 0x10
301#define TW_OP_DOWNLOAD_FIRMWARE 0x16
302#define TW_OP_RESET 0x1C
303
304
305#define TW_AEN_QUEUE_EMPTY 0x0000
306#define TW_AEN_SOFT_RESET 0x0001
307#define TW_AEN_SYNC_TIME_WITH_HOST 0x031
308#define TW_AEN_SEVERITY_ERROR 0x1
309#define TW_AEN_SEVERITY_DEBUG 0x4
310#define TW_AEN_NOT_RETRIEVED 0x1
311#define TW_AEN_RETRIEVED 0x2
312
313
314#define TW_S_INITIAL 0x1
315#define TW_S_STARTED 0x2
316#define TW_S_POSTED 0x4
317#define TW_S_PENDING 0x8
318#define TW_S_COMPLETED 0x10
319#define TW_S_FINISHED 0x20
320
321
322#define TW_9000_ARCH_ID 0x5
323#define TW_CURRENT_DRIVER_SRL 35
324#define TW_CURRENT_DRIVER_BUILD 0
325#define TW_CURRENT_DRIVER_BRANCH 0
326
327
328#define TW_PHASE_INITIAL 0
329#define TW_PHASE_SINGLE 1
330#define TW_PHASE_SGLIST 2
331
332
333#define TW_9550SX_DRAIN_COMPLETED 0xFFFF
334#define TW_SECTOR_SIZE 512
335#define TW_ALIGNMENT_9000 4
336#define TW_ALIGNMENT_9000_SGL 0x3
337#define TW_MAX_UNITS 16
338#define TW_MAX_UNITS_9650SE 32
339#define TW_INIT_MESSAGE_CREDITS 0x100
340#define TW_INIT_COMMAND_PACKET_SIZE 0x3
341#define TW_INIT_COMMAND_PACKET_SIZE_EXTENDED 0x6
342#define TW_EXTENDED_INIT_CONNECT 0x2
343#define TW_BUNDLED_FW_SAFE_TO_FLASH 0x4
344#define TW_CTLR_FW_RECOMMENDS_FLASH 0x8
345#define TW_CTLR_FW_COMPATIBLE 0x2
346#define TW_BASE_FW_SRL 24
347#define TW_BASE_FW_BRANCH 0
348#define TW_BASE_FW_BUILD 1
349#define TW_FW_SRL_LUNS_SUPPORTED 28
350#define TW_Q_LENGTH 256
351#define TW_Q_START 0
352#define TW_MAX_SLOT 32
353#define TW_MAX_RESET_TRIES 2
354#define TW_MAX_CMDS_PER_LUN 254
355#define TW_MAX_RESPONSE_DRAIN 256
356#define TW_MAX_AEN_DRAIN 255
357#define TW_IN_RESET 2
358#define TW_USING_MSI 3
359#define TW_IN_ATTENTION_LOOP 4
360#define TW_MAX_SECTORS 256
361#define TW_AEN_WAIT_TIME 1000
362#define TW_IOCTL_WAIT_TIME (1 * HZ)
363#define TW_MAX_CDB_LEN 16
364#define TW_ISR_DONT_COMPLETE 2
365#define TW_ISR_DONT_RESULT 3
366#define TW_IOCTL_CHRDEV_TIMEOUT 60
367#define TW_IOCTL_CHRDEV_FREE -1
368#define TW_COMMAND_OFFSET 128
369#define TW_VERSION_TABLE 0x0402
370#define TW_TIMEKEEP_TABLE 0x040A
371#define TW_INFORMATION_TABLE 0x0403
372#define TW_PARAM_FWVER 3
373#define TW_PARAM_FWVER_LENGTH 16
374#define TW_PARAM_BIOSVER 4
375#define TW_PARAM_BIOSVER_LENGTH 16
376#define TW_PARAM_PORTCOUNT 3
377#define TW_PARAM_PORTCOUNT_LENGTH 1
378#define TW_MIN_SGL_LENGTH 0x200
379#define TW_MAX_SENSE_LENGTH 256
380#define TW_EVENT_SOURCE_AEN 0x1000
381#define TW_EVENT_SOURCE_COMMAND 0x1001
382#define TW_EVENT_SOURCE_PCHIP 0x1002
383#define TW_EVENT_SOURCE_DRIVER 0x1003
384#define TW_IOCTL_GET_COMPATIBILITY_INFO 0x101
385#define TW_IOCTL_GET_LAST_EVENT 0x102
386#define TW_IOCTL_GET_FIRST_EVENT 0x103
387#define TW_IOCTL_GET_NEXT_EVENT 0x104
388#define TW_IOCTL_GET_PREVIOUS_EVENT 0x105
389#define TW_IOCTL_GET_LOCK 0x106
390#define TW_IOCTL_RELEASE_LOCK 0x107
391#define TW_IOCTL_FIRMWARE_PASS_THROUGH 0x108
392#define TW_IOCTL_ERROR_STATUS_NOT_LOCKED 0x1001
393#define TW_IOCTL_ERROR_STATUS_LOCKED 0x1002
394#define TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS 0x1003
395#define TW_IOCTL_ERROR_STATUS_AEN_CLOBBER 0x1004
396#define TW_IOCTL_ERROR_OS_EFAULT -EFAULT
397#define TW_IOCTL_ERROR_OS_EINTR -EINTR
398#define TW_IOCTL_ERROR_OS_EINVAL -EINVAL
399#define TW_IOCTL_ERROR_OS_ENOMEM -ENOMEM
400#define TW_IOCTL_ERROR_OS_ERESTARTSYS -ERESTARTSYS
401#define TW_IOCTL_ERROR_OS_EIO -EIO
402#define TW_IOCTL_ERROR_OS_ENOTTY -ENOTTY
403#define TW_IOCTL_ERROR_OS_ENODEV -ENODEV
404#define TW_ALLOCATION_LENGTH 128
405#define TW_SENSE_DATA_LENGTH 18
406#define TW_STATUS_CHECK_CONDITION 2
407#define TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x10a
408#define TW_ERROR_UNIT_OFFLINE 0x128
409#define TW_MESSAGE_SOURCE_CONTROLLER_ERROR 3
410#define TW_MESSAGE_SOURCE_CONTROLLER_EVENT 4
411#define TW_MESSAGE_SOURCE_LINUX_DRIVER 6
412#define TW_DRIVER TW_MESSAGE_SOURCE_LINUX_DRIVER
413#define TW_MESSAGE_SOURCE_LINUX_OS 9
414#define TW_OS TW_MESSAGE_SOURCE_LINUX_OS
415#ifndef PCI_DEVICE_ID_3WARE_9000
416#define PCI_DEVICE_ID_3WARE_9000 0x1002
417#endif
418#ifndef PCI_DEVICE_ID_3WARE_9550SX
419#define PCI_DEVICE_ID_3WARE_9550SX 0x1003
420#endif
421#ifndef PCI_DEVICE_ID_3WARE_9650SE
422#define PCI_DEVICE_ID_3WARE_9650SE 0x1004
423#endif
424#ifndef PCI_DEVICE_ID_3WARE_9690SA
425#define PCI_DEVICE_ID_3WARE_9690SA 0x1005
426#endif
427
428
429
430
431#define TW_OPRES_IN(x,y) ((x << 5) | (y & 0x1f))
432#define TW_OP_OUT(x) (x & 0x1f)
433
434
435#define TW_OPSGL_IN(x,y) ((x << 5) | (y & 0x1f))
436#define TW_SGL_OUT(x) ((x >> 5) & 0x7)
437
438
439#define TW_SEV_OUT(x) (x & 0x7)
440
441
442#define TW_RESID_OUT(x) ((x >> 4) & 0xff)
443
444
445#define TW_REQ_LUN_IN(lun, request_id) (((lun << 12) & 0xf000) | (request_id & 0xfff))
446#define TW_LUN_OUT(lun) ((lun >> 12) & 0xf)
447
448
449#define TW_CONTROL_REG_ADDR(x) (x->base_addr)
450#define TW_STATUS_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0x4)
451#define TW_COMMAND_QUEUE_REG_ADDR(x) (sizeof(dma_addr_t) > 4 ? ((unsigned char __iomem *)x->base_addr + 0x20) : ((unsigned char __iomem *)x->base_addr + 0x8))
452#define TW_COMMAND_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x20)
453#define TW_RESPONSE_QUEUE_REG_ADDR(x) ((unsigned char __iomem *)x->base_addr + 0xC)
454#define TW_RESPONSE_QUEUE_REG_ADDR_LARGE(x) ((unsigned char __iomem *)x->base_addr + 0x30)
455#define TW_CLEAR_ALL_INTERRUPTS(x) (writel(TW_STATUS_VALID_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
456#define TW_CLEAR_ATTENTION_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
457#define TW_CLEAR_HOST_INTERRUPT(x) (writel(TW_CONTROL_CLEAR_HOST_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
458#define TW_DISABLE_INTERRUPTS(x) (writel(TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
459#define TW_ENABLE_AND_CLEAR_INTERRUPTS(x) (writel(TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | TW_CONTROL_UNMASK_RESPONSE_INTERRUPT | TW_CONTROL_ENABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
460#define TW_MASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_MASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
461#define TW_UNMASK_COMMAND_INTERRUPT(x) (writel(TW_CONTROL_UNMASK_COMMAND_INTERRUPT, TW_CONTROL_REG_ADDR(x)))
462#define TW_SOFT_RESET(x) (writel(TW_CONTROL_ISSUE_SOFT_RESET | \
463 TW_CONTROL_CLEAR_HOST_INTERRUPT | \
464 TW_CONTROL_CLEAR_ATTENTION_INTERRUPT | \
465 TW_CONTROL_MASK_COMMAND_INTERRUPT | \
466 TW_CONTROL_MASK_RESPONSE_INTERRUPT | \
467 TW_CONTROL_CLEAR_ERROR_STATUS | \
468 TW_CONTROL_DISABLE_INTERRUPTS, TW_CONTROL_REG_ADDR(x)))
469#define TW_PRINTK(h,a,b,c) { \
470if (h) \
471printk(KERN_WARNING "3w-9xxx: scsi%d: ERROR: (0x%02X:0x%04X): %s.\n",h->host_no,a,b,c); \
472else \
473printk(KERN_WARNING "3w-9xxx: ERROR: (0x%02X:0x%04X): %s.\n",a,b,c); \
474}
475#define TW_MAX_LUNS(srl) (srl < TW_FW_SRL_LUNS_SUPPORTED ? 1 : 16)
476#define TW_COMMAND_SIZE (sizeof(dma_addr_t) > 4 ? 5 : 4)
477#define TW_APACHE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 72 : 109)
478#define TW_ESCALADE_MAX_SGL_LENGTH (sizeof(dma_addr_t) > 4 ? 41 : 62)
479#define TW_PADDING_LENGTH (sizeof(dma_addr_t) > 4 ? 8 : 0)
480#define TW_CPU_TO_SGL(x) (sizeof(dma_addr_t) > 4 ? cpu_to_le64(x) : cpu_to_le32(x))
481
482#pragma pack(1)
483
484
485typedef struct TAG_TW_SG_Entry {
486 dma_addr_t address;
487 u32 length;
488} TW_SG_Entry;
489
490
491typedef struct TW_Command {
492 unsigned char opcode__sgloffset;
493 unsigned char size;
494 unsigned char request_id;
495 unsigned char unit__hostid;
496
497 unsigned char status;
498 unsigned char flags;
499 union {
500 unsigned short block_count;
501 unsigned short parameter_count;
502 } byte6_offset;
503 union {
504 struct {
505 u32 lba;
506 TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
507 dma_addr_t padding;
508 } io;
509 struct {
510 TW_SG_Entry sgl[TW_ESCALADE_MAX_SGL_LENGTH];
511 u32 padding;
512 dma_addr_t padding2;
513 } param;
514 } byte8_offset;
515} TW_Command;
516
517
518typedef struct TAG_TW_Command_Apache {
519 unsigned char opcode__reserved;
520 unsigned char unit;
521 unsigned short request_id__lunl;
522 unsigned char status;
523 unsigned char sgl_offset;
524 unsigned short sgl_entries__lunh;
525 unsigned char cdb[16];
526 TW_SG_Entry sg_list[TW_APACHE_MAX_SGL_LENGTH];
527 unsigned char padding[TW_PADDING_LENGTH];
528} TW_Command_Apache;
529
530
531typedef struct TAG_TW_Command_Apache_Header {
532 unsigned char sense_data[TW_SENSE_DATA_LENGTH];
533 struct {
534 char reserved[4];
535 unsigned short error;
536 unsigned char padding;
537 unsigned char severity__reserved;
538 } status_block;
539 unsigned char err_specific_desc[98];
540 struct {
541 unsigned char size_header;
542 unsigned short reserved;
543 unsigned char size_sense;
544 } header_desc;
545} TW_Command_Apache_Header;
546
547
548typedef struct TAG_TW_Command_Full {
549 TW_Command_Apache_Header header;
550 union {
551 TW_Command oldcommand;
552 TW_Command_Apache newcommand;
553 } command;
554} TW_Command_Full;
555
556
557typedef struct TAG_TW_Initconnect {
558 unsigned char opcode__reserved;
559 unsigned char size;
560 unsigned char request_id;
561 unsigned char res2;
562 unsigned char status;
563 unsigned char flags;
564 unsigned short message_credits;
565 u32 features;
566 unsigned short fw_srl;
567 unsigned short fw_arch_id;
568 unsigned short fw_branch;
569 unsigned short fw_build;
570 u32 result;
571} TW_Initconnect;
572
573
574typedef struct TAG_TW_Event
575{
576 unsigned int sequence_id;
577 unsigned int time_stamp_sec;
578 unsigned short aen_code;
579 unsigned char severity;
580 unsigned char retrieved;
581 unsigned char repeat_count;
582 unsigned char parameter_len;
583 unsigned char parameter_data[98];
584} TW_Event;
585
586typedef struct TAG_TW_Ioctl_Driver_Command {
587 unsigned int control_code;
588 unsigned int status;
589 unsigned int unique_id;
590 unsigned int sequence_id;
591 unsigned int os_specific;
592 unsigned int buffer_length;
593} TW_Ioctl_Driver_Command;
594
595typedef struct TAG_TW_Ioctl_Apache {
596 TW_Ioctl_Driver_Command driver_command;
597 char padding[488];
598 TW_Command_Full firmware_command;
599 char data_buffer[1];
600} TW_Ioctl_Buf_Apache;
601
602
603typedef struct TAG_TW_Lock {
604 unsigned long timeout_msec;
605 unsigned long time_remaining_msec;
606 unsigned long force_flag;
607} TW_Lock;
608
609
610typedef struct {
611 unsigned short table_id;
612 unsigned short parameter_id;
613 unsigned short parameter_size_bytes;
614 unsigned short actual_parameter_size_bytes;
615 unsigned char data[1];
616} TW_Param_Apache, *PTW_Param_Apache;
617
618
619typedef union TAG_TW_Response_Queue {
620 u32 response_id;
621 u32 value;
622} TW_Response_Queue;
623
624
625typedef struct TAG_TW_Compatibility_Info
626{
627 char driver_version[32];
628 unsigned short working_srl;
629 unsigned short working_branch;
630 unsigned short working_build;
631 unsigned short driver_srl_high;
632 unsigned short driver_branch_high;
633 unsigned short driver_build_high;
634 unsigned short driver_srl_low;
635 unsigned short driver_branch_low;
636 unsigned short driver_build_low;
637 unsigned short fw_on_ctlr_srl;
638 unsigned short fw_on_ctlr_branch;
639 unsigned short fw_on_ctlr_build;
640} TW_Compatibility_Info;
641
642#pragma pack()
643
644typedef struct TAG_TW_Device_Extension {
645 u32 __iomem *base_addr;
646 unsigned long *generic_buffer_virt[TW_Q_LENGTH];
647 dma_addr_t generic_buffer_phys[TW_Q_LENGTH];
648 TW_Command_Full *command_packet_virt[TW_Q_LENGTH];
649 dma_addr_t command_packet_phys[TW_Q_LENGTH];
650 struct pci_dev *tw_pci_dev;
651 struct scsi_cmnd *srb[TW_Q_LENGTH];
652 unsigned char free_queue[TW_Q_LENGTH];
653 unsigned char free_head;
654 unsigned char free_tail;
655 unsigned char pending_queue[TW_Q_LENGTH];
656 unsigned char pending_head;
657 unsigned char pending_tail;
658 int state[TW_Q_LENGTH];
659 unsigned int posted_request_count;
660 unsigned int max_posted_request_count;
661 unsigned int pending_request_count;
662 unsigned int max_pending_request_count;
663 unsigned int max_sgl_entries;
664 unsigned int sgl_entries;
665 unsigned int num_resets;
666 unsigned int sector_count;
667 unsigned int max_sector_count;
668 unsigned int aen_count;
669 struct Scsi_Host *host;
670 long flags;
671 int reset_print;
672 TW_Event *event_queue[TW_Q_LENGTH];
673 unsigned char error_index;
674 unsigned char event_queue_wrapped;
675 unsigned int error_sequence_id;
676 int ioctl_sem_lock;
677 u32 ioctl_msec;
678 int chrdev_request_id;
679 wait_queue_head_t ioctl_wqueue;
680 struct mutex ioctl_lock;
681 char aen_clobber;
682 TW_Compatibility_Info tw_compat_info;
683} TW_Device_Extension;
684
685#endif
686
687
