LXR linux/drivers/scsi/bfa/bfa_hw

   1/*
   2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
   3 * All rights reserved
   4 * www.brocade.com
   5 *
   6 * Linux driver for Brocade Fibre Channel Host Bus Adapter.
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms of the GNU General Public License (GPL) Version 2 as
  10 * published by the Free Software Foundation
  11 *
  12 * This program is distributed in the hope that it will be useful, but
  13 * WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 */
  17
  18#include "bfad_drv.h"
  19#include "bfa_modules.h"
  20#include "bfi_reg.h"
  21
  22BFA_TRC_FILE(HAL, IOCFC_CT);
  23
  24/*
  25 * Dummy interrupt handler for handling spurious interrupt during chip-reinit.
  26 */
  27static void
  28bfa_hwct_msix_dummy(struct bfa_s *bfa, int vec)
  29{
  30}
  31
  32void
  33bfa_hwct_reginit(struct bfa_s *bfa)
  34{
  35        struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  36        void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
  37        int     fn = bfa_ioc_pcifn(&bfa->ioc);
  38
  39        if (fn == 0) {
  40                bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
  41                bfa_regs->intr_mask   = (kva + HOSTFN0_INT_MSK);
  42        } else {
  43                bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
  44                bfa_regs->intr_mask   = (kva + HOSTFN1_INT_MSK);
  45        }
  46}
  47
  48void
  49bfa_hwct2_reginit(struct bfa_s *bfa)
  50{
  51        struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  52        void __iomem    *kva = bfa_ioc_bar0(&bfa->ioc);
  53
  54        bfa_regs->intr_status = (kva + CT2_HOSTFN_INT_STATUS);
  55        bfa_regs->intr_mask   = (kva + CT2_HOSTFN_INTR_MASK);
  56}
  57
  58void
  59bfa_hwct_reqq_ack(struct bfa_s *bfa, int reqq)
  60{
  61        u32     r32;
  62
  63        r32 = readl(bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
  64        writel(r32, bfa->iocfc.bfa_regs.cpe_q_ctrl[reqq]);
  65}
  66
  67/*
  68 * Actions to respond RME Interrupt for Catapult ASIC:
  69 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
  70 * - Acknowledge by writing to RME Queue Control register
  71 * - Update CI
  72 */
  73void
  74bfa_hwct_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
  75{
  76        u32     r32;
  77
  78        r32 = readl(bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
  79        writel(r32, bfa->iocfc.bfa_regs.rme_q_ctrl[rspq]);
  80
  81        bfa_rspq_ci(bfa, rspq) = ci;
  82        writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
  83        mmiowb();
  84}
  85
  86/*
  87 * Actions to respond RME Interrupt for Catapult2 ASIC:
  88 * - Write 1 to Interrupt Status register (INTx only - done in bfa_intx())
  89 * - Update CI
  90 */
  91void
  92bfa_hwct2_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
  93{
  94        bfa_rspq_ci(bfa, rspq) = ci;
  95        writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
  96        mmiowb();
  97}
  98
  99void
 100bfa_hwct_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
 101                 u32 *num_vecs, u32 *max_vec_bit)
 102{
 103        *msix_vecs_bmap = (1 << BFI_MSIX_CT_MAX) - 1;
 104        *max_vec_bit = (1 << (BFI_MSIX_CT_MAX - 1));
 105        *num_vecs = BFI_MSIX_CT_MAX;
 106}
 107
 108/*
 109 * Setup MSI-X vector for catapult
 110 */
 111void
 112bfa_hwct_msix_init(struct bfa_s *bfa, int nvecs)
 113{
 114        WARN_ON((nvecs != 1) && (nvecs != BFI_MSIX_CT_MAX));
 115        bfa_trc(bfa, nvecs);
 116
 117        bfa->msix.nvecs = nvecs;
 118        bfa_hwct_msix_uninstall(bfa);
 119}
 120
 121void
 122bfa_hwct_msix_ctrl_install(struct bfa_s *bfa)
 123{
 124        if (bfa->msix.nvecs == 0)
 125                return;
 126
 127        if (bfa->msix.nvecs == 1)
 128                bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_all;
 129        else
 130                bfa->msix.handler[BFI_MSIX_LPU_ERR_CT] = bfa_msix_lpu_err;
 131}
 132
 133void
 134bfa_hwct_msix_queue_install(struct bfa_s *bfa)
 135{
 136        int i;
 137
 138        if (bfa->msix.nvecs == 0)
 139                return;
 140
 141        if (bfa->msix.nvecs == 1) {
 142                for (i = BFI_MSIX_CPE_QMIN_CT; i < BFI_MSIX_CT_MAX; i++)
 143                        bfa->msix.handler[i] = bfa_msix_all;
 144                return;
 145        }
 146
 147        for (i = BFI_MSIX_CPE_QMIN_CT; i <= BFI_MSIX_CPE_QMAX_CT; i++)
 148                bfa->msix.handler[i] = bfa_msix_reqq;
 149
 150        for (i = BFI_MSIX_RME_QMIN_CT; i <= BFI_MSIX_RME_QMAX_CT; i++)
 151                bfa->msix.handler[i] = bfa_msix_rspq;
 152}
 153
 154void
 155bfa_hwct_msix_uninstall(struct bfa_s *bfa)
 156{
 157        int i;
 158
 159        for (i = 0; i < BFI_MSIX_CT_MAX; i++)
 160                bfa->msix.handler[i] = bfa_hwct_msix_dummy;
 161}
 162
 163/*
 164 * Enable MSI-X vectors
 165 */
 166void
 167bfa_hwct_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
 168{
 169        bfa_trc(bfa, 0);
 170        bfa_ioc_isr_mode_set(&bfa->ioc, msix);
 171}
 172
 173void
 174bfa_hwct_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
 175{
 176        *start = BFI_MSIX_RME_QMIN_CT;
 177        *end = BFI_MSIX_RME_QMAX_CT;
 178}
 179