1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/list.h>
29#include <linux/workqueue.h>
30#include <linux/interrupt.h>
31#include <linux/platform_device.h>
32#include <linux/io.h>
33#include <linux/clk.h>
34#include <linux/spi/spi.h>
35
36#define RSPI_SPCR 0x00
37#define RSPI_SSLP 0x01
38#define RSPI_SPPCR 0x02
39#define RSPI_SPSR 0x03
40#define RSPI_SPDR 0x04
41#define RSPI_SPSCR 0x08
42#define RSPI_SPSSR 0x09
43#define RSPI_SPBR 0x0a
44#define RSPI_SPDCR 0x0b
45#define RSPI_SPCKD 0x0c
46#define RSPI_SSLND 0x0d
47#define RSPI_SPND 0x0e
48#define RSPI_SPCR2 0x0f
49#define RSPI_SPCMD0 0x10
50#define RSPI_SPCMD1 0x12
51#define RSPI_SPCMD2 0x14
52#define RSPI_SPCMD3 0x16
53#define RSPI_SPCMD4 0x18
54#define RSPI_SPCMD5 0x1a
55#define RSPI_SPCMD6 0x1c
56#define RSPI_SPCMD7 0x1e
57
58
59#define SPCR_SPRIE 0x80
60#define SPCR_SPE 0x40
61#define SPCR_SPTIE 0x20
62#define SPCR_SPEIE 0x10
63#define SPCR_MSTR 0x08
64#define SPCR_MODFEN 0x04
65#define SPCR_TXMD 0x02
66#define SPCR_SPMS 0x01
67
68
69#define SSLP_SSL1P 0x02
70#define SSLP_SSL0P 0x01
71
72
73#define SPPCR_MOIFE 0x20
74#define SPPCR_MOIFV 0x10
75#define SPPCR_SPOM 0x04
76#define SPPCR_SPLP2 0x02
77#define SPPCR_SPLP 0x01
78
79
80#define SPSR_SPRF 0x80
81#define SPSR_SPTEF 0x20
82#define SPSR_PERF 0x08
83#define SPSR_MODF 0x04
84#define SPSR_IDLNF 0x02
85#define SPSR_OVRF 0x01
86
87
88#define SPSCR_SPSLN_MASK 0x07
89
90
91#define SPSSR_SPECM_MASK 0x70
92#define SPSSR_SPCP_MASK 0x07
93
94
95#define SPDCR_SPLW 0x20
96#define SPDCR_SPRDTD 0x10
97#define SPDCR_SLSEL1 0x08
98#define SPDCR_SLSEL0 0x04
99#define SPDCR_SLSEL_MASK 0x0c
100#define SPDCR_SPFC1 0x02
101#define SPDCR_SPFC0 0x01
102
103
104#define SPCKD_SCKDL_MASK 0x07
105
106
107#define SSLND_SLNDL_MASK 0x07
108
109
110#define SPND_SPNDL_MASK 0x07
111
112
113#define SPCR2_PTE 0x08
114#define SPCR2_SPIE 0x04
115#define SPCR2_SPOE 0x02
116#define SPCR2_SPPE 0x01
117
118
119#define SPCMD_SCKDEN 0x8000
120#define SPCMD_SLNDEN 0x4000
121#define SPCMD_SPNDEN 0x2000
122#define SPCMD_LSBF 0x1000
123#define SPCMD_SPB_MASK 0x0f00
124#define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
125#define SPCMD_SPB_20BIT 0x0000
126#define SPCMD_SPB_24BIT 0x0100
127#define SPCMD_SPB_32BIT 0x0200
128#define SPCMD_SSLKP 0x0080
129#define SPCMD_SSLA_MASK 0x0030
130#define SPCMD_BRDV_MASK 0x000c
131#define SPCMD_CPOL 0x0002
132#define SPCMD_CPHA 0x0001
133
134struct rspi_data {
135 void __iomem *addr;
136 u32 max_speed_hz;
137 struct spi_master *master;
138 struct list_head queue;
139 struct work_struct ws;
140 wait_queue_head_t wait;
141 spinlock_t lock;
142 struct clk *clk;
143 unsigned char spsr;
144};
145
146static void rspi_write8(struct rspi_data *rspi, u8 data, u16 offset)
147{
148 iowrite8(data, rspi->addr + offset);
149}
150
151static void rspi_write16(struct rspi_data *rspi, u16 data, u16 offset)
152{
153 iowrite16(data, rspi->addr + offset);
154}
155
156static u8 rspi_read8(struct rspi_data *rspi, u16 offset)
157{
158 return ioread8(rspi->addr + offset);
159}
160
161static u16 rspi_read16(struct rspi_data *rspi, u16 offset)
162{
163 return ioread16(rspi->addr + offset);
164}
165
166static unsigned char rspi_calc_spbr(struct rspi_data *rspi)
167{
168 int tmp;
169 unsigned char spbr;
170
171 tmp = clk_get_rate(rspi->clk) / (2 * rspi->max_speed_hz) - 1;
172 spbr = clamp(tmp, 0, 255);
173
174 return spbr;
175}
176
177static void rspi_enable_irq(struct rspi_data *rspi, u8 enable)
178{
179 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
180}
181
182static void rspi_disable_irq(struct rspi_data *rspi, u8 disable)
183{
184 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
185}
186
187static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
188 u8 enable_bit)
189{
190 int ret;
191
192 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
193 rspi_enable_irq(rspi, enable_bit);
194 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
195 if (ret == 0 && !(rspi->spsr & wait_mask))
196 return -ETIMEDOUT;
197
198 return 0;
199}
200
201static void rspi_assert_ssl(struct rspi_data *rspi)
202{
203 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
204}
205
206static void rspi_negate_ssl(struct rspi_data *rspi)
207{
208 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
209}
210
211static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
212{
213
214 rspi_write8(rspi, 0x00, RSPI_SPPCR);
215
216
217 rspi_write8(rspi, rspi_calc_spbr(rspi), RSPI_SPBR);
218
219
220 rspi_write8(rspi, 0x00, RSPI_SPDCR);
221
222
223 rspi_write8(rspi, 0x00, RSPI_SPCKD);
224 rspi_write8(rspi, 0x00, RSPI_SSLND);
225 rspi_write8(rspi, 0x00, RSPI_SPND);
226
227
228 rspi_write8(rspi, 0x00, RSPI_SPCR2);
229
230
231 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP,
232 RSPI_SPCMD0);
233
234
235 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
236
237 return 0;
238}
239
240static int rspi_send_pio(struct rspi_data *rspi, struct spi_message *mesg,
241 struct spi_transfer *t)
242{
243 int remain = t->len;
244 u8 *data;
245
246 data = (u8 *)t->tx_buf;
247 while (remain > 0) {
248 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD,
249 RSPI_SPCR);
250
251 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
252 dev_err(&rspi->master->dev,
253 "%s: tx empty timeout\n", __func__);
254 return -ETIMEDOUT;
255 }
256
257 rspi_write16(rspi, *data, RSPI_SPDR);
258 data++;
259 remain--;
260 }
261
262
263 rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
264
265 return 0;
266}
267
268static int rspi_receive_pio(struct rspi_data *rspi, struct spi_message *mesg,
269 struct spi_transfer *t)
270{
271 int remain = t->len;
272 u8 *data;
273 unsigned char spsr;
274
275 spsr = rspi_read8(rspi, RSPI_SPSR);
276 if (spsr & SPSR_SPRF)
277 rspi_read16(rspi, RSPI_SPDR);
278 if (spsr & SPSR_OVRF)
279 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
280 RSPI_SPCR);
281
282 data = (u8 *)t->rx_buf;
283 while (remain > 0) {
284 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD,
285 RSPI_SPCR);
286
287 if (rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE) < 0) {
288 dev_err(&rspi->master->dev,
289 "%s: tx empty timeout\n", __func__);
290 return -ETIMEDOUT;
291 }
292
293 rspi_write16(rspi, 0x00, RSPI_SPDR);
294
295 if (rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE) < 0) {
296 dev_err(&rspi->master->dev,
297 "%s: receive timeout\n", __func__);
298 return -ETIMEDOUT;
299 }
300
301 *data = (u8)rspi_read16(rspi, RSPI_SPDR);
302
303 data++;
304 remain--;
305 }
306
307 return 0;
308}
309
310static void rspi_work(struct work_struct *work)
311{
312 struct rspi_data *rspi = container_of(work, struct rspi_data, ws);
313 struct spi_message *mesg;
314 struct spi_transfer *t;
315 unsigned long flags;
316 int ret;
317
318 spin_lock_irqsave(&rspi->lock, flags);
319 while (!list_empty(&rspi->queue)) {
320 mesg = list_entry(rspi->queue.next, struct spi_message, queue);
321 list_del_init(&mesg->queue);
322 spin_unlock_irqrestore(&rspi->lock, flags);
323
324 rspi_assert_ssl(rspi);
325
326 list_for_each_entry(t, &mesg->transfers, transfer_list) {
327 if (t->tx_buf) {
328 ret = rspi_send_pio(rspi, mesg, t);
329 if (ret < 0)
330 goto error;
331 }
332 if (t->rx_buf) {
333 ret = rspi_receive_pio(rspi, mesg, t);
334 if (ret < 0)
335 goto error;
336 }
337 mesg->actual_length += t->len;
338 }
339 rspi_negate_ssl(rspi);
340
341 mesg->status = 0;
342 mesg->complete(mesg->context);
343
344 spin_lock_irqsave(&rspi->lock, flags);
345 }
346
347 return;
348
349error:
350 mesg->status = ret;
351 mesg->complete(mesg->context);
352}
353
354static int rspi_setup(struct spi_device *spi)
355{
356 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
357
358 if (!spi->bits_per_word)
359 spi->bits_per_word = 8;
360 rspi->max_speed_hz = spi->max_speed_hz;
361
362 rspi_set_config_register(rspi, 8);
363
364 return 0;
365}
366
367static int rspi_transfer(struct spi_device *spi, struct spi_message *mesg)
368{
369 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
370 unsigned long flags;
371
372 mesg->actual_length = 0;
373 mesg->status = -EINPROGRESS;
374
375 spin_lock_irqsave(&rspi->lock, flags);
376 list_add_tail(&mesg->queue, &rspi->queue);
377 schedule_work(&rspi->ws);
378 spin_unlock_irqrestore(&rspi->lock, flags);
379
380 return 0;
381}
382
383static void rspi_cleanup(struct spi_device *spi)
384{
385}
386
387static irqreturn_t rspi_irq(int irq, void *_sr)
388{
389 struct rspi_data *rspi = (struct rspi_data *)_sr;
390 unsigned long spsr;
391 irqreturn_t ret = IRQ_NONE;
392 unsigned char disable_irq = 0;
393
394 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (spsr & SPSR_SPRF)
396 disable_irq |= SPCR_SPRIE;
397 if (spsr & SPSR_SPTEF)
398 disable_irq |= SPCR_SPTIE;
399
400 if (disable_irq) {
401 ret = IRQ_HANDLED;
402 rspi_disable_irq(rspi, disable_irq);
403 wake_up(&rspi->wait);
404 }
405
406 return ret;
407}
408
409static int __devexit rspi_remove(struct platform_device *pdev)
410{
411 struct rspi_data *rspi = dev_get_drvdata(&pdev->dev);
412
413 spi_unregister_master(rspi->master);
414 free_irq(platform_get_irq(pdev, 0), rspi);
415 clk_put(rspi->clk);
416 iounmap(rspi->addr);
417 spi_master_put(rspi->master);
418
419 return 0;
420}
421
422static int __devinit rspi_probe(struct platform_device *pdev)
423{
424 struct resource *res;
425 struct spi_master *master;
426 struct rspi_data *rspi;
427 int ret, irq;
428 char clk_name[16];
429
430
431 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
432 if (unlikely(res == NULL)) {
433 dev_err(&pdev->dev, "invalid resource\n");
434 return -EINVAL;
435 }
436
437 irq = platform_get_irq(pdev, 0);
438 if (irq < 0) {
439 dev_err(&pdev->dev, "platform_get_irq error\n");
440 return -ENODEV;
441 }
442
443 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
444 if (master == NULL) {
445 dev_err(&pdev->dev, "spi_alloc_master error.\n");
446 return -ENOMEM;
447 }
448
449 rspi = spi_master_get_devdata(master);
450 dev_set_drvdata(&pdev->dev, rspi);
451
452 rspi->master = master;
453 rspi->addr = ioremap(res->start, resource_size(res));
454 if (rspi->addr == NULL) {
455 dev_err(&pdev->dev, "ioremap error.\n");
456 ret = -ENOMEM;
457 goto error1;
458 }
459
460 snprintf(clk_name, sizeof(clk_name), "rspi%d", pdev->id);
461 rspi->clk = clk_get(&pdev->dev, clk_name);
462 if (IS_ERR(rspi->clk)) {
463 dev_err(&pdev->dev, "cannot get clock\n");
464 ret = PTR_ERR(rspi->clk);
465 goto error2;
466 }
467 clk_enable(rspi->clk);
468
469 INIT_LIST_HEAD(&rspi->queue);
470 spin_lock_init(&rspi->lock);
471 INIT_WORK(&rspi->ws, rspi_work);
472 init_waitqueue_head(&rspi->wait);
473
474 master->num_chipselect = 2;
475 master->bus_num = pdev->id;
476 master->setup = rspi_setup;
477 master->transfer = rspi_transfer;
478 master->cleanup = rspi_cleanup;
479
480 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
481 if (ret < 0) {
482 dev_err(&pdev->dev, "request_irq error\n");
483 goto error3;
484 }
485
486 ret = spi_register_master(master);
487 if (ret < 0) {
488 dev_err(&pdev->dev, "spi_register_master error.\n");
489 goto error4;
490 }
491
492 dev_info(&pdev->dev, "probed\n");
493
494 return 0;
495
496error4:
497 free_irq(irq, rspi);
498error3:
499 clk_put(rspi->clk);
500error2:
501 iounmap(rspi->addr);
502error1:
503 spi_master_put(master);
504
505 return ret;
506}
507
508static struct platform_driver rspi_driver = {
509 .probe = rspi_probe,
510 .remove = __devexit_p(rspi_remove),
511 .driver = {
512 .name = "rspi",
513 .owner = THIS_MODULE,
514 },
515};
516module_platform_driver(rspi_driver);
517
518MODULE_DESCRIPTION("Renesas RSPI bus driver");
519MODULE_LICENSE("GPL v2");
520MODULE_AUTHOR("Yoshihiro Shimoda");
521MODULE_ALIAS("platform:rspi");
522
