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23#ifndef __LINUX_XHCI_HCD_H
24#define __LINUX_XHCI_HCD_H
25
26#include <linux/usb.h>
27#include <linux/timer.h>
28#include <linux/kernel.h>
29#include <linux/usb/hcd.h>
30
31
32#include "xhci-ext-caps.h"
33#include "pci-quirks.h"
34
35
36#define XHCI_SBRN_OFFSET (0x60)
37
38
39#define MAX_HC_SLOTS 256
40
41#define MAX_HC_PORTS 127
42
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57
58
59struct xhci_cap_regs {
60 __le32 hc_capbase;
61 __le32 hcs_params1;
62 __le32 hcs_params2;
63 __le32 hcs_params3;
64 __le32 hcc_params;
65 __le32 db_off;
66 __le32 run_regs_off;
67
68};
69
70
71
72#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73
74#define HC_VERSION(p) (((p) >> 16) & 0xffff)
75
76
77
78#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79#define HCS_SLOTS_MASK 0xff
80
81#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
82
83#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84
85
86
87
88#define HCS_IST(p) (((p) >> 0) & 0xf)
89
90#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
91
92
93#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
94
95
96
97#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
98
99#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100
101
102
103#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
104
105#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
106
107
108
109#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
110
111#define HCC_PPC(p) ((p) & (1 << 3))
112
113#define HCS_INDICATOR(p) ((p) & (1 << 4))
114
115#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
116
117#define HCC_LTC(p) ((p) & (1 << 6))
118
119#define HCC_NSS(p) ((p) & (1 << 7))
120
121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125
126#define DBOFF_MASK (~0x3)
127
128
129#define RTSOFF_MASK (~0x1f)
130
131
132
133#define NUM_PORT_REGS 4
134
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156
157struct xhci_op_regs {
158 __le32 command;
159 __le32 status;
160 __le32 page_size;
161 __le32 reserved1;
162 __le32 reserved2;
163 __le32 dev_notification;
164 __le64 cmd_ring;
165
166 __le32 reserved3[4];
167 __le64 dcbaa_ptr;
168 __le32 config_reg;
169
170 __le32 reserved4[241];
171
172 __le32 port_status_base;
173 __le32 port_power_base;
174 __le32 port_link_base;
175 __le32 reserved5;
176
177 __le32 reserved6[NUM_PORT_REGS*254];
178};
179
180
181
182#define CMD_RUN XHCI_CMD_RUN
183
184
185
186
187#define CMD_RESET (1 << 1)
188
189#define CMD_EIE XHCI_CMD_EIE
190
191#define CMD_HSEIE XHCI_CMD_HSEIE
192
193
194#define CMD_LRESET (1 << 7)
195
196#define CMD_CSS (1 << 8)
197#define CMD_CRS (1 << 9)
198
199#define CMD_EWE XHCI_CMD_EWE
200
201
202
203
204
205#define CMD_PM_INDEX (1 << 11)
206
207
208
209#define IMAN_IP (1 << 1)
210#define IMAN_IE (1 << 0)
211
212
213
214#define STS_HALT XHCI_STS_HALT
215
216#define STS_FATAL (1 << 2)
217
218#define STS_EINT (1 << 3)
219
220#define STS_PORT (1 << 4)
221
222
223#define STS_SAVE (1 << 8)
224
225#define STS_RESTORE (1 << 9)
226
227#define STS_SRE (1 << 10)
228
229#define STS_CNR XHCI_STS_CNR
230
231#define STS_HCE (1 << 12)
232
233
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237
238
239#define DEV_NOTE_MASK (0xffff)
240#define ENABLE_DEV_NOTE(x) (1 << (x))
241
242
243
244#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
245
246
247
248
249#define CMD_RING_PAUSE (1 << 1)
250
251#define CMD_RING_ABORT (1 << 2)
252
253#define CMD_RING_RUNNING (1 << 3)
254
255
256#define CMD_RING_RSVD_BITS (0x3f)
257
258
259
260#define MAX_DEVS(p) ((p) & 0xff)
261
262
263
264
265#define PORT_CONNECT (1 << 0)
266
267#define PORT_PE (1 << 1)
268
269
270#define PORT_OC (1 << 3)
271
272#define PORT_RESET (1 << 4)
273
274
275
276
277#define PORT_PLS_MASK (0xf << 5)
278#define XDEV_U0 (0x0 << 5)
279#define XDEV_U2 (0x2 << 5)
280#define XDEV_U3 (0x3 << 5)
281#define XDEV_RESUME (0xf << 5)
282
283#define PORT_POWER (1 << 9)
284
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290
291
292#define DEV_SPEED_MASK (0xf << 10)
293#define XDEV_FS (0x1 << 10)
294#define XDEV_LS (0x2 << 10)
295#define XDEV_HS (0x3 << 10)
296#define XDEV_SS (0x4 << 10)
297#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
298#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
299#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
300#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
301#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
302
303#define SLOT_SPEED_FS (XDEV_FS << 10)
304#define SLOT_SPEED_LS (XDEV_LS << 10)
305#define SLOT_SPEED_HS (XDEV_HS << 10)
306#define SLOT_SPEED_SS (XDEV_SS << 10)
307
308#define PORT_LED_OFF (0 << 14)
309#define PORT_LED_AMBER (1 << 14)
310#define PORT_LED_GREEN (2 << 14)
311#define PORT_LED_MASK (3 << 14)
312
313#define PORT_LINK_STROBE (1 << 16)
314
315#define PORT_CSC (1 << 17)
316
317#define PORT_PEC (1 << 18)
318
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322
323#define PORT_WRC (1 << 19)
324
325#define PORT_OCC (1 << 20)
326
327#define PORT_RC (1 << 21)
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339
340
341#define PORT_PLC (1 << 22)
342
343#define PORT_CEC (1 << 23)
344
345
346#define PORT_WKCONN_E (1 << 25)
347
348#define PORT_WKDISC_E (1 << 26)
349
350#define PORT_WKOC_E (1 << 27)
351
352
353#define PORT_DEV_REMOVE (1 << 30)
354
355#define PORT_WR (1 << 31)
356
357
358#define DUPLICATE_ENTRY ((u8)(-1))
359
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362
363
364#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
365
366#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
367
368
369
370#define PORT_L1S_MASK 7
371#define PORT_L1S_SUCCESS 1
372#define PORT_RWE (1 << 3)
373#define PORT_HIRD(p) (((p) & 0xf) << 4)
374#define PORT_HIRD_MASK (0xf << 4)
375#define PORT_L1DS(p) (((p) & 0xff) << 8)
376#define PORT_HLE (1 << 16)
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394
395struct xhci_intr_reg {
396 __le32 irq_pending;
397 __le32 irq_control;
398 __le32 erst_size;
399 __le32 rsvd;
400 __le64 erst_base;
401 __le64 erst_dequeue;
402};
403
404
405#define ER_IRQ_PENDING(p) ((p) & 0x1)
406
407
408#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
409#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
410#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
411
412
413
414
415
416
417#define ER_IRQ_INTERVAL_MASK (0xffff)
418
419#define ER_IRQ_COUNTER_MASK (0xffff << 16)
420
421
422
423#define ERST_SIZE_MASK (0xffff << 16)
424
425
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427
428
429#define ERST_DESI_MASK (0x7)
430
431
432
433#define ERST_EHB (1 << 3)
434#define ERST_PTR_MASK (0xf)
435
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444
445struct xhci_run_regs {
446 __le32 microframe_index;
447 __le32 rsvd[7];
448 struct xhci_intr_reg ir_set[128];
449};
450
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459
460struct xhci_doorbell_array {
461 __le32 doorbell[256];
462};
463
464#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
465#define DB_VALUE_HOST 0x00000000
466
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474
475struct xhci_protocol_caps {
476 u32 revision;
477 u32 name_string;
478 u32 port_info;
479};
480
481#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
482#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
483#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
484
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494
495struct xhci_container_ctx {
496 unsigned type;
497#define XHCI_CTX_TYPE_DEVICE 0x1
498#define XHCI_CTX_TYPE_INPUT 0x2
499
500 int size;
501
502 u8 *bytes;
503 dma_addr_t dma;
504};
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516
517struct xhci_slot_ctx {
518 __le32 dev_info;
519 __le32 dev_info2;
520 __le32 tt_info;
521 __le32 dev_state;
522
523 __le32 reserved[4];
524};
525
526
527
528#define ROUTE_STRING_MASK (0xfffff)
529
530#define DEV_SPEED (0xf << 20)
531
532
533#define DEV_MTT (0x1 << 25)
534
535#define DEV_HUB (0x1 << 26)
536
537#define LAST_CTX_MASK (0x1f << 27)
538#define LAST_CTX(p) ((p) << 27)
539#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
540#define SLOT_FLAG (1 << 0)
541#define EP0_FLAG (1 << 1)
542
543
544
545#define MAX_EXIT (0xffff)
546
547#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
548#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
549
550#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
551
552
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555
556
557
558#define TT_SLOT (0xff)
559
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561
562
563#define TT_PORT (0xff << 8)
564#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
565
566
567
568#define DEV_ADDR_MASK (0xff)
569
570
571#define SLOT_STATE (0x1f << 27)
572#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
573
574#define SLOT_STATE_DISABLED 0
575#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
576#define SLOT_STATE_DEFAULT 1
577#define SLOT_STATE_ADDRESSED 2
578#define SLOT_STATE_CONFIGURED 3
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598struct xhci_ep_ctx {
599 __le32 ep_info;
600 __le32 ep_info2;
601 __le64 deq;
602 __le32 tx_info;
603
604 __le32 reserved[3];
605};
606
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615
616
617#define EP_STATE_MASK (0xf)
618#define EP_STATE_DISABLED 0
619#define EP_STATE_RUNNING 1
620#define EP_STATE_HALTED 2
621#define EP_STATE_STOPPED 3
622#define EP_STATE_ERROR 4
623
624#define EP_MULT(p) (((p) & 0x3) << 8)
625#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
626
627
628
629#define EP_INTERVAL(p) (((p) & 0xff) << 16)
630#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
631#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
632#define EP_MAXPSTREAMS_MASK (0x1f << 10)
633#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
634
635#define EP_HAS_LSA (1 << 15)
636
637
638
639
640
641
642#define FORCE_EVENT (0x1)
643#define ERROR_COUNT(p) (((p) & 0x3) << 1)
644#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
645#define EP_TYPE(p) ((p) << 3)
646#define ISOC_OUT_EP 1
647#define BULK_OUT_EP 2
648#define INT_OUT_EP 3
649#define CTRL_EP 4
650#define ISOC_IN_EP 5
651#define BULK_IN_EP 6
652#define INT_IN_EP 7
653
654
655#define MAX_BURST(p) (((p)&0xff) << 8)
656#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
657#define MAX_PACKET(p) (((p)&0xffff) << 16)
658#define MAX_PACKET_MASK (0xffff << 16)
659#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
660
661
662
663
664#define GET_MAX_PACKET(p) ((p) & 0x7ff)
665
666
667#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
668#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
669#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
670
671
672#define EP_CTX_CYCLE_MASK (1 << 0)
673
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681
682struct xhci_input_control_ctx {
683 __le32 drop_flags;
684 __le32 add_flags;
685 __le32 rsvd2[6];
686};
687
688#define EP_IS_ADDED(ctrl_ctx, i) \
689 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
690#define EP_IS_DROPPED(ctrl_ctx, i) \
691 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
692
693
694
695
696
697struct xhci_command {
698
699 struct xhci_container_ctx *in_ctx;
700 u32 status;
701
702
703
704 struct completion *completion;
705 union xhci_trb *command_trb;
706 struct list_head cmd_list;
707};
708
709
710#define DROP_EP(x) (0x1 << x)
711
712#define ADD_EP(x) (0x1 << x)
713
714struct xhci_stream_ctx {
715
716 __le64 stream_ring;
717
718 __le32 reserved[2];
719};
720
721
722#define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
723
724#define SCT_SEC_TR 0
725
726#define SCT_PRI_TR 1
727
728#define SCT_SSA_8 2
729#define SCT_SSA_16 3
730#define SCT_SSA_32 4
731#define SCT_SSA_64 5
732#define SCT_SSA_128 6
733#define SCT_SSA_256 7
734
735
736struct xhci_stream_info {
737 struct xhci_ring **stream_rings;
738
739 unsigned int num_streams;
740
741
742
743 struct xhci_stream_ctx *stream_ctx_array;
744 unsigned int num_stream_ctxs;
745 dma_addr_t ctx_array_dma;
746
747 struct radix_tree_root trb_address_map;
748 struct xhci_command *free_streams_command;
749};
750
751#define SMALL_STREAM_ARRAY_SIZE 256
752#define MEDIUM_STREAM_ARRAY_SIZE 1024
753
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758
759
760struct xhci_bw_info {
761
762 unsigned int ep_interval;
763
764 unsigned int mult;
765 unsigned int num_packets;
766 unsigned int max_packet_size;
767 unsigned int max_esit_payload;
768 unsigned int type;
769};
770
771
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773
774
775
776#define FS_BLOCK 1
777#define HS_BLOCK 4
778#define SS_BLOCK 16
779#define DMI_BLOCK 32
780
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784
785
786#define DMI_OVERHEAD 8
787#define DMI_OVERHEAD_BURST 4
788#define SS_OVERHEAD 8
789#define SS_OVERHEAD_BURST 32
790#define HS_OVERHEAD 26
791#define FS_OVERHEAD 20
792#define LS_OVERHEAD 128
793
794
795
796
797
798#define TT_HS_OVERHEAD (31 + 94)
799#define TT_DMI_OVERHEAD (25 + 12)
800
801
802#define FS_BW_LIMIT 1285
803#define TT_BW_LIMIT 1320
804#define HS_BW_LIMIT 1607
805#define SS_BW_LIMIT_IN 3906
806#define DMI_BW_LIMIT_IN 3906
807#define SS_BW_LIMIT_OUT 3906
808#define DMI_BW_LIMIT_OUT 3906
809
810
811#define FS_BW_RESERVED 10
812#define HS_BW_RESERVED 20
813#define SS_BW_RESERVED 10
814
815struct xhci_virt_ep {
816 struct xhci_ring *ring;
817
818 struct xhci_stream_info *stream_info;
819
820
821
822 struct xhci_ring *new_ring;
823 unsigned int ep_state;
824#define SET_DEQ_PENDING (1 << 0)
825#define EP_HALTED (1 << 1)
826#define EP_HALT_PENDING (1 << 2)
827
828#define EP_GETTING_STREAMS (1 << 3)
829#define EP_HAS_STREAMS (1 << 4)
830
831#define EP_GETTING_NO_STREAMS (1 << 5)
832
833 struct list_head cancelled_td_list;
834
835 union xhci_trb *stopped_trb;
836 struct xhci_td *stopped_td;
837 unsigned int stopped_stream;
838
839 struct timer_list stop_cmd_timer;
840 int stop_cmds_pending;
841 struct xhci_hcd *xhci;
842
843
844
845
846 struct xhci_segment *queued_deq_seg;
847 union xhci_trb *queued_deq_ptr;
848
849
850
851
852
853
854
855 bool skip;
856
857 struct xhci_bw_info bw_info;
858 struct list_head bw_endpoint_list;
859};
860
861enum xhci_overhead_type {
862 LS_OVERHEAD_TYPE = 0,
863 FS_OVERHEAD_TYPE,
864 HS_OVERHEAD_TYPE,
865};
866
867struct xhci_interval_bw {
868 unsigned int num_packets;
869
870
871
872 struct list_head endpoints;
873
874 unsigned int overhead[3];
875};
876
877#define XHCI_MAX_INTERVAL 16
878
879struct xhci_interval_bw_table {
880 unsigned int interval0_esit_payload;
881 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
882
883 unsigned int bw_used;
884 unsigned int ss_bw_in;
885 unsigned int ss_bw_out;
886};
887
888
889struct xhci_virt_device {
890 struct usb_device *udev;
891
892
893
894
895
896
897
898
899 struct xhci_container_ctx *out_ctx;
900
901 struct xhci_container_ctx *in_ctx;
902
903 struct xhci_ring **ring_cache;
904 int num_rings_cached;
905
906 int address;
907#define XHCI_MAX_RINGS_CACHED 31
908 struct xhci_virt_ep eps[31];
909 struct completion cmd_completion;
910
911 u32 cmd_status;
912 struct list_head cmd_list;
913 u8 fake_port;
914 u8 real_port;
915 struct xhci_interval_bw_table *bw_table;
916 struct xhci_tt_bw_info *tt_info;
917};
918
919
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921
922
923
924
925
926
927struct xhci_root_port_bw_info {
928 struct list_head tts;
929 unsigned int num_active_tts;
930 struct xhci_interval_bw_table bw_table;
931};
932
933struct xhci_tt_bw_info {
934 struct list_head tt_list;
935 int slot_id;
936 int ttport;
937 struct xhci_interval_bw_table bw_table;
938 int active_eps;
939};
940
941
942
943
944
945
946struct xhci_device_context_array {
947
948 __le64 dev_context_ptrs[MAX_HC_SLOTS];
949
950 dma_addr_t dma;
951};
952
953
954
955
956
957
958
959struct xhci_transfer_event {
960
961 __le64 buffer;
962 __le32 transfer_len;
963
964 __le32 flags;
965};
966
967
968#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
969
970
971#define COMP_CODE_MASK (0xff << 24)
972#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
973#define COMP_SUCCESS 1
974
975#define COMP_DB_ERR 2
976
977#define COMP_BABBLE 3
978
979#define COMP_TX_ERR 4
980
981#define COMP_TRB_ERR 5
982
983#define COMP_STALL 6
984
985#define COMP_ENOMEM 7
986
987#define COMP_BW_ERR 8
988
989#define COMP_ENOSLOTS 9
990
991#define COMP_STREAM_ERR 10
992
993#define COMP_EBADSLT 11
994
995#define COMP_EBADEP 12
996
997#define COMP_SHORT_TX 13
998
999#define COMP_UNDERRUN 14
1000
1001#define COMP_OVERRUN 15
1002
1003#define COMP_VF_FULL 16
1004
1005#define COMP_EINVAL 17
1006
1007#define COMP_BW_OVER 18
1008
1009#define COMP_CTX_STATE 19
1010
1011#define COMP_PING_ERR 20
1012
1013#define COMP_ER_FULL 21
1014
1015#define COMP_DEV_ERR 22
1016
1017#define COMP_MISSED_INT 23
1018
1019#define COMP_CMD_STOP 24
1020
1021#define COMP_CMD_ABORT 25
1022
1023#define COMP_STOP 26
1024
1025#define COMP_STOP_INVAL 27
1026
1027#define COMP_DBG_ABORT 28
1028
1029#define COMP_MEL_ERR 29
1030
1031
1032#define COMP_BUFF_OVER 31
1033
1034#define COMP_ISSUES 32
1035
1036#define COMP_UNKNOWN 33
1037
1038#define COMP_STRID_ERR 34
1039
1040#define COMP_2ND_BW_ERR 35
1041
1042#define COMP_SPLIT_ERR 36
1043
1044struct xhci_link_trb {
1045
1046 __le64 segment_ptr;
1047 __le32 intr_target;
1048 __le32 control;
1049};
1050
1051
1052#define LINK_TOGGLE (0x1<<1)
1053
1054
1055struct xhci_event_cmd {
1056
1057 __le64 cmd_trb;
1058 __le32 status;
1059 __le32 flags;
1060};
1061
1062
1063
1064
1065#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1066#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1067
1068
1069#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1070#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1071
1072#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1073#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1074#define LAST_EP_INDEX 30
1075
1076
1077#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1078#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1079
1080
1081
1082
1083#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1084
1085
1086
1087#define TRB_LEN(p) ((p) & 0x1ffff)
1088
1089#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1090#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1091#define TRB_TBC(p) (((p) & 0x3) << 7)
1092#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1093
1094
1095#define TRB_CYCLE (1<<0)
1096
1097
1098
1099
1100#define TRB_ENT (1<<1)
1101
1102#define TRB_ISP (1<<2)
1103
1104#define TRB_NO_SNOOP (1<<3)
1105
1106#define TRB_CHAIN (1<<4)
1107
1108#define TRB_IOC (1<<5)
1109
1110#define TRB_IDT (1<<6)
1111
1112
1113#define TRB_BEI (1<<9)
1114
1115
1116#define TRB_DIR_IN (1<<16)
1117#define TRB_TX_TYPE(p) ((p) << 16)
1118#define TRB_DATA_OUT 2
1119#define TRB_DATA_IN 3
1120
1121
1122#define TRB_SIA (1<<31)
1123
1124struct xhci_generic_trb {
1125 __le32 field[4];
1126};
1127
1128union xhci_trb {
1129 struct xhci_link_trb link;
1130 struct xhci_transfer_event trans_event;
1131 struct xhci_event_cmd event_cmd;
1132 struct xhci_generic_trb generic;
1133};
1134
1135
1136#define TRB_TYPE_BITMASK (0xfc00)
1137#define TRB_TYPE(p) ((p) << 10)
1138#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1139
1140
1141#define TRB_NORMAL 1
1142
1143#define TRB_SETUP 2
1144
1145#define TRB_DATA 3
1146
1147#define TRB_STATUS 4
1148
1149#define TRB_ISOC 5
1150
1151#define TRB_LINK 6
1152#define TRB_EVENT_DATA 7
1153
1154#define TRB_TR_NOOP 8
1155
1156
1157#define TRB_ENABLE_SLOT 9
1158
1159#define TRB_DISABLE_SLOT 10
1160
1161#define TRB_ADDR_DEV 11
1162
1163#define TRB_CONFIG_EP 12
1164
1165#define TRB_EVAL_CONTEXT 13
1166
1167#define TRB_RESET_EP 14
1168
1169#define TRB_STOP_RING 15
1170
1171#define TRB_SET_DEQ 16
1172
1173#define TRB_RESET_DEV 17
1174
1175#define TRB_FORCE_EVENT 18
1176
1177#define TRB_NEG_BANDWIDTH 19
1178
1179#define TRB_SET_LT 20
1180
1181#define TRB_GET_BW 21
1182
1183#define TRB_FORCE_HEADER 22
1184
1185#define TRB_CMD_NOOP 23
1186
1187
1188
1189#define TRB_TRANSFER 32
1190
1191#define TRB_COMPLETION 33
1192
1193#define TRB_PORT_STATUS 34
1194
1195#define TRB_BANDWIDTH_EVENT 35
1196
1197#define TRB_DOORBELL 36
1198
1199#define TRB_HC_EVENT 37
1200
1201#define TRB_DEV_NOTE 38
1202
1203#define TRB_MFINDEX_WRAP 39
1204
1205
1206
1207#define TRB_NEC_CMD_COMP 48
1208
1209#define TRB_NEC_GET_FW 49
1210
1211#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1212
1213#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1214 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1215#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1216 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1217
1218#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1219#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1220
1221
1222
1223
1224
1225
1226#define TRBS_PER_SEGMENT 64
1227
1228#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1229#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1230#define SEGMENT_SHIFT (__ffs(SEGMENT_SIZE))
1231
1232#define TRB_MAX_BUFF_SHIFT 16
1233#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1234
1235struct xhci_segment {
1236 union xhci_trb *trbs;
1237
1238 struct xhci_segment *next;
1239 dma_addr_t dma;
1240};
1241
1242struct xhci_td {
1243 struct list_head td_list;
1244 struct list_head cancelled_td_list;
1245 struct urb *urb;
1246 struct xhci_segment *start_seg;
1247 union xhci_trb *first_trb;
1248 union xhci_trb *last_trb;
1249};
1250
1251struct xhci_dequeue_state {
1252 struct xhci_segment *new_deq_seg;
1253 union xhci_trb *new_deq_ptr;
1254 int new_cycle_state;
1255};
1256
1257enum xhci_ring_type {
1258 TYPE_CTRL = 0,
1259 TYPE_ISOC,
1260 TYPE_BULK,
1261 TYPE_INTR,
1262 TYPE_STREAM,
1263 TYPE_COMMAND,
1264 TYPE_EVENT,
1265};
1266
1267struct xhci_ring {
1268 struct xhci_segment *first_seg;
1269 struct xhci_segment *last_seg;
1270 union xhci_trb *enqueue;
1271 struct xhci_segment *enq_seg;
1272 unsigned int enq_updates;
1273 union xhci_trb *dequeue;
1274 struct xhci_segment *deq_seg;
1275 unsigned int deq_updates;
1276 struct list_head td_list;
1277
1278
1279
1280
1281
1282 u32 cycle_state;
1283 unsigned int stream_id;
1284 unsigned int num_segs;
1285 unsigned int num_trbs_free;
1286 unsigned int num_trbs_free_temp;
1287 enum xhci_ring_type type;
1288 bool last_td_was_short;
1289};
1290
1291struct xhci_erst_entry {
1292
1293 __le64 seg_addr;
1294 __le32 seg_size;
1295
1296 __le32 rsvd;
1297};
1298
1299struct xhci_erst {
1300 struct xhci_erst_entry *entries;
1301 unsigned int num_entries;
1302
1303 dma_addr_t erst_dma_addr;
1304
1305 unsigned int erst_size;
1306};
1307
1308struct xhci_scratchpad {
1309 u64 *sp_array;
1310 dma_addr_t sp_dma;
1311 void **sp_buffers;
1312 dma_addr_t *sp_dma_buffers;
1313};
1314
1315struct urb_priv {
1316 int length;
1317 int td_cnt;
1318 struct xhci_td *td[0];
1319};
1320
1321
1322
1323
1324
1325
1326#define ERST_NUM_SEGS 1
1327
1328#define ERST_SIZE 64
1329
1330#define ERST_ENTRIES 1
1331
1332#define POLL_TIMEOUT 60
1333
1334#define XHCI_STOP_EP_CMD_TIMEOUT 5
1335
1336
1337struct s3_save {
1338 u32 command;
1339 u32 dev_nt;
1340 u64 dcbaa_ptr;
1341 u32 config_reg;
1342 u32 irq_pending;
1343 u32 irq_control;
1344 u32 erst_size;
1345 u64 erst_base;
1346 u64 erst_dequeue;
1347};
1348
1349
1350struct dev_info {
1351 u32 dev_id;
1352 struct list_head list;
1353};
1354
1355struct xhci_bus_state {
1356 unsigned long bus_suspended;
1357 unsigned long next_statechange;
1358
1359
1360
1361 u32 port_c_suspend;
1362 u32 suspended_ports;
1363 u32 port_remote_wakeup;
1364 unsigned long resume_done[USB_MAXCHILDREN];
1365};
1366
1367static inline unsigned int hcd_index(struct usb_hcd *hcd)
1368{
1369 if (hcd->speed == HCD_USB3)
1370 return 0;
1371 else
1372 return 1;
1373}
1374
1375
1376struct xhci_hcd {
1377 struct usb_hcd *main_hcd;
1378 struct usb_hcd *shared_hcd;
1379
1380 struct xhci_cap_regs __iomem *cap_regs;
1381 struct xhci_op_regs __iomem *op_regs;
1382 struct xhci_run_regs __iomem *run_regs;
1383 struct xhci_doorbell_array __iomem *dba;
1384
1385 struct xhci_intr_reg __iomem *ir_set;
1386
1387
1388 __u32 hcs_params1;
1389 __u32 hcs_params2;
1390 __u32 hcs_params3;
1391 __u32 hcc_params;
1392
1393 spinlock_t lock;
1394
1395
1396 u8 sbrn;
1397 u16 hci_version;
1398 u8 max_slots;
1399 u8 max_interrupters;
1400 u8 max_ports;
1401 u8 isoc_threshold;
1402 int event_ring_max;
1403 int addr_64;
1404
1405 int page_size;
1406
1407 int page_shift;
1408
1409 int msix_count;
1410 struct msix_entry *msix_entries;
1411
1412 struct xhci_device_context_array *dcbaa;
1413 struct xhci_ring *cmd_ring;
1414 unsigned int cmd_ring_reserved_trbs;
1415 struct xhci_ring *event_ring;
1416 struct xhci_erst erst;
1417
1418 struct xhci_scratchpad *scratchpad;
1419
1420 struct list_head lpm_failed_devs;
1421
1422
1423 struct completion addr_dev;
1424 int slot_id;
1425
1426 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1427
1428 struct xhci_root_port_bw_info *rh_bw;
1429
1430
1431 struct dma_pool *device_pool;
1432 struct dma_pool *segment_pool;
1433 struct dma_pool *small_streams_pool;
1434 struct dma_pool *medium_streams_pool;
1435
1436#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1437
1438 struct timer_list event_ring_timer;
1439 int zombie;
1440#endif
1441
1442 unsigned int xhc_state;
1443
1444 u32 command;
1445 struct s3_save s3;
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458#define XHCI_STATE_DYING (1 << 0)
1459#define XHCI_STATE_HALTED (1 << 1)
1460
1461 int error_bitmask;
1462 unsigned int quirks;
1463#define XHCI_LINK_TRB_QUIRK (1 << 0)
1464#define XHCI_RESET_EP_QUIRK (1 << 1)
1465#define XHCI_NEC_HOST (1 << 2)
1466#define XHCI_AMD_PLL_FIX (1 << 3)
1467#define XHCI_SPURIOUS_SUCCESS (1 << 4)
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477#define XHCI_EP_LIMIT_QUIRK (1 << 5)
1478#define XHCI_BROKEN_MSI (1 << 6)
1479#define XHCI_RESET_ON_RESUME (1 << 7)
1480#define XHCI_SW_BW_CHECKING (1 << 8)
1481#define XHCI_AMD_0x96_HOST (1 << 9)
1482 unsigned int num_active_eps;
1483 unsigned int limit_active_eps;
1484
1485 struct xhci_bus_state bus_state[2];
1486
1487 u8 *port_array;
1488
1489 __le32 __iomem **usb3_ports;
1490 unsigned int num_usb3_ports;
1491
1492 __le32 __iomem **usb2_ports;
1493 unsigned int num_usb2_ports;
1494
1495 unsigned sw_lpm_support:1;
1496
1497 unsigned hw_lpm_support:1;
1498};
1499
1500
1501static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1502{
1503 return *((struct xhci_hcd **) (hcd->hcd_priv));
1504}
1505
1506static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1507{
1508 return xhci->main_hcd;
1509}
1510
1511#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1512#define XHCI_DEBUG 1
1513#else
1514#define XHCI_DEBUG 0
1515#endif
1516
1517#define xhci_dbg(xhci, fmt, args...) \
1518 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1519#define xhci_info(xhci, fmt, args...) \
1520 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1521#define xhci_err(xhci, fmt, args...) \
1522 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1523#define xhci_warn(xhci, fmt, args...) \
1524 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1525
1526
1527
1528static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1529 __le32 __iomem *regs)
1530{
1531 return readl(regs);
1532}
1533static inline void xhci_writel(struct xhci_hcd *xhci,
1534 const unsigned int val, __le32 __iomem *regs)
1535{
1536 writel(val, regs);
1537}
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1549 __le64 __iomem *regs)
1550{
1551 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1552 u64 val_lo = readl(ptr);
1553 u64 val_hi = readl(ptr + 1);
1554 return val_lo + (val_hi << 32);
1555}
1556static inline void xhci_write_64(struct xhci_hcd *xhci,
1557 const u64 val, __le64 __iomem *regs)
1558{
1559 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1560 u32 val_lo = lower_32_bits(val);
1561 u32 val_hi = upper_32_bits(val);
1562
1563 writel(val_lo, ptr);
1564 writel(val_hi, ptr + 1);
1565}
1566
1567static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1568{
1569 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1570}
1571
1572
1573void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1574void xhci_print_registers(struct xhci_hcd *xhci);
1575void xhci_dbg_regs(struct xhci_hcd *xhci);
1576void xhci_print_run_regs(struct xhci_hcd *xhci);
1577void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1578void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1579void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1580void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1581void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1582void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1583void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1584void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1585char *xhci_get_slot_state(struct xhci_hcd *xhci,
1586 struct xhci_container_ctx *ctx);
1587void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1588 unsigned int slot_id, unsigned int ep_index,
1589 struct xhci_virt_ep *ep);
1590
1591
1592void xhci_mem_cleanup(struct xhci_hcd *xhci);
1593int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1594void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1595int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1596int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1597void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1598 struct usb_device *udev);
1599unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1600unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1601unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1602unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1603void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1604void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1605 struct xhci_bw_info *ep_bw,
1606 struct xhci_interval_bw_table *bw_table,
1607 struct usb_device *udev,
1608 struct xhci_virt_ep *virt_ep,
1609 struct xhci_tt_bw_info *tt_info);
1610void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1611 struct xhci_virt_device *virt_dev,
1612 int old_active_eps);
1613void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1614void xhci_update_bw_info(struct xhci_hcd *xhci,
1615 struct xhci_container_ctx *in_ctx,
1616 struct xhci_input_control_ctx *ctrl_ctx,
1617 struct xhci_virt_device *virt_dev);
1618void xhci_endpoint_copy(struct xhci_hcd *xhci,
1619 struct xhci_container_ctx *in_ctx,
1620 struct xhci_container_ctx *out_ctx,
1621 unsigned int ep_index);
1622void xhci_slot_copy(struct xhci_hcd *xhci,
1623 struct xhci_container_ctx *in_ctx,
1624 struct xhci_container_ctx *out_ctx);
1625int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1626 struct usb_device *udev, struct usb_host_endpoint *ep,
1627 gfp_t mem_flags);
1628void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1629int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1630 unsigned int num_trbs, gfp_t flags);
1631void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1632 struct xhci_virt_device *virt_dev,
1633 unsigned int ep_index);
1634struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1635 unsigned int num_stream_ctxs,
1636 unsigned int num_streams, gfp_t flags);
1637void xhci_free_stream_info(struct xhci_hcd *xhci,
1638 struct xhci_stream_info *stream_info);
1639void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1640 struct xhci_ep_ctx *ep_ctx,
1641 struct xhci_stream_info *stream_info);
1642void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1643 struct xhci_ep_ctx *ep_ctx,
1644 struct xhci_virt_ep *ep);
1645void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1646 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1647struct xhci_ring *xhci_dma_to_transfer_ring(
1648 struct xhci_virt_ep *ep,
1649 u64 address);
1650struct xhci_ring *xhci_stream_id_to_ring(
1651 struct xhci_virt_device *dev,
1652 unsigned int ep_index,
1653 unsigned int stream_id);
1654struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1655 bool allocate_in_ctx, bool allocate_completion,
1656 gfp_t mem_flags);
1657void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1658void xhci_free_command(struct xhci_hcd *xhci,
1659 struct xhci_command *command);
1660
1661#ifdef CONFIG_PCI
1662
1663int xhci_register_pci(void);
1664void xhci_unregister_pci(void);
1665#else
1666static inline int xhci_register_pci(void) { return 0; }
1667static inline void xhci_unregister_pci(void) {}
1668#endif
1669
1670#if defined(CONFIG_USB_XHCI_PLATFORM) \
1671 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1672int xhci_register_plat(void);
1673void xhci_unregister_plat(void);
1674#else
1675static inline int xhci_register_plat(void)
1676{ return 0; }
1677static inline void xhci_unregister_plat(void)
1678{ }
1679#endif
1680
1681
1682typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1683void xhci_quiesce(struct xhci_hcd *xhci);
1684int xhci_halt(struct xhci_hcd *xhci);
1685int xhci_reset(struct xhci_hcd *xhci);
1686int xhci_init(struct usb_hcd *hcd);
1687int xhci_run(struct usb_hcd *hcd);
1688void xhci_stop(struct usb_hcd *hcd);
1689void xhci_shutdown(struct usb_hcd *hcd);
1690int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1691
1692#ifdef CONFIG_PM
1693int xhci_suspend(struct xhci_hcd *xhci);
1694int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1695#else
1696#define xhci_suspend NULL
1697#define xhci_resume NULL
1698#endif
1699
1700int xhci_get_frame(struct usb_hcd *hcd);
1701irqreturn_t xhci_irq(struct usb_hcd *hcd);
1702irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1703int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1704void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1705int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1706 struct xhci_virt_device *virt_dev,
1707 struct usb_device *hdev,
1708 struct usb_tt *tt, gfp_t mem_flags);
1709int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1710 struct usb_host_endpoint **eps, unsigned int num_eps,
1711 unsigned int num_streams, gfp_t mem_flags);
1712int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1713 struct usb_host_endpoint **eps, unsigned int num_eps,
1714 gfp_t mem_flags);
1715int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1716int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1717int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1718 struct usb_device *udev, int enable);
1719int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1720 struct usb_tt *tt, gfp_t mem_flags);
1721int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1722int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1723int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1724int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1725void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1726int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1727int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1728void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1729
1730
1731dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1732struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1733 union xhci_trb *start_trb, union xhci_trb *end_trb,
1734 dma_addr_t suspect_dma);
1735int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1736void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1737int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1738int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1739 u32 slot_id);
1740int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1741 u32 field1, u32 field2, u32 field3, u32 field4);
1742int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1743 unsigned int ep_index, int suspend);
1744int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1745 int slot_id, unsigned int ep_index);
1746int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1747 int slot_id, unsigned int ep_index);
1748int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1749 int slot_id, unsigned int ep_index);
1750int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1751 struct urb *urb, int slot_id, unsigned int ep_index);
1752int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1753 u32 slot_id, bool command_must_succeed);
1754int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1755 u32 slot_id);
1756int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1757 unsigned int ep_index);
1758int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1759void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1760 unsigned int slot_id, unsigned int ep_index,
1761 unsigned int stream_id, struct xhci_td *cur_td,
1762 struct xhci_dequeue_state *state);
1763void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1764 unsigned int slot_id, unsigned int ep_index,
1765 unsigned int stream_id,
1766 struct xhci_dequeue_state *deq_state);
1767void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1768 struct usb_device *udev, unsigned int ep_index);
1769void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1770 unsigned int slot_id, unsigned int ep_index,
1771 struct xhci_dequeue_state *deq_state);
1772void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1773void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1774 unsigned int ep_index, unsigned int stream_id);
1775
1776
1777void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1778 int port_id, u32 link_state);
1779void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1780 int port_id, u32 port_bit);
1781int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1782 char *buf, u16 wLength);
1783int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1784
1785#ifdef CONFIG_PM
1786int xhci_bus_suspend(struct usb_hcd *hcd);
1787int xhci_bus_resume(struct usb_hcd *hcd);
1788#else
1789#define xhci_bus_suspend NULL
1790#define xhci_bus_resume NULL
1791#endif
1792
1793u32 xhci_port_state_to_neutral(u32 state);
1794int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1795 u16 port);
1796void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1797
1798
1799struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1800struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1801struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1802
1803#endif
1804