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20#ifndef __SH_FLCTL_H__
21#define __SH_FLCTL_H__
22
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/partitions.h>
26#include <linux/pm_qos.h>
27
28
29#define FLCMNCR(f) (f->reg + 0x0)
30#define FLCMDCR(f) (f->reg + 0x4)
31#define FLCMCDR(f) (f->reg + 0x8)
32#define FLADR(f) (f->reg + 0xC)
33#define FLADR2(f) (f->reg + 0x3C)
34#define FLDATAR(f) (f->reg + 0x10)
35#define FLDTCNTR(f) (f->reg + 0x14)
36#define FLINTDMACR(f) (f->reg + 0x18)
37#define FLBSYTMR(f) (f->reg + 0x1C)
38#define FLBSYCNT(f) (f->reg + 0x20)
39#define FLDTFIFO(f) (f->reg + 0x24)
40#define FLECFIFO(f) (f->reg + 0x28)
41#define FLTRCR(f) (f->reg + 0x2C)
42#define FLHOLDCR(f) (f->reg + 0x38)
43#define FL4ECCRESULT0(f) (f->reg + 0x80)
44#define FL4ECCRESULT1(f) (f->reg + 0x84)
45#define FL4ECCRESULT2(f) (f->reg + 0x88)
46#define FL4ECCRESULT3(f) (f->reg + 0x8C)
47#define FL4ECCCR(f) (f->reg + 0x90)
48#define FL4ECCCNT(f) (f->reg + 0x94)
49#define FLERRADR(f) (f->reg + 0x98)
50
51
52#define ECCPOS2 (0x1 << 25)
53#define _4ECCCNTEN (0x1 << 24)
54#define _4ECCEN (0x1 << 23)
55#define _4ECCCORRECT (0x1 << 22)
56#define SHBUSSEL (0x1 << 20)
57#define SEL_16BIT (0x1 << 19)
58#define SNAND_E (0x1 << 18)
59#define QTSEL_E (0x1 << 17)
60#define ENDIAN (0x1 << 16)
61#define FCKSEL_E (0x1 << 15)
62#define ECCPOS_00 (0x00 << 12)
63#define ECCPOS_01 (0x01 << 12)
64#define ECCPOS_02 (0x02 << 12)
65#define ACM_SACCES_MODE (0x01 << 10)
66#define NANWF_E (0x1 << 9)
67#define SE_D (0x1 << 8)
68#define CE1_ENABLE (0x1 << 4)
69#define CE0_ENABLE (0x1 << 3)
70#define TYPESEL_SET (0x1 << 0)
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81
82#define PULSE3 (0x1 << 27)
83#define PULSE2 (0x1 << 17)
84#define PULSE1 (0x1 << 15)
85#define PULSE0 (0x1 << 9)
86#define CLK_8B_0_5 PULSE1
87#define CLK_8B_1 0x0
88#define CLK_8B_1_5 (PULSE1 | PULSE2)
89#define CLK_8B_2 PULSE0
90#define CLK_8B_3 (PULSE0 | PULSE1 | PULSE2)
91#define CLK_8B_4 (PULSE0 | PULSE2)
92#define CLK_16B_6L_2H PULSE0
93#define CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2)
94#define CLK_16B_12L_4H (PULSE0 | PULSE2)
95
96
97#define ADRCNT2_E (0x1 << 31)
98#define ADRMD_E (0x1 << 26)
99#define CDSRC_E (0x1 << 25)
100#define DOSR_E (0x1 << 24)
101#define SELRW (0x1 << 21)
102#define DOADR_E (0x1 << 20)
103#define ADRCNT_1 (0x00 << 18)
104#define ADRCNT_2 (0x01 << 18)
105#define ADRCNT_3 (0x02 << 18)
106#define ADRCNT_4 (0x03 << 18)
107#define DOCMD2_E (0x1 << 17)
108#define DOCMD1_E (0x1 << 16)
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110
111#define TRSTRT (0x1 << 0)
112#define TREND (0x1 << 1)
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120
121#define HOLDEN (0x1 << 0)
122
123
124#define _4ECCFA (0x1 << 2)
125#define _4ECCEND (0x1 << 1)
126#define _4ECCEXST (0x1 << 0)
127
128#define INIT_FL4ECCRESULT_VAL 0x03FF03FF
129#define LOOP_TIMEOUT_MAX 0x00010000
130
131struct sh_flctl {
132 struct mtd_info mtd;
133 struct nand_chip chip;
134 struct platform_device *pdev;
135 struct dev_pm_qos_request pm_qos;
136 void __iomem *reg;
137
138 uint8_t done_buff[2048 + 64];
139 int read_bytes;
140 int index;
141 int seqin_column;
142 int seqin_page_addr;
143 uint32_t seqin_read_cmd;
144 int erase1_page_addr;
145 uint32_t erase_ADRCNT;
146 uint32_t rw_ADRCNT;
147 uint32_t flcmncr_base;
148
149 int hwecc_cant_correct[4];
150
151 unsigned page_size:1;
152 unsigned hwecc:1;
153 unsigned holden:1;
154 unsigned qos_request:1;
155};
156
157struct sh_flctl_platform_data {
158 struct mtd_partition *parts;
159 int nr_parts;
160 unsigned long flcmncr_val;
161
162 unsigned has_hwecc:1;
163 unsigned use_holden:1;
164};
165
166static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
167{
168 return container_of(mtdinfo, struct sh_flctl, mtd);
169}
170
171#endif
172