LXR linux/include/linux/ssb/ssb_driver

   1/*
   2 * Hardware-specific External Interface I/O core definitions
   3 * for the BCM47xx family of SiliconBackplane-based chips.
   4 *
   5 * The External Interface core supports a total of three external chip selects
   6 * supporting external interfaces. One of the external chip selects is
   7 * used for Flash, one is used for PCMCIA, and the other may be
   8 * programmed to support either a synchronous interface or an
   9 * asynchronous interface. The asynchronous interface can be used to
  10 * support external devices such as UARTs and the BCM2019 Bluetooth
  11 * baseband processor.
  12 * The external interface core also contains 2 on-chip 16550 UARTs, clock
  13 * frequency control, a watchdog interrupt timer, and a GPIO interface.
  14 *
  15 * Copyright 2005, Broadcom Corporation
  16 * Copyright 2006, Michael Buesch
  17 *
  18 * Licensed under the GPL version 2. See COPYING for details.
  19 */
  20#ifndef LINUX_SSB_EXTIFCORE_H_
  21#define LINUX_SSB_EXTIFCORE_H_
  22
  23/* external interface address space */
  24#define SSB_EXTIF_PCMCIA_MEMBASE(x)     (x)
  25#define SSB_EXTIF_PCMCIA_IOBASE(x)      ((x) + 0x100000)
  26#define SSB_EXTIF_PCMCIA_CFGBASE(x)     ((x) + 0x200000)
  27#define SSB_EXTIF_CFGIF_BASE(x)         ((x) + 0x800000)
  28#define SSB_EXTIF_FLASH_BASE(x)         ((x) + 0xc00000)
  29
  30#define SSB_EXTIF_NR_GPIOOUT            5
  31/* GPIO NOTE:
  32 * The multiple instances of output and output enable registers
  33 * are present to allow driver software for multiple cores to control
  34 * gpio outputs without needing to share a single register pair.
  35 * Use the following helper macro to get a register offset value.
  36 */
  37#define SSB_EXTIF_GPIO_OUT(index)       ({              \
  38        BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
  39        SSB_EXTIF_GPIO_OUT_BASE + ((index) * 8);        \
  40                                        })
  41#define SSB_EXTIF_GPIO_OUTEN(index)     ({              \
  42        BUILD_BUG_ON(index >= SSB_EXTIF_NR_GPIOOUT);    \
  43        SSB_EXTIF_GPIO_OUTEN_BASE + ((index) * 8);      \
  44                                        })
  45
  46/** EXTIF core registers **/
  47
  48#define SSB_EXTIF_CTL                   0x0000
  49#define  SSB_EXTIF_CTL_UARTEN           (1 << 0) /* UART enable */
  50#define SSB_EXTIF_EXTSTAT               0x0004
  51#define  SSB_EXTIF_EXTSTAT_EMODE        (1 << 0) /* Endian mode (ro) */
  52#define  SSB_EXTIF_EXTSTAT_EIRQPIN      (1 << 1) /* External interrupt pin (ro) */
  53#define  SSB_EXTIF_EXTSTAT_GPIOIRQPIN   (1 << 2) /* GPIO interrupt pin (ro) */
  54#define SSB_EXTIF_PCMCIA_CFG            0x0010
  55#define SSB_EXTIF_PCMCIA_MEMWAIT        0x0014
  56#define SSB_EXTIF_PCMCIA_ATTRWAIT       0x0018
  57#define SSB_EXTIF_PCMCIA_IOWAIT         0x001C
  58#define SSB_EXTIF_PROG_CFG              0x0020
  59#define SSB_EXTIF_PROG_WAITCNT          0x0024
  60#define SSB_EXTIF_FLASH_CFG             0x0028
  61#define SSB_EXTIF_FLASH_WAITCNT         0x002C
  62#define SSB_EXTIF_WATCHDOG              0x0040
  63#define SSB_EXTIF_CLOCK_N               0x0044
  64#define SSB_EXTIF_CLOCK_SB              0x0048
  65#define SSB_EXTIF_CLOCK_PCI             0x004C
  66#define SSB_EXTIF_CLOCK_MII             0x0050
  67#define SSB_EXTIF_GPIO_IN               0x0060
  68#define SSB_EXTIF_GPIO_OUT_BASE         0x0064
  69#define SSB_EXTIF_GPIO_OUTEN_BASE       0x0068
  70#define SSB_EXTIF_EJTAG_OUTEN           0x0090
  71#define SSB_EXTIF_GPIO_INTPOL           0x0094
  72#define SSB_EXTIF_GPIO_INTMASK          0x0098
  73#define SSB_EXTIF_UART_DATA             0x0300
  74#define SSB_EXTIF_UART_TIMER            0x0310
  75#define SSB_EXTIF_UART_FCR              0x0320
  76#define SSB_EXTIF_UART_LCR              0x0330
  77#define SSB_EXTIF_UART_MCR              0x0340
  78#define SSB_EXTIF_UART_LSR              0x0350
  79#define SSB_EXTIF_UART_MSR              0x0360
  80#define SSB_EXTIF_UART_SCRATCH          0x0370
  81
  82
  83
  84
  85/* pcmcia/prog/flash_config */
  86#define SSB_EXTCFG_EN                   (1 << 0)        /* enable */
  87#define SSB_EXTCFG_MODE                 0xE             /* mode */
  88#define SSB_EXTCFG_MODE_SHIFT           1
  89#define  SSB_EXTCFG_MODE_FLASH          0x0             /* flash/asynchronous mode */
  90#define  SSB_EXTCFG_MODE_SYNC           0x2             /* synchronous mode */
  91#define  SSB_EXTCFG_MODE_PCMCIA         0x4             /* pcmcia mode */
  92#define SSB_EXTCFG_DS16                 (1 << 4)        /* destsize:  0=8bit, 1=16bit */
  93#define SSB_EXTCFG_BSWAP                (1 << 5)        /* byteswap */
  94#define SSB_EXTCFG_CLKDIV               0xC0            /* clock divider */
  95#define SSB_EXTCFG_CLKDIV_SHIFT         6
  96#define  SSB_EXTCFG_CLKDIV_2            0x0             /* backplane/2 */
  97#define  SSB_EXTCFG_CLKDIV_3            0x40            /* backplane/3 */
  98#define  SSB_EXTCFG_CLKDIV_4            0x80            /* backplane/4 */
  99#define SSB_EXTCFG_CLKEN                (1 << 8)        /* clock enable */
 100#define SSB_EXTCFG_STROBE               (1 << 9)        /* size/bytestrobe (synch only) */
 101
 102/* pcmcia_memwait */
 103#define SSB_PCMCIA_MEMW_0               0x0000003F      /* waitcount0 */
 104#define SSB_PCMCIA_MEMW_1               0x00001F00      /* waitcount1 */
 105#define SSB_PCMCIA_MEMW_1_SHIFT         8
 106#define SSB_PCMCIA_MEMW_2               0x001F0000      /* waitcount2 */
 107#define SSB_PCMCIA_MEMW_2_SHIFT         16
 108#define SSB_PCMCIA_MEMW_3               0x1F000000      /* waitcount3 */
 109#define SSB_PCMCIA_MEMW_3_SHIFT         24
 110
 111/* pcmcia_attrwait */
 112#define SSB_PCMCIA_ATTW_0               0x0000003F      /* waitcount0 */
 113#define SSB_PCMCIA_ATTW_1               0x00001F00      /* waitcount1 */
 114#define SSB_PCMCIA_ATTW_1_SHIFT         8
 115#define SSB_PCMCIA_ATTW_2               0x001F0000      /* waitcount2 */
 116#define SSB_PCMCIA_ATTW_2_SHIFT         16
 117#define SSB_PCMCIA_ATTW_3               0x1F000000      /* waitcount3 */
 118#define SSB_PCMCIA_ATTW_3_SHIFT         24
 119
 120/* pcmcia_iowait */
 121#define SSB_PCMCIA_IOW_0                0x0000003F      /* waitcount0 */
 122#define SSB_PCMCIA_IOW_1                0x00001F00      /* waitcount1 */
 123#define SSB_PCMCIA_IOW_1_SHIFT          8
 124#define SSB_PCMCIA_IOW_2                0x001F0000      /* waitcount2 */
 125#define SSB_PCMCIA_IOW_2_SHIFT          16
 126#define SSB_PCMCIA_IOW_3                0x1F000000      /* waitcount3 */
 127#define SSB_PCMCIA_IOW_3_SHIFT          24
 128
 129/* prog_waitcount */
 130#define SSB_PROG_WCNT_0                 0x0000001F      /* waitcount0 */
 131#define SSB_PROG_WCNT_1                 0x00001F00      /* waitcount1 */
 132#define SSB_PROG_WCNT_1_SHIFT           8
 133#define SSB_PROG_WCNT_2                 0x001F0000      /* waitcount2 */
 134#define SSB_PROG_WCNT_2_SHIFT           16
 135#define SSB_PROG_WCNT_3                 0x1F000000      /* waitcount3 */
 136#define SSB_PROG_WCNT_3_SHIFT           24
 137
 138#define SSB_PROG_W0                     0x0000000C
 139#define SSB_PROG_W1                     0x00000A00
 140#define SSB_PROG_W2                     0x00020000
 141#define SSB_PROG_W3                     0x01000000
 142
 143/* flash_waitcount */
 144#define SSB_FLASH_WCNT_0                0x0000001F      /* waitcount0 */
 145#define SSB_FLASH_WCNT_1                0x00001F00      /* waitcount1 */
 146#define SSB_FLASH_WCNT_1_SHIFT          8
 147#define SSB_FLASH_WCNT_2                0x001F0000      /* waitcount2 */
 148#define SSB_FLASH_WCNT_2_SHIFT          16
 149#define SSB_FLASH_WCNT_3                0x1F000000      /* waitcount3 */
 150#define SSB_FLASH_WCNT_3_SHIFT          24
 151
 152/* watchdog */
 153#define SSB_EXTIF_WATCHDOG_CLK          48000000        /* Hz */
 154
 155
 156
 157#ifdef CONFIG_SSB_DRIVER_EXTIF
 158
 159struct ssb_extif {
 160        struct ssb_device *dev;
 161};
 162
 163static inline bool ssb_extif_available(struct ssb_extif *extif)
 164{
 165        return (extif->dev != NULL);
 166}
 167
 168extern void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
 169                                       u32 *plltype, u32 *n, u32 *m);
 170
 171extern void ssb_extif_timing_init(struct ssb_extif *extif,
 172                                  unsigned long ns);
 173
 174extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 175                                         u32 ticks);
 176
 177/* Extif GPIO pin access */
 178u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
 179u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value);
 180u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value);
 181u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value);
 182u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value);
 183
 184#ifdef CONFIG_SSB_SERIAL
 185extern int ssb_extif_serial_init(struct ssb_extif *extif,
 186                                 struct ssb_serial_port *ports);
 187#endif /* CONFIG_SSB_SERIAL */
 188
 189
 190#else /* CONFIG_SSB_DRIVER_EXTIF */
 191/* extif disabled */
 192
 193struct ssb_extif {
 194};
 195
 196static inline bool ssb_extif_available(struct ssb_extif *extif)
 197{
 198        return 0;
 199}
 200
 201static inline
 202void ssb_extif_get_clockcontrol(struct ssb_extif *extif,
 203                                u32 *plltype, u32 *n, u32 *m)
 204{
 205}
 206
 207static inline
 208void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
 209                                  u32 ticks)
 210{
 211}
 212
 213#endif /* CONFIG_SSB_DRIVER_EXTIF */
 214#endif /* LINUX_SSB_EXTIFCORE_H_ */
 215