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9#include <linux/device.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/physmap.h>
13#include <linux/mtd/partitions.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#include <linux/irq.h>
17#include <linux/interrupt.h>
18#include <asm/bfin5xx_spi.h>
19#include <asm/dma.h>
20#include <asm/gpio.h>
21#include <asm/nand.h>
22#include <asm/portmux.h>
23#include <asm/dpmc.h>
24#include <linux/input.h>
25
26
27
28
29const char bfin_board_name[] = "ADI BF538-EZKIT";
30
31
32
33
34
35
36#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
37static struct platform_device rtc_device = {
38 .name = "rtc-bfin",
39 .id = -1,
40};
41#endif
42
43#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
44#ifdef CONFIG_SERIAL_BFIN_UART0
45static struct resource bfin_uart0_resources[] = {
46 {
47 .start = UART0_THR,
48 .end = UART0_GCTL+2,
49 .flags = IORESOURCE_MEM,
50 },
51 {
52 .start = IRQ_UART0_TX,
53 .end = IRQ_UART0_TX,
54 .flags = IORESOURCE_IRQ,
55 },
56 {
57 .start = IRQ_UART0_RX,
58 .end = IRQ_UART0_RX,
59 .flags = IORESOURCE_IRQ,
60 },
61 {
62 .start = IRQ_UART0_ERROR,
63 .end = IRQ_UART0_ERROR,
64 .flags = IORESOURCE_IRQ,
65 },
66 {
67 .start = CH_UART0_TX,
68 .end = CH_UART0_TX,
69 .flags = IORESOURCE_DMA,
70 },
71 {
72 .start = CH_UART0_RX,
73 .end = CH_UART0_RX,
74 .flags = IORESOURCE_DMA,
75 },
76#ifdef CONFIG_BFIN_UART0_CTSRTS
77 {
78 .start = GPIO_PG7,
79 .end = GPIO_PG7,
80 .flags = IORESOURCE_IO,
81 },
82 {
83 .start = GPIO_PG6,
84 .end = GPIO_PG6,
85 .flags = IORESOURCE_IO,
86 },
87#endif
88};
89
90static unsigned short bfin_uart0_peripherals[] = {
91 P_UART0_TX, P_UART0_RX, 0
92};
93
94static struct platform_device bfin_uart0_device = {
95 .name = "bfin-uart",
96 .id = 0,
97 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
98 .resource = bfin_uart0_resources,
99 .dev = {
100 .platform_data = &bfin_uart0_peripherals,
101 },
102};
103#endif
104#ifdef CONFIG_SERIAL_BFIN_UART1
105static struct resource bfin_uart1_resources[] = {
106 {
107 .start = UART1_THR,
108 .end = UART1_GCTL+2,
109 .flags = IORESOURCE_MEM,
110 },
111 {
112 .start = IRQ_UART1_TX,
113 .end = IRQ_UART1_TX,
114 .flags = IORESOURCE_IRQ,
115 },
116 {
117 .start = IRQ_UART1_RX,
118 .end = IRQ_UART1_RX,
119 .flags = IORESOURCE_IRQ,
120 },
121 {
122 .start = IRQ_UART1_ERROR,
123 .end = IRQ_UART1_ERROR,
124 .flags = IORESOURCE_IRQ,
125 },
126 {
127 .start = CH_UART1_TX,
128 .end = CH_UART1_TX,
129 .flags = IORESOURCE_DMA,
130 },
131 {
132 .start = CH_UART1_RX,
133 .end = CH_UART1_RX,
134 .flags = IORESOURCE_DMA,
135 },
136};
137
138static unsigned short bfin_uart1_peripherals[] = {
139 P_UART1_TX, P_UART1_RX, 0
140};
141
142static struct platform_device bfin_uart1_device = {
143 .name = "bfin-uart",
144 .id = 1,
145 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
146 .resource = bfin_uart1_resources,
147 .dev = {
148 .platform_data = &bfin_uart1_peripherals,
149 },
150};
151#endif
152#ifdef CONFIG_SERIAL_BFIN_UART2
153static struct resource bfin_uart2_resources[] = {
154 {
155 .start = UART2_THR,
156 .end = UART2_GCTL+2,
157 .flags = IORESOURCE_MEM,
158 },
159 {
160 .start = IRQ_UART2_TX,
161 .end = IRQ_UART2_TX,
162 .flags = IORESOURCE_IRQ,
163 },
164 {
165 .start = IRQ_UART2_RX,
166 .end = IRQ_UART2_RX,
167 .flags = IORESOURCE_IRQ,
168 },
169 {
170 .start = IRQ_UART2_ERROR,
171 .end = IRQ_UART2_ERROR,
172 .flags = IORESOURCE_IRQ,
173 },
174 {
175 .start = CH_UART2_TX,
176 .end = CH_UART2_TX,
177 .flags = IORESOURCE_DMA,
178 },
179 {
180 .start = CH_UART2_RX,
181 .end = CH_UART2_RX,
182 .flags = IORESOURCE_DMA,
183 },
184};
185
186static unsigned short bfin_uart2_peripherals[] = {
187 P_UART2_TX, P_UART2_RX, 0
188};
189
190static struct platform_device bfin_uart2_device = {
191 .name = "bfin-uart",
192 .id = 2,
193 .num_resources = ARRAY_SIZE(bfin_uart2_resources),
194 .resource = bfin_uart2_resources,
195 .dev = {
196 .platform_data = &bfin_uart2_peripherals,
197 },
198};
199#endif
200#endif
201
202#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
203#ifdef CONFIG_BFIN_SIR0
204static struct resource bfin_sir0_resources[] = {
205 {
206 .start = 0xFFC00400,
207 .end = 0xFFC004FF,
208 .flags = IORESOURCE_MEM,
209 },
210 {
211 .start = IRQ_UART0_RX,
212 .end = IRQ_UART0_RX+1,
213 .flags = IORESOURCE_IRQ,
214 },
215 {
216 .start = CH_UART0_RX,
217 .end = CH_UART0_RX+1,
218 .flags = IORESOURCE_DMA,
219 },
220};
221static struct platform_device bfin_sir0_device = {
222 .name = "bfin_sir",
223 .id = 0,
224 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
225 .resource = bfin_sir0_resources,
226};
227#endif
228#ifdef CONFIG_BFIN_SIR1
229static struct resource bfin_sir1_resources[] = {
230 {
231 .start = 0xFFC02000,
232 .end = 0xFFC020FF,
233 .flags = IORESOURCE_MEM,
234 },
235 {
236 .start = IRQ_UART1_RX,
237 .end = IRQ_UART1_RX+1,
238 .flags = IORESOURCE_IRQ,
239 },
240 {
241 .start = CH_UART1_RX,
242 .end = CH_UART1_RX+1,
243 .flags = IORESOURCE_DMA,
244 },
245};
246static struct platform_device bfin_sir1_device = {
247 .name = "bfin_sir",
248 .id = 1,
249 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
250 .resource = bfin_sir1_resources,
251};
252#endif
253#ifdef CONFIG_BFIN_SIR2
254static struct resource bfin_sir2_resources[] = {
255 {
256 .start = 0xFFC02100,
257 .end = 0xFFC021FF,
258 .flags = IORESOURCE_MEM,
259 },
260 {
261 .start = IRQ_UART2_RX,
262 .end = IRQ_UART2_RX+1,
263 .flags = IORESOURCE_IRQ,
264 },
265 {
266 .start = CH_UART2_RX,
267 .end = CH_UART2_RX+1,
268 .flags = IORESOURCE_DMA,
269 },
270};
271static struct platform_device bfin_sir2_device = {
272 .name = "bfin_sir",
273 .id = 2,
274 .num_resources = ARRAY_SIZE(bfin_sir2_resources),
275 .resource = bfin_sir2_resources,
276};
277#endif
278#endif
279
280#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
281#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
282static struct resource bfin_sport0_uart_resources[] = {
283 {
284 .start = SPORT0_TCR1,
285 .end = SPORT0_MRCS3+4,
286 .flags = IORESOURCE_MEM,
287 },
288 {
289 .start = IRQ_SPORT0_RX,
290 .end = IRQ_SPORT0_RX+1,
291 .flags = IORESOURCE_IRQ,
292 },
293 {
294 .start = IRQ_SPORT0_ERROR,
295 .end = IRQ_SPORT0_ERROR,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static unsigned short bfin_sport0_peripherals[] = {
301 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
302 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
303};
304
305static struct platform_device bfin_sport0_uart_device = {
306 .name = "bfin-sport-uart",
307 .id = 0,
308 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
309 .resource = bfin_sport0_uart_resources,
310 .dev = {
311 .platform_data = &bfin_sport0_peripherals,
312 },
313};
314#endif
315#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
316static struct resource bfin_sport1_uart_resources[] = {
317 {
318 .start = SPORT1_TCR1,
319 .end = SPORT1_MRCS3+4,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 .start = IRQ_SPORT1_RX,
324 .end = IRQ_SPORT1_RX+1,
325 .flags = IORESOURCE_IRQ,
326 },
327 {
328 .start = IRQ_SPORT1_ERROR,
329 .end = IRQ_SPORT1_ERROR,
330 .flags = IORESOURCE_IRQ,
331 },
332};
333
334static unsigned short bfin_sport1_peripherals[] = {
335 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
336 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
337};
338
339static struct platform_device bfin_sport1_uart_device = {
340 .name = "bfin-sport-uart",
341 .id = 1,
342 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
343 .resource = bfin_sport1_uart_resources,
344 .dev = {
345 .platform_data = &bfin_sport1_peripherals,
346 },
347};
348#endif
349#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
350static struct resource bfin_sport2_uart_resources[] = {
351 {
352 .start = SPORT2_TCR1,
353 .end = SPORT2_MRCS3+4,
354 .flags = IORESOURCE_MEM,
355 },
356 {
357 .start = IRQ_SPORT2_RX,
358 .end = IRQ_SPORT2_RX+1,
359 .flags = IORESOURCE_IRQ,
360 },
361 {
362 .start = IRQ_SPORT2_ERROR,
363 .end = IRQ_SPORT2_ERROR,
364 .flags = IORESOURCE_IRQ,
365 },
366};
367
368static unsigned short bfin_sport2_peripherals[] = {
369 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
370 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
371};
372
373static struct platform_device bfin_sport2_uart_device = {
374 .name = "bfin-sport-uart",
375 .id = 2,
376 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
377 .resource = bfin_sport2_uart_resources,
378 .dev = {
379 .platform_data = &bfin_sport2_peripherals,
380 },
381};
382#endif
383#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
384static struct resource bfin_sport3_uart_resources[] = {
385 {
386 .start = SPORT3_TCR1,
387 .end = SPORT3_MRCS3+4,
388 .flags = IORESOURCE_MEM,
389 },
390 {
391 .start = IRQ_SPORT3_RX,
392 .end = IRQ_SPORT3_RX+1,
393 .flags = IORESOURCE_IRQ,
394 },
395 {
396 .start = IRQ_SPORT3_ERROR,
397 .end = IRQ_SPORT3_ERROR,
398 .flags = IORESOURCE_IRQ,
399 },
400};
401
402static unsigned short bfin_sport3_peripherals[] = {
403 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
404 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
405};
406
407static struct platform_device bfin_sport3_uart_device = {
408 .name = "bfin-sport-uart",
409 .id = 3,
410 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
411 .resource = bfin_sport3_uart_resources,
412 .dev = {
413 .platform_data = &bfin_sport3_peripherals,
414 },
415};
416#endif
417#endif
418
419#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
420static unsigned short bfin_can_peripherals[] = {
421 P_CAN0_RX, P_CAN0_TX, 0
422};
423
424static struct resource bfin_can_resources[] = {
425 {
426 .start = 0xFFC02A00,
427 .end = 0xFFC02FFF,
428 .flags = IORESOURCE_MEM,
429 },
430 {
431 .start = IRQ_CAN_RX,
432 .end = IRQ_CAN_RX,
433 .flags = IORESOURCE_IRQ,
434 },
435 {
436 .start = IRQ_CAN_TX,
437 .end = IRQ_CAN_TX,
438 .flags = IORESOURCE_IRQ,
439 },
440 {
441 .start = IRQ_CAN_ERROR,
442 .end = IRQ_CAN_ERROR,
443 .flags = IORESOURCE_IRQ,
444 },
445};
446
447static struct platform_device bfin_can_device = {
448 .name = "bfin_can",
449 .num_resources = ARRAY_SIZE(bfin_can_resources),
450 .resource = bfin_can_resources,
451 .dev = {
452 .platform_data = &bfin_can_peripherals,
453 },
454};
455#endif
456
457
458
459
460
461#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
462#include <linux/smc91x.h>
463
464static struct smc91x_platdata smc91x_info = {
465 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
466 .leda = RPC_LED_100_10,
467 .ledb = RPC_LED_TX_RX,
468};
469
470static struct resource smc91x_resources[] = {
471 {
472 .name = "smc91x-regs",
473 .start = 0x20310300,
474 .end = 0x20310300 + 16,
475 .flags = IORESOURCE_MEM,
476 }, {
477 .start = IRQ_PF0,
478 .end = IRQ_PF0,
479 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
480 },
481};
482static struct platform_device smc91x_device = {
483 .name = "smc91x",
484 .id = 0,
485 .num_resources = ARRAY_SIZE(smc91x_resources),
486 .resource = smc91x_resources,
487 .dev = {
488 .platform_data = &smc91x_info,
489 },
490};
491#endif
492
493#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
494
495#if defined(CONFIG_MTD_M25P80) \
496 || defined(CONFIG_MTD_M25P80_MODULE)
497
498static struct mtd_partition bfin_spi_flash_partitions[] = {
499 {
500 .name = "bootloader(spi)",
501 .size = 0x00040000,
502 .offset = 0,
503 .mask_flags = MTD_CAP_ROM
504 }, {
505 .name = "linux kernel(spi)",
506 .size = 0x1c0000,
507 .offset = 0x40000
508 }
509};
510
511static struct flash_platform_data bfin_spi_flash_data = {
512 .name = "m25p80",
513 .parts = bfin_spi_flash_partitions,
514 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
515 .type = "m25p16",
516};
517
518static struct bfin5xx_spi_chip spi_flash_chip_info = {
519 .enable_dma = 0,
520};
521#endif
522#endif
523
524#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
525#include <linux/spi/ad7879.h>
526static const struct ad7879_platform_data bfin_ad7879_ts_info = {
527 .model = 7879,
528 .x_plate_ohms = 620,
529 .pressure_max = 10000,
530 .pressure_min = 0,
531 .first_conversion_delay = 3,
532 .acquisition_time = 1,
533 .median = 2,
534 .averaging = 1,
535 .pen_down_acc_interval = 255,
536 .gpio_export = 1,
537 .gpio_base = -1,
538};
539#endif
540
541#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
542#include <asm/bfin-lq035q1.h>
543
544static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
545 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
546 .ppi_mode = USE_RGB565_16_BIT_PPI,
547 .use_bl = 0,
548 .gpio_bl = GPIO_PF7,
549};
550
551static struct resource bfin_lq035q1_resources[] = {
552 {
553 .start = IRQ_PPI_ERROR,
554 .end = IRQ_PPI_ERROR,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559static struct platform_device bfin_lq035q1_device = {
560 .name = "bfin-lq035q1",
561 .id = -1,
562 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
563 .resource = bfin_lq035q1_resources,
564 .dev = {
565 .platform_data = &bfin_lq035q1_data,
566 },
567};
568#endif
569
570static struct spi_board_info bf538_spi_board_info[] __initdata = {
571#if defined(CONFIG_MTD_M25P80) \
572 || defined(CONFIG_MTD_M25P80_MODULE)
573 {
574
575 .modalias = "m25p80",
576 .max_speed_hz = 25000000,
577 .bus_num = 0,
578 .chip_select = 1,
579 .platform_data = &bfin_spi_flash_data,
580 .controller_data = &spi_flash_chip_info,
581 .mode = SPI_MODE_3,
582 },
583#endif
584#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
585 {
586 .modalias = "ad7879",
587 .platform_data = &bfin_ad7879_ts_info,
588 .irq = IRQ_PF3,
589 .max_speed_hz = 5000000,
590 .bus_num = 0,
591 .chip_select = 1,
592 .mode = SPI_CPHA | SPI_CPOL,
593 },
594#endif
595#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
596 {
597 .modalias = "bfin-lq035q1-spi",
598 .max_speed_hz = 20000000,
599 .bus_num = 0,
600 .chip_select = 2,
601 .mode = SPI_CPHA | SPI_CPOL,
602 },
603#endif
604#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
605 {
606 .modalias = "spidev",
607 .max_speed_hz = 3125000,
608 .bus_num = 0,
609 .chip_select = 1,
610 },
611#endif
612};
613
614
615static struct resource bfin_spi0_resource[] = {
616 [0] = {
617 .start = SPI0_REGBASE,
618 .end = SPI0_REGBASE + 0xFF,
619 .flags = IORESOURCE_MEM,
620 },
621 [1] = {
622 .start = CH_SPI0,
623 .end = CH_SPI0,
624 .flags = IORESOURCE_DMA,
625 },
626 [2] = {
627 .start = IRQ_SPI0,
628 .end = IRQ_SPI0,
629 .flags = IORESOURCE_IRQ,
630 }
631};
632
633
634static struct resource bfin_spi1_resource[] = {
635 [0] = {
636 .start = SPI1_REGBASE,
637 .end = SPI1_REGBASE + 0xFF,
638 .flags = IORESOURCE_MEM,
639 },
640 [1] = {
641 .start = CH_SPI1,
642 .end = CH_SPI1,
643 .flags = IORESOURCE_DMA,
644 },
645 [2] = {
646 .start = IRQ_SPI1,
647 .end = IRQ_SPI1,
648 .flags = IORESOURCE_IRQ,
649 }
650};
651
652
653static struct resource bfin_spi2_resource[] = {
654 [0] = {
655 .start = SPI2_REGBASE,
656 .end = SPI2_REGBASE + 0xFF,
657 .flags = IORESOURCE_MEM,
658 },
659 [1] = {
660 .start = CH_SPI2,
661 .end = CH_SPI2,
662 .flags = IORESOURCE_DMA,
663 },
664 [2] = {
665 .start = IRQ_SPI2,
666 .end = IRQ_SPI2,
667 .flags = IORESOURCE_IRQ,
668 }
669};
670
671
672static struct bfin5xx_spi_master bf538_spi_master_info0 = {
673 .num_chipselect = 8,
674 .enable_dma = 1,
675 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
676};
677
678static struct platform_device bf538_spi_master0 = {
679 .name = "bfin-spi",
680 .id = 0,
681 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
682 .resource = bfin_spi0_resource,
683 .dev = {
684 .platform_data = &bf538_spi_master_info0,
685 },
686};
687
688static struct bfin5xx_spi_master bf538_spi_master_info1 = {
689 .num_chipselect = 2,
690 .enable_dma = 1,
691 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
692};
693
694static struct platform_device bf538_spi_master1 = {
695 .name = "bfin-spi",
696 .id = 1,
697 .num_resources = ARRAY_SIZE(bfin_spi1_resource),
698 .resource = bfin_spi1_resource,
699 .dev = {
700 .platform_data = &bf538_spi_master_info1,
701 },
702};
703
704static struct bfin5xx_spi_master bf538_spi_master_info2 = {
705 .num_chipselect = 2,
706 .enable_dma = 1,
707 .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
708};
709
710static struct platform_device bf538_spi_master2 = {
711 .name = "bfin-spi",
712 .id = 2,
713 .num_resources = ARRAY_SIZE(bfin_spi2_resource),
714 .resource = bfin_spi2_resource,
715 .dev = {
716 .platform_data = &bf538_spi_master_info2,
717 },
718};
719
720#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
721static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
722
723static struct resource bfin_twi0_resource[] = {
724 [0] = {
725 .start = TWI0_REGBASE,
726 .end = TWI0_REGBASE + 0xFF,
727 .flags = IORESOURCE_MEM,
728 },
729 [1] = {
730 .start = IRQ_TWI0,
731 .end = IRQ_TWI0,
732 .flags = IORESOURCE_IRQ,
733 },
734};
735
736static struct platform_device i2c_bfin_twi0_device = {
737 .name = "i2c-bfin-twi",
738 .id = 0,
739 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
740 .resource = bfin_twi0_resource,
741 .dev = {
742 .platform_data = &bfin_twi0_pins,
743 },
744};
745
746static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0};
747
748static struct resource bfin_twi1_resource[] = {
749 [0] = {
750 .start = TWI1_REGBASE,
751 .end = TWI1_REGBASE + 0xFF,
752 .flags = IORESOURCE_MEM,
753 },
754 [1] = {
755 .start = IRQ_TWI1,
756 .end = IRQ_TWI1,
757 .flags = IORESOURCE_IRQ,
758 },
759};
760
761static struct platform_device i2c_bfin_twi1_device = {
762 .name = "i2c-bfin-twi",
763 .id = 1,
764 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
765 .resource = bfin_twi1_resource,
766};
767#endif
768#endif
769
770#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
771#include <linux/gpio_keys.h>
772
773static struct gpio_keys_button bfin_gpio_keys_table[] = {
774 {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
775};
776
777static struct gpio_keys_platform_data bfin_gpio_keys_data = {
778 .buttons = bfin_gpio_keys_table,
779 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
780};
781
782static struct platform_device bfin_device_gpiokeys = {
783 .name = "gpio-keys",
784 .dev = {
785 .platform_data = &bfin_gpio_keys_data,
786 },
787};
788#endif
789
790static const unsigned int cclk_vlev_datasheet[] =
791{
792
793
794
795
796 VRPAIR(VLEV_100, 150000000),
797 VRPAIR(VLEV_100, 250000000),
798 VRPAIR(VLEV_110, 276000000),
799 VRPAIR(VLEV_115, 301000000),
800 VRPAIR(VLEV_120, 525000000),
801 VRPAIR(VLEV_125, 550000000),
802 VRPAIR(VLEV_130, 600000000),
803};
804
805static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
806 .tuple_tab = cclk_vlev_datasheet,
807 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
808 .vr_settling_time = 25 ,
809};
810
811static struct platform_device bfin_dpmc = {
812 .name = "bfin dpmc",
813 .dev = {
814 .platform_data = &bfin_dmpc_vreg_data,
815 },
816};
817
818#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
819static struct mtd_partition ezkit_partitions[] = {
820 {
821 .name = "bootloader(nor)",
822 .size = 0x40000,
823 .offset = 0,
824 }, {
825 .name = "linux kernel(nor)",
826 .size = 0x180000,
827 .offset = MTDPART_OFS_APPEND,
828 }, {
829 .name = "file system(nor)",
830 .size = MTDPART_SIZ_FULL,
831 .offset = MTDPART_OFS_APPEND,
832 }
833};
834
835static struct physmap_flash_data ezkit_flash_data = {
836 .width = 2,
837 .parts = ezkit_partitions,
838 .nr_parts = ARRAY_SIZE(ezkit_partitions),
839};
840
841static struct resource ezkit_flash_resource = {
842 .start = 0x20000000,
843#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
844 .end = 0x202fffff,
845#else
846 .end = 0x203fffff,
847#endif
848 .flags = IORESOURCE_MEM,
849};
850
851static struct platform_device ezkit_flash_device = {
852 .name = "physmap-flash",
853 .id = 0,
854 .dev = {
855 .platform_data = &ezkit_flash_data,
856 },
857 .num_resources = 1,
858 .resource = &ezkit_flash_resource,
859};
860#endif
861
862static struct platform_device *cm_bf538_devices[] __initdata = {
863
864 &bfin_dpmc,
865
866#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
867 &rtc_device,
868#endif
869
870#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
871#ifdef CONFIG_SERIAL_BFIN_UART0
872 &bfin_uart0_device,
873#endif
874#ifdef CONFIG_SERIAL_BFIN_UART1
875 &bfin_uart1_device,
876#endif
877#ifdef CONFIG_SERIAL_BFIN_UART2
878 &bfin_uart2_device,
879#endif
880#endif
881
882#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
883 &bf538_spi_master0,
884 &bf538_spi_master1,
885 &bf538_spi_master2,
886#endif
887
888#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
889 &i2c_bfin_twi0_device,
890 &i2c_bfin_twi1_device,
891#endif
892
893#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
894#ifdef CONFIG_BFIN_SIR0
895 &bfin_sir0_device,
896#endif
897#ifdef CONFIG_BFIN_SIR1
898 &bfin_sir1_device,
899#endif
900#ifdef CONFIG_BFIN_SIR2
901 &bfin_sir2_device,
902#endif
903#endif
904
905#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
906#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
907 &bfin_sport0_uart_device,
908#endif
909#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
910 &bfin_sport1_uart_device,
911#endif
912#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
913 &bfin_sport2_uart_device,
914#endif
915#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
916 &bfin_sport3_uart_device,
917#endif
918#endif
919
920#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
921 &bfin_can_device,
922#endif
923
924#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
925 &smc91x_device,
926#endif
927
928#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
929 &bfin_lq035q1_device,
930#endif
931
932#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
933 &bfin_device_gpiokeys,
934#endif
935
936#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
937 &ezkit_flash_device,
938#endif
939};
940
941static int __init ezkit_init(void)
942{
943 printk(KERN_INFO "%s(): registering device resources\n", __func__);
944 platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
945
946#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
947 spi_register_board_info(bf538_spi_board_info,
948 ARRAY_SIZE(bf538_spi_board_info));
949#endif
950
951 return 0;
952}
953
954arch_initcall(ezkit_init);
955
956static struct platform_device *ezkit_early_devices[] __initdata = {
957#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
958#ifdef CONFIG_SERIAL_BFIN_UART0
959 &bfin_uart0_device,
960#endif
961#ifdef CONFIG_SERIAL_BFIN_UART1
962 &bfin_uart1_device,
963#endif
964#ifdef CONFIG_SERIAL_BFIN_UART2
965 &bfin_uart2_device,
966#endif
967#endif
968
969#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
970#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
971 &bfin_sport0_uart_device,
972#endif
973#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
974 &bfin_sport1_uart_device,
975#endif
976#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
977 &bfin_sport2_uart_device,
978#endif
979#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
980 &bfin_sport3_uart_device,
981#endif
982#endif
983};
984
985void __init native_machine_early_platform_add_devices(void)
986{
987 printk(KERN_INFO "register early platform devices\n");
988 early_platform_add_devices(ezkit_early_devices,
989 ARRAY_SIZE(ezkit_early_devices));
990}
991
