1#ifndef __iop_sap_out_defs_h
2#define __iop_sap_out_defs_h
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17#ifndef REG_RD
18#define REG_RD( scope, inst, reg ) \
19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
21#endif
22
23#ifndef REG_WR
24#define REG_WR( scope, inst, reg, val ) \
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27#endif
28
29#ifndef REG_RD_VECT
30#define REG_RD_VECT( scope, inst, reg, index ) \
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
34#endif
35
36#ifndef REG_WR_VECT
37#define REG_WR_VECT( scope, inst, reg, index, val ) \
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
41#endif
42
43#ifndef REG_RD_INT
44#define REG_RD_INT( scope, inst, reg ) \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46#endif
47
48#ifndef REG_WR_INT
49#define REG_WR_INT( scope, inst, reg, val ) \
50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51#endif
52
53#ifndef REG_RD_INT_VECT
54#define REG_RD_INT_VECT( scope, inst, reg, index ) \
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56 (index) * STRIDE_##scope##_##reg )
57#endif
58
59#ifndef REG_WR_INT_VECT
60#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62 (index) * STRIDE_##scope##_##reg, (val) )
63#endif
64
65#ifndef REG_TYPE_CONV
66#define REG_TYPE_CONV( type, orgtype, val ) \
67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68#endif
69
70#ifndef reg_page_size
71#define reg_page_size 8192
72#endif
73
74#ifndef REG_ADDR
75#define REG_ADDR( scope, inst, reg ) \
76 ( (inst) + REG_RD_ADDR_##scope##_##reg )
77#endif
78
79#ifndef REG_ADDR_VECT
80#define REG_ADDR_VECT( scope, inst, reg, index ) \
81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82 (index) * STRIDE_##scope##_##reg )
83#endif
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86
87
88typedef struct {
89 unsigned int clk0_src : 2;
90 unsigned int clk0_gate_src : 2;
91 unsigned int clk0_force_src : 3;
92 unsigned int clk1_src : 2;
93 unsigned int clk1_gate_src : 2;
94 unsigned int clk1_force_src : 3;
95 unsigned int clk2_src : 2;
96 unsigned int clk2_gate_src : 2;
97 unsigned int clk2_force_src : 3;
98 unsigned int clk3_src : 2;
99 unsigned int clk3_gate_src : 2;
100 unsigned int clk3_force_src : 3;
101 unsigned int dummy1 : 4;
102} reg_iop_sap_out_rw_gen_gated;
103#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
104#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
105
106
107typedef struct {
108 unsigned int byte0_clk_sel : 3;
109 unsigned int byte0_gated_clk : 2;
110 unsigned int byte0_clk_inv : 1;
111 unsigned int byte1_clk_sel : 3;
112 unsigned int byte1_gated_clk : 2;
113 unsigned int byte1_clk_inv : 1;
114 unsigned int byte2_clk_sel : 3;
115 unsigned int byte2_gated_clk : 2;
116 unsigned int byte2_clk_inv : 1;
117 unsigned int byte3_clk_sel : 3;
118 unsigned int byte3_gated_clk : 2;
119 unsigned int byte3_clk_inv : 1;
120 unsigned int dummy1 : 8;
121} reg_iop_sap_out_rw_bus0;
122#define REG_RD_ADDR_iop_sap_out_rw_bus0 4
123#define REG_WR_ADDR_iop_sap_out_rw_bus0 4
124
125
126typedef struct {
127 unsigned int byte0_clk_sel : 3;
128 unsigned int byte0_gated_clk : 2;
129 unsigned int byte0_clk_inv : 1;
130 unsigned int byte1_clk_sel : 3;
131 unsigned int byte1_gated_clk : 2;
132 unsigned int byte1_clk_inv : 1;
133 unsigned int byte2_clk_sel : 3;
134 unsigned int byte2_gated_clk : 2;
135 unsigned int byte2_clk_inv : 1;
136 unsigned int byte3_clk_sel : 3;
137 unsigned int byte3_gated_clk : 2;
138 unsigned int byte3_clk_inv : 1;
139 unsigned int dummy1 : 8;
140} reg_iop_sap_out_rw_bus1;
141#define REG_RD_ADDR_iop_sap_out_rw_bus1 8
142#define REG_WR_ADDR_iop_sap_out_rw_bus1 8
143
144
145typedef struct {
146 unsigned int byte0_clk_sel : 3;
147 unsigned int byte0_clk_ext : 3;
148 unsigned int byte0_gated_clk : 2;
149 unsigned int byte0_clk_inv : 1;
150 unsigned int byte0_logic : 2;
151 unsigned int byte1_clk_sel : 3;
152 unsigned int byte1_clk_ext : 3;
153 unsigned int byte1_gated_clk : 2;
154 unsigned int byte1_clk_inv : 1;
155 unsigned int byte1_logic : 2;
156 unsigned int dummy1 : 10;
157} reg_iop_sap_out_rw_bus0_lo_oe;
158#define REG_RD_ADDR_iop_sap_out_rw_bus0_lo_oe 12
159#define REG_WR_ADDR_iop_sap_out_rw_bus0_lo_oe 12
160
161
162typedef struct {
163 unsigned int byte2_clk_sel : 3;
164 unsigned int byte2_clk_ext : 3;
165 unsigned int byte2_gated_clk : 2;
166 unsigned int byte2_clk_inv : 1;
167 unsigned int byte2_logic : 2;
168 unsigned int byte3_clk_sel : 3;
169 unsigned int byte3_clk_ext : 3;
170 unsigned int byte3_gated_clk : 2;
171 unsigned int byte3_clk_inv : 1;
172 unsigned int byte3_logic : 2;
173 unsigned int dummy1 : 10;
174} reg_iop_sap_out_rw_bus0_hi_oe;
175#define REG_RD_ADDR_iop_sap_out_rw_bus0_hi_oe 16
176#define REG_WR_ADDR_iop_sap_out_rw_bus0_hi_oe 16
177
178
179typedef struct {
180 unsigned int byte0_clk_sel : 3;
181 unsigned int byte0_clk_ext : 3;
182 unsigned int byte0_gated_clk : 2;
183 unsigned int byte0_clk_inv : 1;
184 unsigned int byte0_logic : 2;
185 unsigned int byte1_clk_sel : 3;
186 unsigned int byte1_clk_ext : 3;
187 unsigned int byte1_gated_clk : 2;
188 unsigned int byte1_clk_inv : 1;
189 unsigned int byte1_logic : 2;
190 unsigned int dummy1 : 10;
191} reg_iop_sap_out_rw_bus1_lo_oe;
192#define REG_RD_ADDR_iop_sap_out_rw_bus1_lo_oe 20
193#define REG_WR_ADDR_iop_sap_out_rw_bus1_lo_oe 20
194
195
196typedef struct {
197 unsigned int byte2_clk_sel : 3;
198 unsigned int byte2_clk_ext : 3;
199 unsigned int byte2_gated_clk : 2;
200 unsigned int byte2_clk_inv : 1;
201 unsigned int byte2_logic : 2;
202 unsigned int byte3_clk_sel : 3;
203 unsigned int byte3_clk_ext : 3;
204 unsigned int byte3_gated_clk : 2;
205 unsigned int byte3_clk_inv : 1;
206 unsigned int byte3_logic : 2;
207 unsigned int dummy1 : 10;
208} reg_iop_sap_out_rw_bus1_hi_oe;
209#define REG_RD_ADDR_iop_sap_out_rw_bus1_hi_oe 24
210#define REG_WR_ADDR_iop_sap_out_rw_bus1_hi_oe 24
211
212#define STRIDE_iop_sap_out_rw_gio 4
213
214typedef struct {
215 unsigned int out_clk_sel : 3;
216 unsigned int out_clk_ext : 4;
217 unsigned int out_gated_clk : 2;
218 unsigned int out_clk_inv : 1;
219 unsigned int out_logic : 1;
220 unsigned int oe_clk_sel : 3;
221 unsigned int oe_clk_ext : 3;
222 unsigned int oe_gated_clk : 2;
223 unsigned int oe_clk_inv : 1;
224 unsigned int oe_logic : 2;
225 unsigned int dummy1 : 10;
226} reg_iop_sap_out_rw_gio;
227#define REG_RD_ADDR_iop_sap_out_rw_gio 28
228#define REG_WR_ADDR_iop_sap_out_rw_gio 28
229
230
231
232enum {
233 regk_iop_sap_out_and = 0x00000002,
234 regk_iop_sap_out_clk0 = 0x00000000,
235 regk_iop_sap_out_clk1 = 0x00000001,
236 regk_iop_sap_out_clk12 = 0x00000002,
237 regk_iop_sap_out_clk2 = 0x00000002,
238 regk_iop_sap_out_clk200 = 0x00000001,
239 regk_iop_sap_out_clk3 = 0x00000003,
240 regk_iop_sap_out_ext = 0x00000003,
241 regk_iop_sap_out_gated = 0x00000004,
242 regk_iop_sap_out_gio1 = 0x00000000,
243 regk_iop_sap_out_gio13 = 0x00000002,
244 regk_iop_sap_out_gio13_clk = 0x0000000c,
245 regk_iop_sap_out_gio15 = 0x00000001,
246 regk_iop_sap_out_gio18 = 0x00000003,
247 regk_iop_sap_out_gio18_clk = 0x0000000d,
248 regk_iop_sap_out_gio1_clk = 0x00000008,
249 regk_iop_sap_out_gio21_clk = 0x0000000e,
250 regk_iop_sap_out_gio23 = 0x00000002,
251 regk_iop_sap_out_gio29_clk = 0x0000000f,
252 regk_iop_sap_out_gio31 = 0x00000003,
253 regk_iop_sap_out_gio5 = 0x00000001,
254 regk_iop_sap_out_gio5_clk = 0x00000009,
255 regk_iop_sap_out_gio6_clk = 0x0000000a,
256 regk_iop_sap_out_gio7 = 0x00000000,
257 regk_iop_sap_out_gio7_clk = 0x0000000b,
258 regk_iop_sap_out_gio_in13 = 0x00000001,
259 regk_iop_sap_out_gio_in21 = 0x00000002,
260 regk_iop_sap_out_gio_in29 = 0x00000003,
261 regk_iop_sap_out_gio_in5 = 0x00000000,
262 regk_iop_sap_out_inv = 0x00000001,
263 regk_iop_sap_out_nand = 0x00000003,
264 regk_iop_sap_out_no = 0x00000000,
265 regk_iop_sap_out_none = 0x00000000,
266 regk_iop_sap_out_rw_bus0_default = 0x00000000,
267 regk_iop_sap_out_rw_bus0_hi_oe_default = 0x00000000,
268 regk_iop_sap_out_rw_bus0_lo_oe_default = 0x00000000,
269 regk_iop_sap_out_rw_bus1_default = 0x00000000,
270 regk_iop_sap_out_rw_bus1_hi_oe_default = 0x00000000,
271 regk_iop_sap_out_rw_bus1_lo_oe_default = 0x00000000,
272 regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
273 regk_iop_sap_out_rw_gio_default = 0x00000000,
274 regk_iop_sap_out_rw_gio_size = 0x00000020,
275 regk_iop_sap_out_spu0_gio0 = 0x00000002,
276 regk_iop_sap_out_spu0_gio1 = 0x00000003,
277 regk_iop_sap_out_spu0_gio12 = 0x00000004,
278 regk_iop_sap_out_spu0_gio13 = 0x00000004,
279 regk_iop_sap_out_spu0_gio14 = 0x00000004,
280 regk_iop_sap_out_spu0_gio15 = 0x00000004,
281 regk_iop_sap_out_spu0_gio2 = 0x00000002,
282 regk_iop_sap_out_spu0_gio3 = 0x00000003,
283 regk_iop_sap_out_spu0_gio4 = 0x00000002,
284 regk_iop_sap_out_spu0_gio5 = 0x00000003,
285 regk_iop_sap_out_spu0_gio6 = 0x00000002,
286 regk_iop_sap_out_spu0_gio7 = 0x00000003,
287 regk_iop_sap_out_spu1_gio0 = 0x00000005,
288 regk_iop_sap_out_spu1_gio1 = 0x00000006,
289 regk_iop_sap_out_spu1_gio12 = 0x00000007,
290 regk_iop_sap_out_spu1_gio13 = 0x00000007,
291 regk_iop_sap_out_spu1_gio14 = 0x00000007,
292 regk_iop_sap_out_spu1_gio15 = 0x00000007,
293 regk_iop_sap_out_spu1_gio2 = 0x00000005,
294 regk_iop_sap_out_spu1_gio3 = 0x00000006,
295 regk_iop_sap_out_spu1_gio4 = 0x00000005,
296 regk_iop_sap_out_spu1_gio5 = 0x00000006,
297 regk_iop_sap_out_spu1_gio6 = 0x00000005,
298 regk_iop_sap_out_spu1_gio7 = 0x00000006,
299 regk_iop_sap_out_timer_grp0_tmr2 = 0x00000004,
300 regk_iop_sap_out_timer_grp1_tmr2 = 0x00000005,
301 regk_iop_sap_out_timer_grp2_tmr2 = 0x00000006,
302 regk_iop_sap_out_timer_grp3_tmr2 = 0x00000007,
303 regk_iop_sap_out_tmr = 0x00000005,
304 regk_iop_sap_out_yes = 0x00000001
305};
306#endif
307
