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14#include <linux/sys.h>
15#include <linux/linkage.h>
16#include <asm/page.h>
17#include <asm/smp.h>
18#include <asm/cpu-regs.h>
19#include <asm/frame.inc>
20#include <asm/timer-regs.h>
21#include <proc/cache.h>
22#include <unit/timex.h>
23#include "mn10300-serial.h"
24
25#define SCxCTR 0x00
26#define SCxICR 0x04
27#define SCxTXB 0x08
28#define SCxRXB 0x09
29#define SCxSTR 0x0c
30#define SCxTIM 0x0d
31
32 .text
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39
40 .balign L1_CACHE_BYTES
41ENTRY(mn10300_serial_vdma_interrupt)
42
43
44 movm [d2,d3,a2,a3,exreg0],(sp)
45
46 movhu (IAGR),a2
47
48 and IAGR_GN,a2
49 add a2,a2
50 add mn10300_serial_int_tbl,a2
51
52 mov (a2+),a3
53 mov (__iobase,a3),e2
54 mov (a2),a2
55 jmp (a2)
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67
68ENTRY(mn10300_serial_vdma_rx_handler)
69 mov (__rx_icr,a3),e3
70 mov GxICR_DETECT,d2
71 movbu d2,(e3)
72 movhu (e3),d2
73
74 mov (__rx_inp,a3),d3
75 mov d3,a2
76 add 2,d3
77 and MNSC_BUFFER_SIZE-1,d3
78 mov (__rx_outp,a3),d2
79 cmp d3,d2
80 beq mnsc_vdma_rx_overflow
81
82 mov (__rx_buffer,a3),d2
83 add d2,a2
84 movhu (SCxSTR,e2),d2
85 movbu d2,(1,a2)
86 movbu (SCxRXB,e2),d2
87 movbu d2,(a2)
88 mov d3,(__rx_inp,a3)
89 bset MNSCx_RX_AVAIL,(__intr_flags,a3)
90
91mnsc_vdma_rx_done:
92 mov (__tm_icr,a3),a2
93 mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2
94 movhu d2,(a2)
95 movhu (a2),d2
96
97 movm (sp),[d2,d3,a2,a3,exreg0]
98 rti
99
100mnsc_vdma_rx_overflow:
101 bset MNSCx_RX_OVERF,(__intr_flags,a3)
102 bra mnsc_vdma_rx_done
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113
114 .balign L1_CACHE_BYTES
115ENTRY(mn10300_serial_vdma_tx_handler)
116 mov (__tx_icr,a3),e3
117 mov GxICR_DETECT,d2
118 movbu d2,(e3)
119 movhu (e3),d2
120
121 btst 0x01,(__tx_break,a3)
122 bne mnsc_vdma_tx_break
123
124 movbu (SCxSTR,e2),d2
125
126 btst SC01STR_TBF,d2
127 bne mnsc_vdma_tx_noint
128
129 movbu (__tx_xchar,a3),d2
130 or d2,d2
131 bne mnsc_vdma_tx_xchar
132
133 mov (__uart_state,a3),a2
134 mov (__xmit_tail,a2),d3
135 mov (__xmit_head,a2),d2
136 cmp d3,d2
137 beq mnsc_vdma_tx_empty
138
139 mov (__xmit_buffer,a2),d2
140
141 movbu (d3,d2),d2
142 movbu d2,(SCxTXB,e2)
143
144 inc d3
145 and __UART_XMIT_SIZE-1,d3
146 mov (__xmit_head,a2),d2
147 mov d3,(__xmit_tail,a2)
148
149 sub d3,d2
150 beq mnsc_vdma_tx_empty
151
152 and __UART_XMIT_SIZE-1,d2
153 cmp __UART_XMIT_SIZE-2,d2
154 beq mnsc_vdma_tx_made_hole
155
156mnsc_vdma_tx_done:
157 mov (__tm_icr,a3),a2
158 mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2
159 movhu d2,(a2)
160 movhu (a2),d2
161
162mnsc_vdma_tx_noint:
163 movm (sp),[d2,d3,a2,a3,exreg0]
164 rti
165
166mnsc_vdma_tx_empty:
167 mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2
168 movhu d2,(e3)
169 movhu (e3),d2
170
171 bset MNSCx_TX_EMPTY,(__intr_flags,a3)
172 bra mnsc_vdma_tx_done
173
174mnsc_vdma_tx_break:
175 movhu (SCxCTR,e2),d2
176 or SC01CTR_BKE,d2
177 movhu d2,(SCxCTR,e2)
178 mov +(NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL)|GxICR_DETECT),d2
179 movhu d2,(e3)
180
181 movhu (e3),d2
182 bra mnsc_vdma_tx_noint
183
184mnsc_vdma_tx_xchar:
185 bclr 0xff,(__tx_xchar,a3)
186 movbu d2,(SCxTXB,e2)
187 bra mnsc_vdma_tx_done
188
189mnsc_vdma_tx_made_hole:
190 bset MNSCx_TX_SPACE,(__intr_flags,a3)
191 bra mnsc_vdma_tx_done
192