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11#ifndef _ASM_X86_UV_UV_BAU_H
12#define _ASM_X86_UV_UV_BAU_H
13
14#include <linux/bitmap.h>
15#define BITSPERBYTE 8
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35
36#define MAX_CPUS_PER_UVHUB 64
37#define MAX_CPUS_PER_SOCKET 32
38#define ADP_SZ 64
39#define UV_CPUS_PER_AS 32
40#define ITEMS_PER_DESC 8
41
42#define MAX_BAU_CONCURRENT 3
43#define UV_ACT_STATUS_MASK 0x3
44#define UV_ACT_STATUS_SIZE 2
45#define UV_DISTRIBUTION_SIZE 256
46#define UV_SW_ACK_NPENDING 8
47#define UV1_NET_ENDPOINT_INTD 0x38
48#define UV2_NET_ENDPOINT_INTD 0x28
49#define UV_NET_ENDPOINT_INTD (is_uv1_hub() ? \
50 UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
51#define UV_DESC_PSHIFT 49
52#define UV_PAYLOADQ_PNODE_SHIFT 49
53#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
54#define UV_BAU_BASENAME "sgi_uv/bau_tunables"
55#define UV_BAU_TUNABLES_DIR "sgi_uv"
56#define UV_BAU_TUNABLES_FILE "bau_tunables"
57#define WHITESPACE " \t\n"
58#define uv_mmask ((1UL << uv_hub_info->m_val) - 1)
59#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
60#define cpubit_isset(cpu, bau_local_cpumask) \
61 test_bit((cpu), (bau_local_cpumask).bits)
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69
70#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
71#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (15UL)
72
73#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ? \
74 UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD : \
75 UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
76
77#define BAU_MISC_CONTROL_MULT_MASK 3
78
79#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
80
81#define BAU_URGENCY_7_SHIFT 28
82#define BAU_URGENCY_7_MASK 7
83
84#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
85
86#define BAU_TRANS_SHIFT 40
87#define BAU_TRANS_MASK 0x3f
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91
92#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
93#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
94#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
95#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
96#define write_gmmr uv_write_global_mmr64
97#define write_lmmr uv_write_local_mmr
98#define read_lmmr uv_read_local_mmr
99#define read_gmmr uv_read_global_mmr64
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103
104#define DS_IDLE 0
105#define DS_ACTIVE 1
106#define DS_DESTINATION_TIMEOUT 2
107#define DS_SOURCE_TIMEOUT 3
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119
120#define UV2H_DESC_IDLE 0
121#define UV2H_DESC_BUSY 2
122#define UV2H_DESC_DEST_TIMEOUT 4
123#define UV2H_DESC_DEST_STRONG_NACK 5
124#define UV2H_DESC_SOURCE_TIMEOUT 6
125#define UV2H_DESC_DEST_PUT_ERR 7
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129
130#define PLUGGED_DELAY 10
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136#define PLUGSB4RESET 100
137
138#define TIMEOUTSB4RESET 1
139
140#define IPI_RESET_LIMIT 1
141
142#define COMPLETE_THRESHOLD 5
143
144#define UV_LB_SUBNODEID 0x10
145
146
147#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
148#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
149
150#define UV2_ACK_MASK 0x7UL
151#define UV2_ACK_UNITS_SHFT 3
152#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
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156
157#define DEST_Q_SIZE 20
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161#define DEST_NUM_RESOURCES 8
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165#define FLUSH_RETRY_PLUGGED 1
166#define FLUSH_RETRY_TIMEOUT 2
167#define FLUSH_GIVEUP 3
168#define FLUSH_COMPLETE 4
169#define FLUSH_RETRY_BUSYBUG 5
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173
174#define CONGESTED_RESPONSE_US 1000
175
176#define CONGESTED_REPS 10
177
178#define CONGESTED_PERIOD 30
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180
181#define MSG_NOOP 0
182#define MSG_REGULAR 1
183#define MSG_RETRY 2
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194
195struct pnmask {
196 unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
197};
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204struct bau_local_cpumask {
205 unsigned long bits;
206};
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225struct bau_msg_payload {
226 unsigned long address;
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229 unsigned short sending_cpu;
230
231 unsigned short acknowledge_count;
232
233 unsigned int reserved1:32;
234};
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240
241struct uv1_bau_msg_header {
242 unsigned int dest_subnodeid:6;
243
244 unsigned int base_dest_nasid:15;
245
246 unsigned int command:8;
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249 unsigned int rsvd_1:3;
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252 unsigned int rsvd_2:9;
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255 unsigned int sequence:16;
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262 unsigned int rsvd_3:1;
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267 unsigned int replied_to:1;
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270 unsigned int msg_type:3;
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273 unsigned int canceled:1;
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276 unsigned int payload_1a:1;
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278 unsigned int payload_1b:2;
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282 unsigned int payload_1ca:6;
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284 unsigned int payload_1c:2;
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288 unsigned int payload_1d:6;
289
290 unsigned int payload_1e:2;
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293 unsigned int rsvd_4:7;
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295 unsigned int swack_flag:1;
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300 unsigned int rsvd_5:6;
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302 unsigned int rsvd_6:5;
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304 unsigned int int_both:1;
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307 unsigned int fairness:3;
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309 unsigned int multilevel:1;
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313 unsigned int chaining:1;
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316 unsigned int rsvd_7:21;
317
318};
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324struct uv2_bau_msg_header {
325 unsigned int base_dest_nasid:15;
326
327 unsigned int dest_subnodeid:5;
328
329 unsigned int rsvd_1:1;
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335 unsigned int replied_to:1;
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338 unsigned int msg_type:3;
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341 unsigned int canceled:1;
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344 unsigned int payload_1:3;
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348 unsigned int payload_2a:3;
349 unsigned int payload_2b:5;
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353 unsigned int payload_3:8;
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356 unsigned int rsvd_2:7;
357
358 unsigned int swack_flag:1;
359
360 unsigned int rsvd_3a:3;
361 unsigned int rsvd_3b:8;
362 unsigned int rsvd_3c:8;
363 unsigned int rsvd_3d:3;
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365 unsigned int fairness:3;
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368 unsigned int sequence:16;
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370 unsigned int chaining:1;
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373 unsigned int multilevel:1;
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376 unsigned int rsvd_4:24;
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380 unsigned int command:8;
381
382};
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389struct bau_desc {
390 struct pnmask distribution;
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394 union bau_msg_header {
395 struct uv1_bau_msg_header uv1_hdr;
396 struct uv2_bau_msg_header uv2_hdr;
397 } header;
398
399 struct bau_msg_payload payload;
400};
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433struct bau_pq_entry {
434 unsigned long address;
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436
437 unsigned short sending_cpu;
438
439 unsigned short acknowledge_count;
440
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442 unsigned short replied_to:1;
443 unsigned short msg_type:3;
444 unsigned short canceled:1;
445 unsigned short unused1:3;
446
447 unsigned char unused2a;
448
449 unsigned char unused2;
450
451 unsigned char swack_vec;
452
453 unsigned short sequence;
454
455 unsigned char unused4[2];
456
457 int number_of_cpus;
458
459 unsigned char unused5[8];
460
461};
462
463struct msg_desc {
464 struct bau_pq_entry *msg;
465 int msg_slot;
466 struct bau_pq_entry *queue_first;
467 struct bau_pq_entry *queue_last;
468};
469
470struct reset_args {
471 int sender;
472};
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477struct ptc_stats {
478
479 unsigned long s_giveup;
480
481 unsigned long s_requestor;
482
483 unsigned long s_stimeout;
484 unsigned long s_dtimeout;
485 unsigned long s_strongnacks;
486 unsigned long s_time;
487 unsigned long s_retriesok;
488 unsigned long s_ntargcpu;
489
490 unsigned long s_ntargself;
491
492 unsigned long s_ntarglocals;
493
494 unsigned long s_ntargremotes;
495
496 unsigned long s_ntarglocaluvhub;
497 unsigned long s_ntargremoteuvhub;
498 unsigned long s_ntarguvhub;
499
500 unsigned long s_ntarguvhub16;
501
502 unsigned long s_ntarguvhub8;
503
504 unsigned long s_ntarguvhub4;
505
506 unsigned long s_ntarguvhub2;
507
508 unsigned long s_ntarguvhub1;
509
510 unsigned long s_resets_plug;
511
512 unsigned long s_resets_timeout;
513
514 unsigned long s_busy;
515
516 unsigned long s_throttles;
517 unsigned long s_retry_messages;
518 unsigned long s_bau_reenabled;
519 unsigned long s_bau_disabled;
520 unsigned long s_uv2_wars;
521 unsigned long s_uv2_wars_hw;
522 unsigned long s_uv2_war_waits;
523
524 unsigned long d_alltlb;
525
526 unsigned long d_onetlb;
527
528 unsigned long d_multmsg;
529
530 unsigned long d_nomsg;
531 unsigned long d_time;
532
533 unsigned long d_requestee;
534
535 unsigned long d_retries;
536
537 unsigned long d_canceled;
538
539 unsigned long d_nocanceled;
540
541 unsigned long d_resets;
542
543 unsigned long d_rcanceled;
544
545};
546
547struct tunables {
548 int *tunp;
549 int deflt;
550};
551
552struct hub_and_pnode {
553 short uvhub;
554 short pnode;
555};
556
557struct socket_desc {
558 short num_cpus;
559 short cpu_number[MAX_CPUS_PER_SOCKET];
560};
561
562struct uvhub_desc {
563 unsigned short socket_mask;
564 short num_cpus;
565 short uvhub;
566 short pnode;
567 struct socket_desc socket[2];
568};
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573struct bau_control {
574 struct bau_desc *descriptor_base;
575 struct bau_pq_entry *queue_first;
576 struct bau_pq_entry *queue_last;
577 struct bau_pq_entry *bau_msg_head;
578 struct bau_control *uvhub_master;
579 struct bau_control *socket_master;
580 struct ptc_stats *statp;
581 cpumask_t *cpumask;
582 unsigned long timeout_interval;
583 unsigned long set_bau_on_time;
584 atomic_t active_descriptor_count;
585 int plugged_tries;
586 int timeout_tries;
587 int ipi_attempts;
588 int conseccompletes;
589 int baudisabled;
590 int set_bau_off;
591 short cpu;
592 short osnode;
593 short uvhub_cpu;
594 short uvhub;
595 short uvhub_version;
596 short cpus_in_socket;
597 short cpus_in_uvhub;
598 short partition_base_pnode;
599 short using_desc;
600 unsigned int inuse_map;
601 unsigned short message_number;
602 unsigned short uvhub_quiesce;
603 short socket_acknowledge_count[DEST_Q_SIZE];
604 cycles_t send_message;
605 spinlock_t uvhub_lock;
606 spinlock_t queue_lock;
607
608 int max_concurr;
609 int max_concurr_const;
610 int plugged_delay;
611 int plugsb4reset;
612 int timeoutsb4reset;
613 int ipi_reset_limit;
614 int complete_threshold;
615 int cong_response_us;
616 int cong_reps;
617 int cong_period;
618 unsigned long clocks_per_100_usec;
619 cycles_t period_time;
620 long period_requests;
621 struct hub_and_pnode *thp;
622};
623
624static inline unsigned long read_mmr_uv2_status(void)
625{
626 return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
627}
628
629static inline void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
630{
631 write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
632}
633
634static inline void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
635{
636 write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
637}
638
639static inline void write_mmr_activation(unsigned long index)
640{
641 write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
642}
643
644static inline void write_gmmr_activation(int pnode, unsigned long mmr_image)
645{
646 write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
647}
648
649static inline void write_mmr_payload_first(int pnode, unsigned long mmr_image)
650{
651 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
652}
653
654static inline void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
655{
656 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
657}
658
659static inline void write_mmr_payload_last(int pnode, unsigned long mmr_image)
660{
661 write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
662}
663
664static inline void write_mmr_misc_control(int pnode, unsigned long mmr_image)
665{
666 write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
667}
668
669static inline unsigned long read_mmr_misc_control(int pnode)
670{
671 return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
672}
673
674static inline void write_mmr_sw_ack(unsigned long mr)
675{
676 uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
677}
678
679static inline void write_gmmr_sw_ack(int pnode, unsigned long mr)
680{
681 write_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
682}
683
684static inline unsigned long read_mmr_sw_ack(void)
685{
686 return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
687}
688
689static inline unsigned long read_gmmr_sw_ack(int pnode)
690{
691 return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
692}
693
694static inline void write_mmr_data_config(int pnode, unsigned long mr)
695{
696 uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
697}
698
699static inline int bau_uvhub_isset(int uvhub, struct pnmask *dstp)
700{
701 return constant_test_bit(uvhub, &dstp->bits[0]);
702}
703static inline void bau_uvhub_set(int pnode, struct pnmask *dstp)
704{
705 __set_bit(pnode, &dstp->bits[0]);
706}
707static inline void bau_uvhubs_clear(struct pnmask *dstp,
708 int nbits)
709{
710 bitmap_zero(&dstp->bits[0], nbits);
711}
712static inline int bau_uvhub_weight(struct pnmask *dstp)
713{
714 return bitmap_weight((unsigned long *)&dstp->bits[0],
715 UV_DISTRIBUTION_SIZE);
716}
717
718static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
719{
720 bitmap_zero(&dstp->bits, nbits);
721}
722
723extern void uv_bau_message_intr1(void);
724extern void uv_bau_timeout_intr1(void);
725
726struct atomic_short {
727 short counter;
728};
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736static inline int atomic_read_short(const struct atomic_short *v)
737{
738 return v->counter;
739}
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748static inline int atom_asr(short i, struct atomic_short *v)
749{
750 return i + xadd(&v->counter, i);
751}
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763static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
764{
765 spin_lock(lock);
766 if (atomic_read(v) >= u) {
767 spin_unlock(lock);
768 return 0;
769 }
770 atomic_inc(v);
771 spin_unlock(lock);
772 return 1;
773}
774
775#endif
776