LXR linux/drivers/gpu/drm/nouveau/nv40

   1/*
   2 * Copyright (C) 2007 Ben Skeggs.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining
   6 * a copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sublicense, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * The above copyright notice and this permission notice (including the
  14 * next paragraph) shall be included in all copies or substantial
  15 * portions of the Software.
  16 *
  17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24 *
  25 */
  26
  27#include "drmP.h"
  28#include "drm.h"
  29#include "nouveau_drv.h"
  30#include "nouveau_fifo.h"
  31#include "nouveau_ramht.h"
  32
  33struct nv40_graph_engine {
  34        struct nouveau_exec_engine base;
  35        u32 grctx_size;
  36};
  37
  38static int
  39nv40_graph_context_new(struct nouveau_channel *chan, int engine)
  40{
  41        struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
  42        struct drm_device *dev = chan->dev;
  43        struct drm_nouveau_private *dev_priv = dev->dev_private;
  44        struct nouveau_gpuobj *grctx = NULL;
  45        unsigned long flags;
  46        int ret;
  47
  48        ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
  49                                 NVOBJ_FLAG_ZERO_ALLOC, &grctx);
  50        if (ret)
  51                return ret;
  52
  53        /* Initialise default context values */
  54        nv40_grctx_fill(dev, grctx);
  55        nv_wo32(grctx, 0, grctx->vinst);
  56
  57        /* init grctx pointer in ramfc, and on PFIFO if channel is
  58         * already active there
  59         */
  60        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
  61        nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
  62        nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
  63        if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
  64                nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
  65        nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
  66        spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
  67
  68        chan->engctx[engine] = grctx;
  69        return 0;
  70}
  71
  72static void
  73nv40_graph_context_del(struct nouveau_channel *chan, int engine)
  74{
  75        struct nouveau_gpuobj *grctx = chan->engctx[engine];
  76        struct drm_device *dev = chan->dev;
  77        struct drm_nouveau_private *dev_priv = dev->dev_private;
  78        u32 inst = 0x01000000 | (grctx->pinst >> 4);
  79        unsigned long flags;
  80
  81        spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
  82        nv_mask(dev, 0x400720, 0x00000000, 0x00000001);
  83        if (nv_rd32(dev, 0x40032c) == inst)
  84                nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
  85        if (nv_rd32(dev, 0x400330) == inst)
  86                nv_mask(dev, 0x400330, 0x01000000, 0x00000000);
  87        nv_mask(dev, 0x400720, 0x00000001, 0x00000001);
  88        spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
  89
  90        /* Free the context resources */
  91        nouveau_gpuobj_ref(NULL, &grctx);
  92        chan->engctx[engine] = NULL;
  93}
  94
  95int
  96nv40_graph_object_new(struct nouveau_channel *chan, int engine,
  97                      u32 handle, u16 class)
  98{
  99        struct drm_device *dev = chan->dev;
 100        struct nouveau_gpuobj *obj = NULL;
 101        int ret;
 102
 103        ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
 104        if (ret)
 105                return ret;
 106        obj->engine = 1;
 107        obj->class  = class;
 108
 109        nv_wo32(obj, 0x00, class);
 110        nv_wo32(obj, 0x04, 0x00000000);
 111#ifndef __BIG_ENDIAN
 112        nv_wo32(obj, 0x08, 0x00000000);
 113#else
 114        nv_wo32(obj, 0x08, 0x01000000);
 115#endif
 116        nv_wo32(obj, 0x0c, 0x00000000);
 117        nv_wo32(obj, 0x10, 0x00000000);
 118
 119        ret = nouveau_ramht_insert(chan, handle, obj);
 120        nouveau_gpuobj_ref(NULL, &obj);
 121        return ret;
 122}
 123
 124static void
 125nv40_graph_set_tile_region(struct drm_device *dev, int i)
 126{
 127        struct drm_nouveau_private *dev_priv = dev->dev_private;
 128        struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 129
 130        switch (dev_priv->chipset) {
 131        case 0x40:
 132        case 0x41: /* guess */
 133        case 0x42:
 134        case 0x43:
 135        case 0x45: /* guess */
 136        case 0x4e:
 137                nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 138                nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 139                nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 140                nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 141                nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 142                nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 143                break;
 144        case 0x44:
 145        case 0x4a:
 146                nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
 147                nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
 148                nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
 149                break;
 150        case 0x46:
 151        case 0x47:
 152        case 0x49:
 153        case 0x4b:
 154        case 0x4c:
 155        case 0x67:
 156        default:
 157                nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
 158                nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
 159                nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
 160                nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
 161                nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
 162                nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
 163                break;
 164        }
 165}
 166
 167/*
 168 * G70          0x47
 169 * G71          0x49
 170 * NV45         0x48
 171 * G72[M]       0x46
 172 * G73          0x4b
 173 * C51_G7X      0x4c
 174 * C51          0x4e
 175 */
 176int
 177nv40_graph_init(struct drm_device *dev, int engine)
 178{
 179        struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
 180        struct drm_nouveau_private *dev_priv = dev->dev_private;
 181        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 182        uint32_t vramsz;
 183        int i, j;
 184
 185        nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
 186                        ~NV_PMC_ENABLE_PGRAPH);
 187        nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 188                         NV_PMC_ENABLE_PGRAPH);
 189
 190        /* generate and upload context program */
 191        nv40_grctx_init(dev, &pgraph->grctx_size);
 192
 193        /* No context present currently */
 194        nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
 195
 196        nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 197        nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
 198
 199        nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
 200        nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
 201        nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
 202        nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
 203        nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
 204        nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
 205
 206        nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
 207        nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
 208
 209        j = nv_rd32(dev, 0x1540) & 0xff;
 210        if (j) {
 211                for (i = 0; !(j & 1); j >>= 1, i++)
 212                        ;
 213                nv_wr32(dev, 0x405000, i);
 214        }
 215
 216        if (dev_priv->chipset == 0x40) {
 217                nv_wr32(dev, 0x4009b0, 0x83280fff);
 218                nv_wr32(dev, 0x4009b4, 0x000000a0);
 219        } else {
 220                nv_wr32(dev, 0x400820, 0x83280eff);
 221                nv_wr32(dev, 0x400824, 0x000000a0);
 222        }
 223
 224        switch (dev_priv->chipset) {
 225        case 0x40:
 226        case 0x45:
 227                nv_wr32(dev, 0x4009b8, 0x0078e366);
 228                nv_wr32(dev, 0x4009bc, 0x0000014c);
 229                break;
 230        case 0x41:
 231        case 0x42: /* pciid also 0x00Cx */
 232        /* case 0x0120: XXX (pciid) */
 233                nv_wr32(dev, 0x400828, 0x007596ff);
 234                nv_wr32(dev, 0x40082c, 0x00000108);
 235                break;
 236        case 0x43:
 237                nv_wr32(dev, 0x400828, 0x0072cb77);
 238                nv_wr32(dev, 0x40082c, 0x00000108);
 239                break;
 240        case 0x44:
 241        case 0x46: /* G72 */
 242        case 0x4a:
 243        case 0x4c: /* G7x-based C51 */
 244        case 0x4e:
 245                nv_wr32(dev, 0x400860, 0);
 246                nv_wr32(dev, 0x400864, 0);
 247                break;
 248        case 0x47: /* G70 */
 249        case 0x49: /* G71 */
 250        case 0x4b: /* G73 */
 251                nv_wr32(dev, 0x400828, 0x07830610);
 252                nv_wr32(dev, 0x40082c, 0x0000016A);
 253                break;
 254        default:
 255                break;
 256        }
 257
 258        nv_wr32(dev, 0x400b38, 0x2ffff800);
 259        nv_wr32(dev, 0x400b3c, 0x00006000);
 260
 261        /* Tiling related stuff. */
 262        switch (dev_priv->chipset) {
 263        case 0x44:
 264        case 0x4a:
 265                nv_wr32(dev, 0x400bc4, 0x1003d888);
 266                nv_wr32(dev, 0x400bbc, 0xb7a7b500);
 267                break;
 268        case 0x46:
 269                nv_wr32(dev, 0x400bc4, 0x0000e024);
 270                nv_wr32(dev, 0x400bbc, 0xb7a7b520);
 271                break;
 272        case 0x4c:
 273        case 0x4e:
 274        case 0x67:
 275                nv_wr32(dev, 0x400bc4, 0x1003d888);
 276                nv_wr32(dev, 0x400bbc, 0xb7a7b540);
 277                break;
 278        default:
 279                break;
 280        }
 281
 282        /* Turn all the tiling regions off. */
 283        for (i = 0; i < pfb->num_tiles; i++)
 284                nv40_graph_set_tile_region(dev, i);
 285
 286        /* begin RAM config */
 287        vramsz = pci_resource_len(dev->pdev, 0) - 1;
 288        switch (dev_priv->chipset) {
 289        case 0x40:
 290                nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
 291                nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
 292                nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
 293                nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
 294                nv_wr32(dev, 0x400820, 0);
 295                nv_wr32(dev, 0x400824, 0);
 296                nv_wr32(dev, 0x400864, vramsz);
 297                nv_wr32(dev, 0x400868, vramsz);
 298                break;
 299        default:
 300                switch (dev_priv->chipset) {
 301                case 0x41:
 302                case 0x42:
 303                case 0x43:
 304                case 0x45:
 305                case 0x4e:
 306                case 0x44:
 307                case 0x4a:
 308                        nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
 309                        nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
 310                        break;
 311                default:
 312                        nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
 313                        nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
 314                        break;
 315                }
 316                nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
 317                nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
 318                nv_wr32(dev, 0x400840, 0);
 319                nv_wr32(dev, 0x400844, 0);
 320                nv_wr32(dev, 0x4008A0, vramsz);
 321                nv_wr32(dev, 0x4008A4, vramsz);
 322                break;
 323        }
 324
 325        return 0;
 326}
 327
 328static int
 329nv40_graph_fini(struct drm_device *dev, int engine, bool suspend)
 330{
 331        u32 inst = nv_rd32(dev, 0x40032c);
 332        if (inst & 0x01000000) {
 333                nv_wr32(dev, 0x400720, 0x00000000);
 334                nv_wr32(dev, 0x400784, inst);
 335                nv_mask(dev, 0x400310, 0x00000020, 0x00000020);
 336                nv_mask(dev, 0x400304, 0x00000001, 0x00000001);
 337                if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000)) {
 338                        u32 insn = nv_rd32(dev, 0x400308);
 339                        NV_ERROR(dev, "PGRAPH: ctxprog timeout 0x%08x\n", insn);
 340                }
 341                nv_mask(dev, 0x40032c, 0x01000000, 0x00000000);
 342        }
 343        return 0;
 344}
 345
 346static int
 347nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
 348{
 349        struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 350        struct drm_nouveau_private *dev_priv = dev->dev_private;
 351        struct nouveau_gpuobj *grctx;
 352        unsigned long flags;
 353        int i;
 354
 355        spin_lock_irqsave(&dev_priv->channels.lock, flags);
 356        for (i = 0; i < pfifo->channels; i++) {
 357                if (!dev_priv->channels.ptr[i])
 358                        continue;
 359                grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
 360
 361                if (grctx && grctx->pinst == inst)
 362                        break;
 363        }
 364        spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 365        return i;
 366}
 367
 368static void
 369nv40_graph_isr(struct drm_device *dev)
 370{
 371        u32 stat;
 372
 373        while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
 374                u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
 375                u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
 376                u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
 377                u32 chid = nv40_graph_isr_chid(dev, inst);
 378                u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 379                u32 subc = (addr & 0x00070000) >> 16;
 380                u32 mthd = (addr & 0x00001ffc);
 381                u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 382                u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
 383                u32 show = stat;
 384
 385                if (stat & NV_PGRAPH_INTR_ERROR) {
 386                        if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 387                                if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
 388                                        show &= ~NV_PGRAPH_INTR_ERROR;
 389                        } else
 390                        if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
 391                                nv_mask(dev, 0x402000, 0, 0);
 392                        }
 393                }
 394
 395                nv_wr32(dev, NV03_PGRAPH_INTR, stat);
 396                nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
 397
 398                if (show && nouveau_ratelimit()) {
 399                        NV_INFO(dev, "PGRAPH -");
 400                        nouveau_bitfield_print(nv10_graph_intr, show);
 401                        printk(" nsource:");
 402                        nouveau_bitfield_print(nv04_graph_nsource, nsource);
 403                        printk(" nstatus:");
 404                        nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
 405                        printk("\n");
 406                        NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
 407                                     "class 0x%04x mthd 0x%04x data 0x%08x\n",
 408                                chid, inst, subc, class, mthd, data);
 409                }
 410        }
 411}
 412
 413static void
 414nv40_graph_destroy(struct drm_device *dev, int engine)
 415{
 416        struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
 417
 418        nouveau_irq_unregister(dev, 12);
 419
 420        NVOBJ_ENGINE_DEL(dev, GR);
 421        kfree(pgraph);
 422}
 423
 424int
 425nv40_graph_create(struct drm_device *dev)
 426{
 427        struct nv40_graph_engine *pgraph;
 428
 429        pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
 430        if (!pgraph)
 431                return -ENOMEM;
 432
 433        pgraph->base.destroy = nv40_graph_destroy;
 434        pgraph->base.init = nv40_graph_init;
 435        pgraph->base.fini = nv40_graph_fini;
 436        pgraph->base.context_new = nv40_graph_context_new;
 437        pgraph->base.context_del = nv40_graph_context_del;
 438        pgraph->base.object_new = nv40_graph_object_new;
 439        pgraph->base.set_tile_region = nv40_graph_set_tile_region;
 440
 441        NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
 442        nouveau_irq_register(dev, 12, nv40_graph_isr);
 443
 444        NVOBJ_CLASS(dev, 0x0030, GR); /* null */
 445        NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
 446        NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
 447        NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
 448        NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
 449        NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
 450        NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
 451        NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
 452        NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
 453        NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
 454        NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
 455        NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
 456        NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
 457        NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
 458        NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
 459
 460        /* curie */
 461        if (nv44_graph_class(dev))
 462                NVOBJ_CLASS(dev, 0x4497, GR);
 463        else
 464                NVOBJ_CLASS(dev, 0x4097, GR);
 465
 466        return 0;
 467}
 468