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27#include "drmP.h"
28#include "radeon_drm.h"
29#include "radeon.h"
30#include "atom.h"
31
32#ifdef CONFIG_PPC_PMAC
33
34#include <asm/machdep.h>
35#include <asm/pmac_feature.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif
39
40
41extern uint32_t
42radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
43 uint8_t dac);
44extern void radeon_link_encoder_connector(struct drm_device *dev);
45
46
47extern void
48radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id,
50 uint32_t supported_device,
51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id,
54 struct radeon_hpd *hpd);
55
56
57extern void
58radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum,
59 uint32_t supported_device);
60
61
62
63
64enum radeon_combios_table_offset {
65
66 COMBIOS_ASIC_INIT_1_TABLE,
67 COMBIOS_BIOS_SUPPORT_TABLE,
68 COMBIOS_DAC_PROGRAMMING_TABLE,
69 COMBIOS_MAX_COLOR_DEPTH_TABLE,
70 COMBIOS_CRTC_INFO_TABLE,
71 COMBIOS_PLL_INFO_TABLE,
72 COMBIOS_TV_INFO_TABLE,
73 COMBIOS_DFP_INFO_TABLE,
74 COMBIOS_HW_CONFIG_INFO_TABLE,
75 COMBIOS_MULTIMEDIA_INFO_TABLE,
76 COMBIOS_TV_STD_PATCH_TABLE,
77 COMBIOS_LCD_INFO_TABLE,
78 COMBIOS_MOBILE_INFO_TABLE,
79 COMBIOS_PLL_INIT_TABLE,
80 COMBIOS_MEM_CONFIG_TABLE,
81 COMBIOS_SAVE_MASK_TABLE,
82 COMBIOS_HARDCODED_EDID_TABLE,
83 COMBIOS_ASIC_INIT_2_TABLE,
84 COMBIOS_CONNECTOR_INFO_TABLE,
85 COMBIOS_DYN_CLK_1_TABLE,
86 COMBIOS_RESERVED_MEM_TABLE,
87 COMBIOS_EXT_TMDS_INFO_TABLE,
88 COMBIOS_MEM_CLK_INFO_TABLE,
89 COMBIOS_EXT_DAC_INFO_TABLE,
90 COMBIOS_MISC_INFO_TABLE,
91 COMBIOS_CRT_INFO_TABLE,
92 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
93 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
94 COMBIOS_FAN_SPEED_INFO_TABLE,
95 COMBIOS_OVERDRIVE_INFO_TABLE,
96 COMBIOS_OEM_INFO_TABLE,
97 COMBIOS_DYN_CLK_2_TABLE,
98 COMBIOS_POWER_CONNECTOR_INFO_TABLE,
99 COMBIOS_I2C_INFO_TABLE,
100
101 COMBIOS_ASIC_INIT_3_TABLE,
102 COMBIOS_ASIC_INIT_4_TABLE,
103 COMBIOS_DETECTED_MEM_TABLE,
104 COMBIOS_ASIC_INIT_5_TABLE,
105 COMBIOS_RAM_RESET_TABLE,
106 COMBIOS_POWERPLAY_INFO_TABLE,
107 COMBIOS_GPIO_INFO_TABLE,
108 COMBIOS_LCD_DDC_INFO_TABLE,
109 COMBIOS_TMDS_POWER_TABLE,
110 COMBIOS_TMDS_POWER_ON_TABLE,
111 COMBIOS_TMDS_POWER_OFF_TABLE,
112};
113
114enum radeon_combios_ddc {
115 DDC_NONE_DETECTED,
116 DDC_MONID,
117 DDC_DVI,
118 DDC_VGA,
119 DDC_CRT2,
120 DDC_LCD,
121 DDC_GPIO,
122};
123
124enum radeon_combios_connector {
125 CONNECTOR_NONE_LEGACY,
126 CONNECTOR_PROPRIETARY_LEGACY,
127 CONNECTOR_CRT_LEGACY,
128 CONNECTOR_DVI_I_LEGACY,
129 CONNECTOR_DVI_D_LEGACY,
130 CONNECTOR_CTV_LEGACY,
131 CONNECTOR_STV_LEGACY,
132 CONNECTOR_UNSUPPORTED_LEGACY
133};
134
135const int legacy_connector_convert[] = {
136 DRM_MODE_CONNECTOR_Unknown,
137 DRM_MODE_CONNECTOR_DVID,
138 DRM_MODE_CONNECTOR_VGA,
139 DRM_MODE_CONNECTOR_DVII,
140 DRM_MODE_CONNECTOR_DVID,
141 DRM_MODE_CONNECTOR_Composite,
142 DRM_MODE_CONNECTOR_SVIDEO,
143 DRM_MODE_CONNECTOR_Unknown,
144};
145
146static uint16_t combios_get_table_offset(struct drm_device *dev,
147 enum radeon_combios_table_offset table)
148{
149 struct radeon_device *rdev = dev->dev_private;
150 int rev;
151 uint16_t offset = 0, check_offset;
152
153 if (!rdev->bios)
154 return 0;
155
156 switch (table) {
157
158 case COMBIOS_ASIC_INIT_1_TABLE:
159 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160 if (check_offset)
161 offset = check_offset;
162 break;
163 case COMBIOS_BIOS_SUPPORT_TABLE:
164 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165 if (check_offset)
166 offset = check_offset;
167 break;
168 case COMBIOS_DAC_PROGRAMMING_TABLE:
169 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170 if (check_offset)
171 offset = check_offset;
172 break;
173 case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175 if (check_offset)
176 offset = check_offset;
177 break;
178 case COMBIOS_CRTC_INFO_TABLE:
179 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180 if (check_offset)
181 offset = check_offset;
182 break;
183 case COMBIOS_PLL_INFO_TABLE:
184 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185 if (check_offset)
186 offset = check_offset;
187 break;
188 case COMBIOS_TV_INFO_TABLE:
189 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190 if (check_offset)
191 offset = check_offset;
192 break;
193 case COMBIOS_DFP_INFO_TABLE:
194 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195 if (check_offset)
196 offset = check_offset;
197 break;
198 case COMBIOS_HW_CONFIG_INFO_TABLE:
199 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200 if (check_offset)
201 offset = check_offset;
202 break;
203 case COMBIOS_MULTIMEDIA_INFO_TABLE:
204 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205 if (check_offset)
206 offset = check_offset;
207 break;
208 case COMBIOS_TV_STD_PATCH_TABLE:
209 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210 if (check_offset)
211 offset = check_offset;
212 break;
213 case COMBIOS_LCD_INFO_TABLE:
214 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215 if (check_offset)
216 offset = check_offset;
217 break;
218 case COMBIOS_MOBILE_INFO_TABLE:
219 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220 if (check_offset)
221 offset = check_offset;
222 break;
223 case COMBIOS_PLL_INIT_TABLE:
224 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225 if (check_offset)
226 offset = check_offset;
227 break;
228 case COMBIOS_MEM_CONFIG_TABLE:
229 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230 if (check_offset)
231 offset = check_offset;
232 break;
233 case COMBIOS_SAVE_MASK_TABLE:
234 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235 if (check_offset)
236 offset = check_offset;
237 break;
238 case COMBIOS_HARDCODED_EDID_TABLE:
239 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240 if (check_offset)
241 offset = check_offset;
242 break;
243 case COMBIOS_ASIC_INIT_2_TABLE:
244 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245 if (check_offset)
246 offset = check_offset;
247 break;
248 case COMBIOS_CONNECTOR_INFO_TABLE:
249 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250 if (check_offset)
251 offset = check_offset;
252 break;
253 case COMBIOS_DYN_CLK_1_TABLE:
254 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255 if (check_offset)
256 offset = check_offset;
257 break;
258 case COMBIOS_RESERVED_MEM_TABLE:
259 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260 if (check_offset)
261 offset = check_offset;
262 break;
263 case COMBIOS_EXT_TMDS_INFO_TABLE:
264 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265 if (check_offset)
266 offset = check_offset;
267 break;
268 case COMBIOS_MEM_CLK_INFO_TABLE:
269 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270 if (check_offset)
271 offset = check_offset;
272 break;
273 case COMBIOS_EXT_DAC_INFO_TABLE:
274 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275 if (check_offset)
276 offset = check_offset;
277 break;
278 case COMBIOS_MISC_INFO_TABLE:
279 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280 if (check_offset)
281 offset = check_offset;
282 break;
283 case COMBIOS_CRT_INFO_TABLE:
284 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285 if (check_offset)
286 offset = check_offset;
287 break;
288 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290 if (check_offset)
291 offset = check_offset;
292 break;
293 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295 if (check_offset)
296 offset = check_offset;
297 break;
298 case COMBIOS_FAN_SPEED_INFO_TABLE:
299 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300 if (check_offset)
301 offset = check_offset;
302 break;
303 case COMBIOS_OVERDRIVE_INFO_TABLE:
304 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305 if (check_offset)
306 offset = check_offset;
307 break;
308 case COMBIOS_OEM_INFO_TABLE:
309 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310 if (check_offset)
311 offset = check_offset;
312 break;
313 case COMBIOS_DYN_CLK_2_TABLE:
314 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315 if (check_offset)
316 offset = check_offset;
317 break;
318 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320 if (check_offset)
321 offset = check_offset;
322 break;
323 case COMBIOS_I2C_INFO_TABLE:
324 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325 if (check_offset)
326 offset = check_offset;
327 break;
328
329 case COMBIOS_ASIC_INIT_3_TABLE:
330 check_offset =
331 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
332 if (check_offset) {
333 rev = RBIOS8(check_offset);
334 if (rev > 0) {
335 check_offset = RBIOS16(check_offset + 0x3);
336 if (check_offset)
337 offset = check_offset;
338 }
339 }
340 break;
341 case COMBIOS_ASIC_INIT_4_TABLE:
342 check_offset =
343 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
344 if (check_offset) {
345 rev = RBIOS8(check_offset);
346 if (rev > 0) {
347 check_offset = RBIOS16(check_offset + 0x5);
348 if (check_offset)
349 offset = check_offset;
350 }
351 }
352 break;
353 case COMBIOS_DETECTED_MEM_TABLE:
354 check_offset =
355 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
356 if (check_offset) {
357 rev = RBIOS8(check_offset);
358 if (rev > 0) {
359 check_offset = RBIOS16(check_offset + 0x7);
360 if (check_offset)
361 offset = check_offset;
362 }
363 }
364 break;
365 case COMBIOS_ASIC_INIT_5_TABLE:
366 check_offset =
367 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
368 if (check_offset) {
369 rev = RBIOS8(check_offset);
370 if (rev == 2) {
371 check_offset = RBIOS16(check_offset + 0x9);
372 if (check_offset)
373 offset = check_offset;
374 }
375 }
376 break;
377 case COMBIOS_RAM_RESET_TABLE:
378 check_offset =
379 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
380 if (check_offset) {
381 while (RBIOS8(check_offset++));
382 check_offset += 2;
383 if (check_offset)
384 offset = check_offset;
385 }
386 break;
387 case COMBIOS_POWERPLAY_INFO_TABLE:
388 check_offset =
389 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
390 if (check_offset) {
391 check_offset = RBIOS16(check_offset + 0x11);
392 if (check_offset)
393 offset = check_offset;
394 }
395 break;
396 case COMBIOS_GPIO_INFO_TABLE:
397 check_offset =
398 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
399 if (check_offset) {
400 check_offset = RBIOS16(check_offset + 0x13);
401 if (check_offset)
402 offset = check_offset;
403 }
404 break;
405 case COMBIOS_LCD_DDC_INFO_TABLE:
406 check_offset =
407 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
408 if (check_offset) {
409 check_offset = RBIOS16(check_offset + 0x15);
410 if (check_offset)
411 offset = check_offset;
412 }
413 break;
414 case COMBIOS_TMDS_POWER_TABLE:
415 check_offset =
416 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
417 if (check_offset) {
418 check_offset = RBIOS16(check_offset + 0x17);
419 if (check_offset)
420 offset = check_offset;
421 }
422 break;
423 case COMBIOS_TMDS_POWER_ON_TABLE:
424 check_offset =
425 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
426 if (check_offset) {
427 check_offset = RBIOS16(check_offset + 0x2);
428 if (check_offset)
429 offset = check_offset;
430 }
431 break;
432 case COMBIOS_TMDS_POWER_OFF_TABLE:
433 check_offset =
434 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
435 if (check_offset) {
436 check_offset = RBIOS16(check_offset + 0x4);
437 if (check_offset)
438 offset = check_offset;
439 }
440 break;
441 default:
442 break;
443 }
444
445 return offset;
446
447}
448
449bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
450{
451 int edid_info, size;
452 struct edid *edid;
453 unsigned char *raw;
454 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE);
455 if (!edid_info)
456 return false;
457
458 raw = rdev->bios + edid_info;
459 size = EDID_LENGTH * (raw[0x7e] + 1);
460 edid = kmalloc(size, GFP_KERNEL);
461 if (edid == NULL)
462 return false;
463
464 memcpy((unsigned char *)edid, raw, size);
465
466 if (!drm_edid_is_valid(edid)) {
467 kfree(edid);
468 return false;
469 }
470
471 rdev->mode_info.bios_hardcoded_edid = edid;
472 rdev->mode_info.bios_hardcoded_edid_size = size;
473 return true;
474}
475
476
477struct edid *
478radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)
479{
480 struct edid *edid;
481
482 if (rdev->mode_info.bios_hardcoded_edid) {
483 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL);
484 if (edid) {
485 memcpy((unsigned char *)edid,
486 (unsigned char *)rdev->mode_info.bios_hardcoded_edid,
487 rdev->mode_info.bios_hardcoded_edid_size);
488 return edid;
489 }
490 }
491 return NULL;
492}
493
494static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,
495 enum radeon_combios_ddc ddc,
496 u32 clk_mask,
497 u32 data_mask)
498{
499 struct radeon_i2c_bus_rec i2c;
500 int ddc_line = 0;
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524 switch (ddc) {
525 case DDC_NONE_DETECTED:
526 default:
527 ddc_line = 0;
528 break;
529 case DDC_DVI:
530 ddc_line = RADEON_GPIO_DVI_DDC;
531 break;
532 case DDC_VGA:
533 ddc_line = RADEON_GPIO_VGA_DDC;
534 break;
535 case DDC_LCD:
536 ddc_line = RADEON_GPIOPAD_MASK;
537 break;
538 case DDC_GPIO:
539 ddc_line = RADEON_MDGPIO_MASK;
540 break;
541 case DDC_MONID:
542 if (rdev->family == CHIP_RS300 ||
543 rdev->family == CHIP_RS400 ||
544 rdev->family == CHIP_RS480)
545 ddc_line = RADEON_GPIOPAD_MASK;
546 else if (rdev->family == CHIP_R300 ||
547 rdev->family == CHIP_R350) {
548 ddc_line = RADEON_GPIO_DVI_DDC;
549 ddc = DDC_DVI;
550 } else
551 ddc_line = RADEON_GPIO_MONID;
552 break;
553 case DDC_CRT2:
554 if (rdev->family == CHIP_R200 ||
555 rdev->family == CHIP_R300 ||
556 rdev->family == CHIP_R350) {
557 ddc_line = RADEON_GPIO_DVI_DDC;
558 ddc = DDC_DVI;
559 } else if (rdev->family == CHIP_RS300 ||
560 rdev->family == CHIP_RS400 ||
561 rdev->family == CHIP_RS480)
562 ddc_line = RADEON_GPIO_MONID;
563 else if (rdev->family >= CHIP_RV350) {
564 ddc_line = RADEON_GPIO_MONID;
565 ddc = DDC_MONID;
566 } else
567 ddc_line = RADEON_GPIO_CRT2_DDC;
568 break;
569 }
570
571 if (ddc_line == RADEON_GPIOPAD_MASK) {
572 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;
573 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;
574 i2c.a_clk_reg = RADEON_GPIOPAD_A;
575 i2c.a_data_reg = RADEON_GPIOPAD_A;
576 i2c.en_clk_reg = RADEON_GPIOPAD_EN;
577 i2c.en_data_reg = RADEON_GPIOPAD_EN;
578 i2c.y_clk_reg = RADEON_GPIOPAD_Y;
579 i2c.y_data_reg = RADEON_GPIOPAD_Y;
580 } else if (ddc_line == RADEON_MDGPIO_MASK) {
581 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;
582 i2c.mask_data_reg = RADEON_MDGPIO_MASK;
583 i2c.a_clk_reg = RADEON_MDGPIO_A;
584 i2c.a_data_reg = RADEON_MDGPIO_A;
585 i2c.en_clk_reg = RADEON_MDGPIO_EN;
586 i2c.en_data_reg = RADEON_MDGPIO_EN;
587 i2c.y_clk_reg = RADEON_MDGPIO_Y;
588 i2c.y_data_reg = RADEON_MDGPIO_Y;
589 } else {
590 i2c.mask_clk_reg = ddc_line;
591 i2c.mask_data_reg = ddc_line;
592 i2c.a_clk_reg = ddc_line;
593 i2c.a_data_reg = ddc_line;
594 i2c.en_clk_reg = ddc_line;
595 i2c.en_data_reg = ddc_line;
596 i2c.y_clk_reg = ddc_line;
597 i2c.y_data_reg = ddc_line;
598 }
599
600 if (clk_mask && data_mask) {
601
602 i2c.mask_clk_mask = clk_mask;
603 i2c.mask_data_mask = data_mask;
604 i2c.a_clk_mask = clk_mask;
605 i2c.a_data_mask = data_mask;
606 i2c.en_clk_mask = clk_mask;
607 i2c.en_data_mask = data_mask;
608 i2c.y_clk_mask = clk_mask;
609 i2c.y_data_mask = data_mask;
610 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||
611 (ddc_line == RADEON_MDGPIO_MASK)) {
612
613 i2c.mask_clk_mask = (0x20 << 8);
614 i2c.mask_data_mask = 0x80;
615 i2c.a_clk_mask = (0x20 << 8);
616 i2c.a_data_mask = 0x80;
617 i2c.en_clk_mask = (0x20 << 8);
618 i2c.en_data_mask = 0x80;
619 i2c.y_clk_mask = (0x20 << 8);
620 i2c.y_data_mask = 0x80;
621 } else {
622
623 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;
624 i2c.mask_data_mask = RADEON_GPIO_MASK_0;
625 i2c.a_clk_mask = RADEON_GPIO_A_1;
626 i2c.a_data_mask = RADEON_GPIO_A_0;
627 i2c.en_clk_mask = RADEON_GPIO_EN_1;
628 i2c.en_data_mask = RADEON_GPIO_EN_0;
629 i2c.y_clk_mask = RADEON_GPIO_Y_1;
630 i2c.y_data_mask = RADEON_GPIO_Y_0;
631 }
632
633 switch (rdev->family) {
634 case CHIP_R100:
635 case CHIP_RV100:
636 case CHIP_RS100:
637 case CHIP_RV200:
638 case CHIP_RS200:
639 case CHIP_RS300:
640 switch (ddc_line) {
641 case RADEON_GPIO_DVI_DDC:
642 i2c.hw_capable = true;
643 break;
644 default:
645 i2c.hw_capable = false;
646 break;
647 }
648 break;
649 case CHIP_R200:
650 switch (ddc_line) {
651 case RADEON_GPIO_DVI_DDC:
652 case RADEON_GPIO_MONID:
653 i2c.hw_capable = true;
654 break;
655 default:
656 i2c.hw_capable = false;
657 break;
658 }
659 break;
660 case CHIP_RV250:
661 case CHIP_RV280:
662 switch (ddc_line) {
663 case RADEON_GPIO_VGA_DDC:
664 case RADEON_GPIO_DVI_DDC:
665 case RADEON_GPIO_CRT2_DDC:
666 i2c.hw_capable = true;
667 break;
668 default:
669 i2c.hw_capable = false;
670 break;
671 }
672 break;
673 case CHIP_R300:
674 case CHIP_R350:
675 switch (ddc_line) {
676 case RADEON_GPIO_VGA_DDC:
677 case RADEON_GPIO_DVI_DDC:
678 i2c.hw_capable = true;
679 break;
680 default:
681 i2c.hw_capable = false;
682 break;
683 }
684 break;
685 case CHIP_RV350:
686 case CHIP_RV380:
687 case CHIP_RS400:
688 case CHIP_RS480:
689 switch (ddc_line) {
690 case RADEON_GPIO_VGA_DDC:
691 case RADEON_GPIO_DVI_DDC:
692 i2c.hw_capable = true;
693 break;
694 case RADEON_GPIO_MONID:
695
696
697
698 i2c.hw_capable = false;
699 break;
700 default:
701 i2c.hw_capable = false;
702 break;
703 }
704 break;
705 default:
706 i2c.hw_capable = false;
707 break;
708 }
709 i2c.mm_i2c = false;
710
711 i2c.i2c_id = ddc;
712 i2c.hpd = RADEON_HPD_NONE;
713
714 if (ddc_line)
715 i2c.valid = true;
716 else
717 i2c.valid = false;
718
719 return i2c;
720}
721
722void radeon_combios_i2c_init(struct radeon_device *rdev)
723{
724 struct drm_device *dev = rdev->ddev;
725 struct radeon_i2c_bus_rec i2c;
726
727
728
729
730
731
732
733
734
735
736
737
738
739 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
740 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
741
742 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
743 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
744
745
746 i2c.valid = true;
747 i2c.hw_capable = true;
748 i2c.mm_i2c = true;
749 i2c.i2c_id = 0xa0;
750 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
751
752 if (rdev->family == CHIP_R300 ||
753 rdev->family == CHIP_R350) {
754
755 } else if (rdev->family == CHIP_RS300 ||
756 rdev->family == CHIP_RS400 ||
757 rdev->family == CHIP_RS480) {
758 u16 offset;
759 u8 id, blocks, clk, data;
760 int i;
761
762
763 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
764 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
765
766 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);
767 if (offset) {
768 blocks = RBIOS8(offset + 2);
769 for (i = 0; i < blocks; i++) {
770 id = RBIOS8(offset + 3 + (i * 5) + 0);
771 if (id == 136) {
772 clk = RBIOS8(offset + 3 + (i * 5) + 3);
773 data = RBIOS8(offset + 3 + (i * 5) + 4);
774
775 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
776 (1 << clk), (1 << data));
777 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
778 break;
779 }
780 }
781 }
782 } else if ((rdev->family == CHIP_R200) ||
783 (rdev->family >= CHIP_R300)) {
784
785 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
786 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
787 } else {
788
789 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
790 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
791
792 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
793 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
794 }
795}
796
797bool radeon_combios_get_clock_info(struct drm_device *dev)
798{
799 struct radeon_device *rdev = dev->dev_private;
800 uint16_t pll_info;
801 struct radeon_pll *p1pll = &rdev->clock.p1pll;
802 struct radeon_pll *p2pll = &rdev->clock.p2pll;
803 struct radeon_pll *spll = &rdev->clock.spll;
804 struct radeon_pll *mpll = &rdev->clock.mpll;
805 int8_t rev;
806 uint16_t sclk, mclk;
807
808 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
809 if (pll_info) {
810 rev = RBIOS8(pll_info);
811
812
813 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
814 p1pll->reference_div = RBIOS16(pll_info + 0x10);
815 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
816 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
817 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
818 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
819
820 if (rev > 9) {
821 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
822 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
823 } else {
824 p1pll->pll_in_min = 40;
825 p1pll->pll_in_max = 500;
826 }
827 *p2pll = *p1pll;
828
829
830 spll->reference_freq = RBIOS16(pll_info + 0x1a);
831 spll->reference_div = RBIOS16(pll_info + 0x1c);
832 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
833 spll->pll_out_max = RBIOS32(pll_info + 0x22);
834
835 if (rev > 10) {
836 spll->pll_in_min = RBIOS32(pll_info + 0x48);
837 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
838 } else {
839
840 spll->pll_in_min = 40;
841 spll->pll_in_max = 500;
842 }
843
844
845 mpll->reference_freq = RBIOS16(pll_info + 0x26);
846 mpll->reference_div = RBIOS16(pll_info + 0x28);
847 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
848 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
849
850 if (rev > 10) {
851 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
852 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
853 } else {
854
855 mpll->pll_in_min = 40;
856 mpll->pll_in_max = 500;
857 }
858
859
860 sclk = RBIOS16(pll_info + 0xa);
861 mclk = RBIOS16(pll_info + 0x8);
862 if (sclk == 0)
863 sclk = 200 * 100;
864 if (mclk == 0)
865 mclk = 200 * 100;
866
867 rdev->clock.default_sclk = sclk;
868 rdev->clock.default_mclk = mclk;
869
870 if (RBIOS32(pll_info + 0x16))
871 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
872 else
873 rdev->clock.max_pixel_clock = 35000;
874
875 return true;
876 }
877 return false;
878}
879
880bool radeon_combios_sideport_present(struct radeon_device *rdev)
881{
882 struct drm_device *dev = rdev->ddev;
883 u16 igp_info;
884
885
886 if (rdev->family == CHIP_RS400)
887 return false;
888
889 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
890
891 if (igp_info) {
892 if (RBIOS16(igp_info + 0x4))
893 return true;
894 }
895 return false;
896}
897
898static const uint32_t default_primarydac_adj[CHIP_LAST] = {
899 0x00000808,
900 0x00000808,
901 0x00000808,
902 0x00000808,
903 0x00000808,
904 0x00000808,
905 0x00000808,
906 0x00000000,
907 0x00000808,
908 0x00000808,
909 0x00000808,
910 0x00000808,
911 0x00000808,
912 0x00000808,
913 0x00000808,
914 0x00000808,
915 0x00000000,
916 0x00000000,
917};
918
919static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,
920 struct radeon_encoder_primary_dac *p_dac)
921{
922 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
923 return;
924}
925
926struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
927 radeon_encoder
928 *encoder)
929{
930 struct drm_device *dev = encoder->base.dev;
931 struct radeon_device *rdev = dev->dev_private;
932 uint16_t dac_info;
933 uint8_t rev, bg, dac;
934 struct radeon_encoder_primary_dac *p_dac = NULL;
935 int found = 0;
936
937 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
938 GFP_KERNEL);
939
940 if (!p_dac)
941 return NULL;
942
943
944 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
945 if (dac_info) {
946 rev = RBIOS8(dac_info) & 0x3;
947 if (rev < 2) {
948 bg = RBIOS8(dac_info + 0x2) & 0xf;
949 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
950 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
951 } else {
952 bg = RBIOS8(dac_info + 0x2) & 0xf;
953 dac = RBIOS8(dac_info + 0x3) & 0xf;
954 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
955 }
956
957 if (p_dac->ps2_pdac_adj)
958 found = 1;
959 }
960
961 if (!found)
962 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);
963
964 return p_dac;
965}
966
967enum radeon_tv_std
968radeon_combios_get_tv_info(struct radeon_device *rdev)
969{
970 struct drm_device *dev = rdev->ddev;
971 uint16_t tv_info;
972 enum radeon_tv_std tv_std = TV_STD_NTSC;
973
974 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
975 if (tv_info) {
976 if (RBIOS8(tv_info + 6) == 'T') {
977 switch (RBIOS8(tv_info + 7) & 0xf) {
978 case 1:
979 tv_std = TV_STD_NTSC;
980 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
981 break;
982 case 2:
983 tv_std = TV_STD_PAL;
984 DRM_DEBUG_KMS("Default TV standard: PAL\n");
985 break;
986 case 3:
987 tv_std = TV_STD_PAL_M;
988 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
989 break;
990 case 4:
991 tv_std = TV_STD_PAL_60;
992 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
993 break;
994 case 5:
995 tv_std = TV_STD_NTSC_J;
996 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
997 break;
998 case 6:
999 tv_std = TV_STD_SCART_PAL;
1000 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
1001 break;
1002 default:
1003 tv_std = TV_STD_NTSC;
1004 DRM_DEBUG_KMS
1005 ("Unknown TV standard; defaulting to NTSC\n");
1006 break;
1007 }
1008
1009 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
1010 case 0:
1011 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");
1012 break;
1013 case 1:
1014 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");
1015 break;
1016 case 2:
1017 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");
1018 break;
1019 case 3:
1020 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");
1021 break;
1022 default:
1023 break;
1024 }
1025 }
1026 }
1027 return tv_std;
1028}
1029
1030static const uint32_t default_tvdac_adj[CHIP_LAST] = {
1031 0x00000000,
1032 0x00280000,
1033 0x00000000,
1034 0x00880000,
1035 0x00000000,
1036 0x00000000,
1037 0x00770000,
1038 0x00290000,
1039 0x00560000,
1040 0x00780000,
1041 0x00770000,
1042 0x00780000,
1043 0x00780000,
1044 0x01080000,
1045 0x01080000,
1046 0x01080000,
1047 0x00780000,
1048 0x00780000,
1049};
1050
1051static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
1052 struct radeon_encoder_tv_dac *tv_dac)
1053{
1054 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
1055 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
1056 tv_dac->ps2_tvdac_adj = 0x00880000;
1057 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1058 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1059 return;
1060}
1061
1062struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
1063 radeon_encoder
1064 *encoder)
1065{
1066 struct drm_device *dev = encoder->base.dev;
1067 struct radeon_device *rdev = dev->dev_private;
1068 uint16_t dac_info;
1069 uint8_t rev, bg, dac;
1070 struct radeon_encoder_tv_dac *tv_dac = NULL;
1071 int found = 0;
1072
1073 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1074 if (!tv_dac)
1075 return NULL;
1076
1077
1078 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1079 if (dac_info) {
1080 rev = RBIOS8(dac_info + 0x3);
1081 if (rev > 4) {
1082 bg = RBIOS8(dac_info + 0xc) & 0xf;
1083 dac = RBIOS8(dac_info + 0xd) & 0xf;
1084 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1085
1086 bg = RBIOS8(dac_info + 0xe) & 0xf;
1087 dac = RBIOS8(dac_info + 0xf) & 0xf;
1088 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1089
1090 bg = RBIOS8(dac_info + 0x10) & 0xf;
1091 dac = RBIOS8(dac_info + 0x11) & 0xf;
1092 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1093
1094 if (tv_dac->ps2_tvdac_adj)
1095 found = 1;
1096 } else if (rev > 1) {
1097 bg = RBIOS8(dac_info + 0xc) & 0xf;
1098 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
1099 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1100
1101 bg = RBIOS8(dac_info + 0xd) & 0xf;
1102 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
1103 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1104
1105 bg = RBIOS8(dac_info + 0xe) & 0xf;
1106 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
1107 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1108
1109 if (tv_dac->ps2_tvdac_adj)
1110 found = 1;
1111 }
1112 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1113 }
1114 if (!found) {
1115
1116 dac_info =
1117 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1118 if (dac_info) {
1119 rev = RBIOS8(dac_info) & 0x3;
1120 if (rev < 2) {
1121 bg = RBIOS8(dac_info + 0x3) & 0xf;
1122 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
1123 tv_dac->ps2_tvdac_adj =
1124 (bg << 16) | (dac << 20);
1125 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1126 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1127
1128 if (tv_dac->ps2_tvdac_adj)
1129 found = 1;
1130 } else {
1131 bg = RBIOS8(dac_info + 0x4) & 0xf;
1132 dac = RBIOS8(dac_info + 0x5) & 0xf;
1133 tv_dac->ps2_tvdac_adj =
1134 (bg << 16) | (dac << 20);
1135 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1136 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1137
1138 if (tv_dac->ps2_tvdac_adj)
1139 found = 1;
1140 }
1141 } else {
1142 DRM_INFO("No TV DAC info found in BIOS\n");
1143 }
1144 }
1145
1146 if (!found)
1147 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
1148
1149 return tv_dac;
1150}
1151
1152static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
1153 radeon_device
1154 *rdev)
1155{
1156 struct radeon_encoder_lvds *lvds = NULL;
1157 uint32_t fp_vert_stretch, fp_horz_stretch;
1158 uint32_t ppll_div_sel, ppll_val;
1159 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
1160
1161 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1162
1163 if (!lvds)
1164 return NULL;
1165
1166 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
1167 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
1168
1169
1170 lvds->panel_pwr_delay = 200;
1171 lvds->panel_vcc_delay = 2000;
1172
1173 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1174 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1175 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1176
1177 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
1178 lvds->native_mode.vdisplay =
1179 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
1180 RADEON_VERT_PANEL_SHIFT) + 1;
1181 else
1182 lvds->native_mode.vdisplay =
1183 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
1184
1185 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
1186 lvds->native_mode.hdisplay =
1187 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
1188 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
1189 else
1190 lvds->native_mode.hdisplay =
1191 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
1192
1193 if ((lvds->native_mode.hdisplay < 640) ||
1194 (lvds->native_mode.vdisplay < 480)) {
1195 lvds->native_mode.hdisplay = 640;
1196 lvds->native_mode.vdisplay = 480;
1197 }
1198
1199 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
1200 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
1201 if ((ppll_val & 0x000707ff) == 0x1bb)
1202 lvds->use_bios_dividers = false;
1203 else {
1204 lvds->panel_ref_divider =
1205 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
1206 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1207 lvds->panel_fb_divider = ppll_val & 0x7ff;
1208
1209 if ((lvds->panel_ref_divider != 0) &&
1210 (lvds->panel_fb_divider > 3))
1211 lvds->use_bios_dividers = true;
1212 }
1213 lvds->panel_vcc_delay = 200;
1214
1215 DRM_INFO("Panel info derived from registers\n");
1216 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1217 lvds->native_mode.vdisplay);
1218
1219 return lvds;
1220}
1221
1222struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
1223 *encoder)
1224{
1225 struct drm_device *dev = encoder->base.dev;
1226 struct radeon_device *rdev = dev->dev_private;
1227 uint16_t lcd_info;
1228 uint32_t panel_setup;
1229 char stmp[30];
1230 int tmp, i;
1231 struct radeon_encoder_lvds *lvds = NULL;
1232
1233 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1234
1235 if (lcd_info) {
1236 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1237
1238 if (!lvds)
1239 return NULL;
1240
1241 for (i = 0; i < 24; i++)
1242 stmp[i] = RBIOS8(lcd_info + i + 1);
1243 stmp[24] = 0;
1244
1245 DRM_INFO("Panel ID String: %s\n", stmp);
1246
1247 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1248 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1249
1250 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1251 lvds->native_mode.vdisplay);
1252
1253 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1254 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1255
1256 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1257 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1258 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1259
1260 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1261 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1262 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1263 if ((lvds->panel_ref_divider != 0) &&
1264 (lvds->panel_fb_divider > 3))
1265 lvds->use_bios_dividers = true;
1266
1267 panel_setup = RBIOS32(lcd_info + 0x39);
1268 lvds->lvds_gen_cntl = 0xff00;
1269 if (panel_setup & 0x1)
1270 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1271
1272 if ((panel_setup >> 4) & 0x1)
1273 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1274
1275 switch ((panel_setup >> 8) & 0x7) {
1276 case 0:
1277 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1278 break;
1279 case 1:
1280 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1281 break;
1282 case 2:
1283 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1284 break;
1285 default:
1286 break;
1287 }
1288
1289 if ((panel_setup >> 16) & 0x1)
1290 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1291
1292 if ((panel_setup >> 17) & 0x1)
1293 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1294
1295 if ((panel_setup >> 18) & 0x1)
1296 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1297
1298 if ((panel_setup >> 23) & 0x1)
1299 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1300
1301 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1302
1303 for (i = 0; i < 32; i++) {
1304 tmp = RBIOS16(lcd_info + 64 + i * 2);
1305 if (tmp == 0)
1306 break;
1307
1308 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1309 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1310 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1311 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1312 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1313 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1314 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1315 (RBIOS8(tmp + 23) * 8);
1316
1317 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1318 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1319 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1320 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1321 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1322 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
1323
1324 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1325 lvds->native_mode.flags = 0;
1326
1327 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1328
1329 }
1330 }
1331 } else {
1332 DRM_INFO("No panel info found in BIOS\n");
1333 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1334 }
1335
1336 if (lvds)
1337 encoder->native_mode = lvds->native_mode;
1338 return lvds;
1339}
1340
1341static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
1342 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},
1343 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},
1344 {{0, 0}, {0, 0}, {0, 0}, {0, 0}},
1345 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},
1346 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},
1347 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},
1348 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},
1349 {{0, 0}, {0, 0}, {0, 0}, {0, 0}},
1350 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},
1351 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},
1352 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},
1353 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},
1354 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},
1355 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},
1356 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},
1357 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},
1358 { {0, 0}, {0, 0}, {0, 0}, {0, 0} },
1359 { {0, 0}, {0, 0}, {0, 0}, {0, 0} },
1360};
1361
1362bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1363 struct radeon_encoder_int_tmds *tmds)
1364{
1365 struct drm_device *dev = encoder->base.dev;
1366 struct radeon_device *rdev = dev->dev_private;
1367 int i;
1368
1369 for (i = 0; i < 4; i++) {
1370 tmds->tmds_pll[i].value =
1371 default_tmds_pll[rdev->family][i].value;
1372 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1373 }
1374
1375 return true;
1376}
1377
1378bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1379 struct radeon_encoder_int_tmds *tmds)
1380{
1381 struct drm_device *dev = encoder->base.dev;
1382 struct radeon_device *rdev = dev->dev_private;
1383 uint16_t tmds_info;
1384 int i, n;
1385 uint8_t ver;
1386
1387 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1388
1389 if (tmds_info) {
1390 ver = RBIOS8(tmds_info);
1391 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);
1392 if (ver == 3) {
1393 n = RBIOS8(tmds_info + 5) + 1;
1394 if (n > 4)
1395 n = 4;
1396 for (i = 0; i < n; i++) {
1397 tmds->tmds_pll[i].value =
1398 RBIOS32(tmds_info + i * 10 + 0x08);
1399 tmds->tmds_pll[i].freq =
1400 RBIOS16(tmds_info + i * 10 + 0x10);
1401 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1402 tmds->tmds_pll[i].freq,
1403 tmds->tmds_pll[i].value);
1404 }
1405 } else if (ver == 4) {
1406 int stride = 0;
1407 n = RBIOS8(tmds_info + 5) + 1;
1408 if (n > 4)
1409 n = 4;
1410 for (i = 0; i < n; i++) {
1411 tmds->tmds_pll[i].value =
1412 RBIOS32(tmds_info + stride + 0x08);
1413 tmds->tmds_pll[i].freq =
1414 RBIOS16(tmds_info + stride + 0x10);
1415 if (i == 0)
1416 stride += 10;
1417 else
1418 stride += 6;
1419 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",
1420 tmds->tmds_pll[i].freq,
1421 tmds->tmds_pll[i].value);
1422 }
1423 }
1424 } else {
1425 DRM_INFO("No TMDS info found in BIOS\n");
1426 return false;
1427 }
1428 return true;
1429}
1430
1431bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1432 struct radeon_encoder_ext_tmds *tmds)
1433{
1434 struct drm_device *dev = encoder->base.dev;
1435 struct radeon_device *rdev = dev->dev_private;
1436 struct radeon_i2c_bus_rec i2c_bus;
1437
1438
1439 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1440 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1441
1442
1443 switch (rdev->mode_info.connector_table) {
1444 case CT_POWERBOOK_EXTERNAL:
1445 case CT_MINI_EXTERNAL:
1446 default:
1447 tmds->dvo_chip = DVO_SIL164;
1448 tmds->slave_addr = 0x70 >> 1;
1449 break;
1450 }
1451
1452 return true;
1453}
1454
1455bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1456 struct radeon_encoder_ext_tmds *tmds)
1457{
1458 struct drm_device *dev = encoder->base.dev;
1459 struct radeon_device *rdev = dev->dev_private;
1460 uint16_t offset;
1461 uint8_t ver;
1462 enum radeon_combios_ddc gpio;
1463 struct radeon_i2c_bus_rec i2c_bus;
1464
1465 tmds->i2c_bus = NULL;
1466 if (rdev->flags & RADEON_IS_IGP) {
1467 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1468 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1469 tmds->dvo_chip = DVO_SIL164;
1470 tmds->slave_addr = 0x70 >> 1;
1471 } else {
1472 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1473 if (offset) {
1474 ver = RBIOS8(offset);
1475 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);
1476 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1477 tmds->slave_addr >>= 1;
1478 gpio = RBIOS8(offset + 4 + 3);
1479 if (gpio == DDC_LCD) {
1480
1481 i2c_bus.valid = true;
1482 i2c_bus.hw_capable = true;
1483 i2c_bus.mm_i2c = true;
1484 i2c_bus.i2c_id = 0xa0;
1485 } else
1486 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
1487 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1488 }
1489 }
1490
1491 if (!tmds->i2c_bus) {
1492 DRM_INFO("No valid Ext TMDS info found in BIOS\n");
1493 return false;
1494 }
1495
1496 return true;
1497}
1498
1499bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1500{
1501 struct radeon_device *rdev = dev->dev_private;
1502 struct radeon_i2c_bus_rec ddc_i2c;
1503 struct radeon_hpd hpd;
1504
1505 rdev->mode_info.connector_table = radeon_connector_table;
1506 if (rdev->mode_info.connector_table == CT_NONE) {
1507#ifdef CONFIG_PPC_PMAC
1508 if (of_machine_is_compatible("PowerBook3,3")) {
1509
1510 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1511 } else if (of_machine_is_compatible("PowerBook3,4") ||
1512 of_machine_is_compatible("PowerBook3,5")) {
1513
1514 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1515 } else if (of_machine_is_compatible("PowerBook5,1") ||
1516 of_machine_is_compatible("PowerBook5,2") ||
1517 of_machine_is_compatible("PowerBook5,3") ||
1518 of_machine_is_compatible("PowerBook5,4") ||
1519 of_machine_is_compatible("PowerBook5,5")) {
1520
1521 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1522 } else if (of_machine_is_compatible("PowerBook5,6")) {
1523
1524 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1525 } else if (of_machine_is_compatible("PowerBook5,7") ||
1526 of_machine_is_compatible("PowerBook5,8") ||
1527 of_machine_is_compatible("PowerBook5,9")) {
1528
1529
1530 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1531 } else if (of_machine_is_compatible("PowerBook4,1") ||
1532 of_machine_is_compatible("PowerBook4,2") ||
1533 of_machine_is_compatible("PowerBook4,3") ||
1534 of_machine_is_compatible("PowerBook6,3") ||
1535 of_machine_is_compatible("PowerBook6,5") ||
1536 of_machine_is_compatible("PowerBook6,7")) {
1537
1538 rdev->mode_info.connector_table = CT_IBOOK;
1539 } else if (of_machine_is_compatible("PowerMac4,4")) {
1540
1541 rdev->mode_info.connector_table = CT_EMAC;
1542 } else if (of_machine_is_compatible("PowerMac10,1")) {
1543
1544 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1545 } else if (of_machine_is_compatible("PowerMac10,2")) {
1546
1547 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1548 } else if (of_machine_is_compatible("PowerMac12,1")) {
1549
1550
1551 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1552 } else if ((rdev->pdev->device == 0x4a48) &&
1553 (rdev->pdev->subsystem_vendor == 0x1002) &&
1554 (rdev->pdev->subsystem_device == 0x4a48)) {
1555
1556 rdev->mode_info.connector_table = CT_MAC_X800;
1557 } else if ((of_machine_is_compatible("PowerMac7,2") ||
1558 of_machine_is_compatible("PowerMac7,3")) &&
1559 (rdev->pdev->device == 0x4150) &&
1560 (rdev->pdev->subsystem_vendor == 0x1002) &&
1561 (rdev->pdev->subsystem_device == 0x4150)) {
1562
1563 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1564 } else if ((rdev->pdev->device == 0x4c66) &&
1565 (rdev->pdev->subsystem_vendor == 0x1002) &&
1566 (rdev->pdev->subsystem_device == 0x4c66)) {
1567
1568 rdev->mode_info.connector_table = CT_SAM440EP;
1569 } else
1570#endif
1571#ifdef CONFIG_PPC64
1572 if (ASIC_IS_RN50(rdev))
1573 rdev->mode_info.connector_table = CT_RN50_POWER;
1574 else
1575#endif
1576 rdev->mode_info.connector_table = CT_GENERIC;
1577 }
1578
1579 switch (rdev->mode_info.connector_table) {
1580 case CT_GENERIC:
1581 DRM_INFO("Connector Table: %d (generic)\n",
1582 rdev->mode_info.connector_table);
1583
1584 if (rdev->flags & RADEON_SINGLE_CRTC) {
1585
1586 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1587 hpd.hpd = RADEON_HPD_NONE;
1588 radeon_add_legacy_encoder(dev,
1589 radeon_get_encoder_enum(dev,
1590 ATOM_DEVICE_CRT1_SUPPORT,
1591 1),
1592 ATOM_DEVICE_CRT1_SUPPORT);
1593 radeon_add_legacy_connector(dev, 0,
1594 ATOM_DEVICE_CRT1_SUPPORT,
1595 DRM_MODE_CONNECTOR_VGA,
1596 &ddc_i2c,
1597 CONNECTOR_OBJECT_ID_VGA,
1598 &hpd);
1599 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1600
1601 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
1602 hpd.hpd = RADEON_HPD_NONE;
1603 radeon_add_legacy_encoder(dev,
1604 radeon_get_encoder_enum(dev,
1605 ATOM_DEVICE_LCD1_SUPPORT,
1606 0),
1607 ATOM_DEVICE_LCD1_SUPPORT);
1608 radeon_add_legacy_connector(dev, 0,
1609 ATOM_DEVICE_LCD1_SUPPORT,
1610 DRM_MODE_CONNECTOR_LVDS,
1611 &ddc_i2c,
1612 CONNECTOR_OBJECT_ID_LVDS,
1613 &hpd);
1614
1615
1616 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1617 hpd.hpd = RADEON_HPD_NONE;
1618 radeon_add_legacy_encoder(dev,
1619 radeon_get_encoder_enum(dev,
1620 ATOM_DEVICE_CRT1_SUPPORT,
1621 1),
1622 ATOM_DEVICE_CRT1_SUPPORT);
1623 radeon_add_legacy_connector(dev, 1,
1624 ATOM_DEVICE_CRT1_SUPPORT,
1625 DRM_MODE_CONNECTOR_VGA,
1626 &ddc_i2c,
1627 CONNECTOR_OBJECT_ID_VGA,
1628 &hpd);
1629 } else {
1630
1631 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1632 hpd.hpd = RADEON_HPD_1;
1633 radeon_add_legacy_encoder(dev,
1634 radeon_get_encoder_enum(dev,
1635 ATOM_DEVICE_DFP1_SUPPORT,
1636 0),
1637 ATOM_DEVICE_DFP1_SUPPORT);
1638 radeon_add_legacy_encoder(dev,
1639 radeon_get_encoder_enum(dev,
1640 ATOM_DEVICE_CRT2_SUPPORT,
1641 2),
1642 ATOM_DEVICE_CRT2_SUPPORT);
1643 radeon_add_legacy_connector(dev, 0,
1644 ATOM_DEVICE_DFP1_SUPPORT |
1645 ATOM_DEVICE_CRT2_SUPPORT,
1646 DRM_MODE_CONNECTOR_DVII,
1647 &ddc_i2c,
1648 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1649 &hpd);
1650
1651
1652 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1653 hpd.hpd = RADEON_HPD_NONE;
1654 radeon_add_legacy_encoder(dev,
1655 radeon_get_encoder_enum(dev,
1656 ATOM_DEVICE_CRT1_SUPPORT,
1657 1),
1658 ATOM_DEVICE_CRT1_SUPPORT);
1659 radeon_add_legacy_connector(dev, 1,
1660 ATOM_DEVICE_CRT1_SUPPORT,
1661 DRM_MODE_CONNECTOR_VGA,
1662 &ddc_i2c,
1663 CONNECTOR_OBJECT_ID_VGA,
1664 &hpd);
1665 }
1666
1667 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1668
1669 ddc_i2c.valid = false;
1670 hpd.hpd = RADEON_HPD_NONE;
1671 radeon_add_legacy_encoder(dev,
1672 radeon_get_encoder_enum(dev,
1673 ATOM_DEVICE_TV1_SUPPORT,
1674 2),
1675 ATOM_DEVICE_TV1_SUPPORT);
1676 radeon_add_legacy_connector(dev, 2,
1677 ATOM_DEVICE_TV1_SUPPORT,
1678 DRM_MODE_CONNECTOR_SVIDEO,
1679 &ddc_i2c,
1680 CONNECTOR_OBJECT_ID_SVIDEO,
1681 &hpd);
1682 }
1683 break;
1684 case CT_IBOOK:
1685 DRM_INFO("Connector Table: %d (ibook)\n",
1686 rdev->mode_info.connector_table);
1687
1688 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1689 hpd.hpd = RADEON_HPD_NONE;
1690 radeon_add_legacy_encoder(dev,
1691 radeon_get_encoder_enum(dev,
1692 ATOM_DEVICE_LCD1_SUPPORT,
1693 0),
1694 ATOM_DEVICE_LCD1_SUPPORT);
1695 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1696 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1697 CONNECTOR_OBJECT_ID_LVDS,
1698 &hpd);
1699
1700 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1701 hpd.hpd = RADEON_HPD_NONE;
1702 radeon_add_legacy_encoder(dev,
1703 radeon_get_encoder_enum(dev,
1704 ATOM_DEVICE_CRT2_SUPPORT,
1705 2),
1706 ATOM_DEVICE_CRT2_SUPPORT);
1707 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1708 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1709 CONNECTOR_OBJECT_ID_VGA,
1710 &hpd);
1711
1712 ddc_i2c.valid = false;
1713 hpd.hpd = RADEON_HPD_NONE;
1714 radeon_add_legacy_encoder(dev,
1715 radeon_get_encoder_enum(dev,
1716 ATOM_DEVICE_TV1_SUPPORT,
1717 2),
1718 ATOM_DEVICE_TV1_SUPPORT);
1719 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1720 DRM_MODE_CONNECTOR_SVIDEO,
1721 &ddc_i2c,
1722 CONNECTOR_OBJECT_ID_SVIDEO,
1723 &hpd);
1724 break;
1725 case CT_POWERBOOK_EXTERNAL:
1726 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1727 rdev->mode_info.connector_table);
1728
1729 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1730 hpd.hpd = RADEON_HPD_NONE;
1731 radeon_add_legacy_encoder(dev,
1732 radeon_get_encoder_enum(dev,
1733 ATOM_DEVICE_LCD1_SUPPORT,
1734 0),
1735 ATOM_DEVICE_LCD1_SUPPORT);
1736 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1737 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1738 CONNECTOR_OBJECT_ID_LVDS,
1739 &hpd);
1740
1741 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1742 hpd.hpd = RADEON_HPD_2;
1743 radeon_add_legacy_encoder(dev,
1744 radeon_get_encoder_enum(dev,
1745 ATOM_DEVICE_DFP2_SUPPORT,
1746 0),
1747 ATOM_DEVICE_DFP2_SUPPORT);
1748 radeon_add_legacy_encoder(dev,
1749 radeon_get_encoder_enum(dev,
1750 ATOM_DEVICE_CRT1_SUPPORT,
1751 1),
1752 ATOM_DEVICE_CRT1_SUPPORT);
1753
1754 radeon_add_legacy_connector(dev, 1,
1755 ATOM_DEVICE_DFP2_SUPPORT |
1756 ATOM_DEVICE_CRT1_SUPPORT,
1757 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1758 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
1759 &hpd);
1760
1761 ddc_i2c.valid = false;
1762 hpd.hpd = RADEON_HPD_NONE;
1763 radeon_add_legacy_encoder(dev,
1764 radeon_get_encoder_enum(dev,
1765 ATOM_DEVICE_TV1_SUPPORT,
1766 2),
1767 ATOM_DEVICE_TV1_SUPPORT);
1768 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1769 DRM_MODE_CONNECTOR_SVIDEO,
1770 &ddc_i2c,
1771 CONNECTOR_OBJECT_ID_SVIDEO,
1772 &hpd);
1773 break;
1774 case CT_POWERBOOK_INTERNAL:
1775 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1776 rdev->mode_info.connector_table);
1777
1778 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1779 hpd.hpd = RADEON_HPD_NONE;
1780 radeon_add_legacy_encoder(dev,
1781 radeon_get_encoder_enum(dev,
1782 ATOM_DEVICE_LCD1_SUPPORT,
1783 0),
1784 ATOM_DEVICE_LCD1_SUPPORT);
1785 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1786 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1787 CONNECTOR_OBJECT_ID_LVDS,
1788 &hpd);
1789
1790 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1791 hpd.hpd = RADEON_HPD_1;
1792 radeon_add_legacy_encoder(dev,
1793 radeon_get_encoder_enum(dev,
1794 ATOM_DEVICE_DFP1_SUPPORT,
1795 0),
1796 ATOM_DEVICE_DFP1_SUPPORT);
1797 radeon_add_legacy_encoder(dev,
1798 radeon_get_encoder_enum(dev,
1799 ATOM_DEVICE_CRT1_SUPPORT,
1800 1),
1801 ATOM_DEVICE_CRT1_SUPPORT);
1802 radeon_add_legacy_connector(dev, 1,
1803 ATOM_DEVICE_DFP1_SUPPORT |
1804 ATOM_DEVICE_CRT1_SUPPORT,
1805 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1806 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1807 &hpd);
1808
1809 ddc_i2c.valid = false;
1810 hpd.hpd = RADEON_HPD_NONE;
1811 radeon_add_legacy_encoder(dev,
1812 radeon_get_encoder_enum(dev,
1813 ATOM_DEVICE_TV1_SUPPORT,
1814 2),
1815 ATOM_DEVICE_TV1_SUPPORT);
1816 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1817 DRM_MODE_CONNECTOR_SVIDEO,
1818 &ddc_i2c,
1819 CONNECTOR_OBJECT_ID_SVIDEO,
1820 &hpd);
1821 break;
1822 case CT_POWERBOOK_VGA:
1823 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1824 rdev->mode_info.connector_table);
1825
1826 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1827 hpd.hpd = RADEON_HPD_NONE;
1828 radeon_add_legacy_encoder(dev,
1829 radeon_get_encoder_enum(dev,
1830 ATOM_DEVICE_LCD1_SUPPORT,
1831 0),
1832 ATOM_DEVICE_LCD1_SUPPORT);
1833 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1834 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1835 CONNECTOR_OBJECT_ID_LVDS,
1836 &hpd);
1837
1838 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1839 hpd.hpd = RADEON_HPD_NONE;
1840 radeon_add_legacy_encoder(dev,
1841 radeon_get_encoder_enum(dev,
1842 ATOM_DEVICE_CRT1_SUPPORT,
1843 1),
1844 ATOM_DEVICE_CRT1_SUPPORT);
1845 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1846 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1847 CONNECTOR_OBJECT_ID_VGA,
1848 &hpd);
1849
1850 ddc_i2c.valid = false;
1851 hpd.hpd = RADEON_HPD_NONE;
1852 radeon_add_legacy_encoder(dev,
1853 radeon_get_encoder_enum(dev,
1854 ATOM_DEVICE_TV1_SUPPORT,
1855 2),
1856 ATOM_DEVICE_TV1_SUPPORT);
1857 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1858 DRM_MODE_CONNECTOR_SVIDEO,
1859 &ddc_i2c,
1860 CONNECTOR_OBJECT_ID_SVIDEO,
1861 &hpd);
1862 break;
1863 case CT_MINI_EXTERNAL:
1864 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1865 rdev->mode_info.connector_table);
1866
1867 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1868 hpd.hpd = RADEON_HPD_2;
1869 radeon_add_legacy_encoder(dev,
1870 radeon_get_encoder_enum(dev,
1871 ATOM_DEVICE_DFP2_SUPPORT,
1872 0),
1873 ATOM_DEVICE_DFP2_SUPPORT);
1874 radeon_add_legacy_encoder(dev,
1875 radeon_get_encoder_enum(dev,
1876 ATOM_DEVICE_CRT2_SUPPORT,
1877 2),
1878 ATOM_DEVICE_CRT2_SUPPORT);
1879
1880 radeon_add_legacy_connector(dev, 0,
1881 ATOM_DEVICE_DFP2_SUPPORT |
1882 ATOM_DEVICE_CRT2_SUPPORT,
1883 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1884 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1885 &hpd);
1886
1887 ddc_i2c.valid = false;
1888 hpd.hpd = RADEON_HPD_NONE;
1889 radeon_add_legacy_encoder(dev,
1890 radeon_get_encoder_enum(dev,
1891 ATOM_DEVICE_TV1_SUPPORT,
1892 2),
1893 ATOM_DEVICE_TV1_SUPPORT);
1894 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1895 DRM_MODE_CONNECTOR_SVIDEO,
1896 &ddc_i2c,
1897 CONNECTOR_OBJECT_ID_SVIDEO,
1898 &hpd);
1899 break;
1900 case CT_MINI_INTERNAL:
1901 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1902 rdev->mode_info.connector_table);
1903
1904 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1905 hpd.hpd = RADEON_HPD_1;
1906 radeon_add_legacy_encoder(dev,
1907 radeon_get_encoder_enum(dev,
1908 ATOM_DEVICE_DFP1_SUPPORT,
1909 0),
1910 ATOM_DEVICE_DFP1_SUPPORT);
1911 radeon_add_legacy_encoder(dev,
1912 radeon_get_encoder_enum(dev,
1913 ATOM_DEVICE_CRT2_SUPPORT,
1914 2),
1915 ATOM_DEVICE_CRT2_SUPPORT);
1916 radeon_add_legacy_connector(dev, 0,
1917 ATOM_DEVICE_DFP1_SUPPORT |
1918 ATOM_DEVICE_CRT2_SUPPORT,
1919 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1920 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
1921 &hpd);
1922
1923 ddc_i2c.valid = false;
1924 hpd.hpd = RADEON_HPD_NONE;
1925 radeon_add_legacy_encoder(dev,
1926 radeon_get_encoder_enum(dev,
1927 ATOM_DEVICE_TV1_SUPPORT,
1928 2),
1929 ATOM_DEVICE_TV1_SUPPORT);
1930 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1931 DRM_MODE_CONNECTOR_SVIDEO,
1932 &ddc_i2c,
1933 CONNECTOR_OBJECT_ID_SVIDEO,
1934 &hpd);
1935 break;
1936 case CT_IMAC_G5_ISIGHT:
1937 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1938 rdev->mode_info.connector_table);
1939
1940 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
1941 hpd.hpd = RADEON_HPD_1;
1942 radeon_add_legacy_encoder(dev,
1943 radeon_get_encoder_enum(dev,
1944 ATOM_DEVICE_DFP1_SUPPORT,
1945 0),
1946 ATOM_DEVICE_DFP1_SUPPORT);
1947 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1948 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1949 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
1950 &hpd);
1951
1952 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
1953 hpd.hpd = RADEON_HPD_NONE;
1954 radeon_add_legacy_encoder(dev,
1955 radeon_get_encoder_enum(dev,
1956 ATOM_DEVICE_CRT2_SUPPORT,
1957 2),
1958 ATOM_DEVICE_CRT2_SUPPORT);
1959 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1960 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1961 CONNECTOR_OBJECT_ID_VGA,
1962 &hpd);
1963
1964 ddc_i2c.valid = false;
1965 hpd.hpd = RADEON_HPD_NONE;
1966 radeon_add_legacy_encoder(dev,
1967 radeon_get_encoder_enum(dev,
1968 ATOM_DEVICE_TV1_SUPPORT,
1969 2),
1970 ATOM_DEVICE_TV1_SUPPORT);
1971 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1972 DRM_MODE_CONNECTOR_SVIDEO,
1973 &ddc_i2c,
1974 CONNECTOR_OBJECT_ID_SVIDEO,
1975 &hpd);
1976 break;
1977 case CT_EMAC:
1978 DRM_INFO("Connector Table: %d (emac)\n",
1979 rdev->mode_info.connector_table);
1980
1981 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
1982 hpd.hpd = RADEON_HPD_NONE;
1983 radeon_add_legacy_encoder(dev,
1984 radeon_get_encoder_enum(dev,
1985 ATOM_DEVICE_CRT1_SUPPORT,
1986 1),
1987 ATOM_DEVICE_CRT1_SUPPORT);
1988 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1989 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1990 CONNECTOR_OBJECT_ID_VGA,
1991 &hpd);
1992
1993 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
1994 hpd.hpd = RADEON_HPD_NONE;
1995 radeon_add_legacy_encoder(dev,
1996 radeon_get_encoder_enum(dev,
1997 ATOM_DEVICE_CRT2_SUPPORT,
1998 2),
1999 ATOM_DEVICE_CRT2_SUPPORT);
2000 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2001 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2002 CONNECTOR_OBJECT_ID_VGA,
2003 &hpd);
2004
2005 ddc_i2c.valid = false;
2006 hpd.hpd = RADEON_HPD_NONE;
2007 radeon_add_legacy_encoder(dev,
2008 radeon_get_encoder_enum(dev,
2009 ATOM_DEVICE_TV1_SUPPORT,
2010 2),
2011 ATOM_DEVICE_TV1_SUPPORT);
2012 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2013 DRM_MODE_CONNECTOR_SVIDEO,
2014 &ddc_i2c,
2015 CONNECTOR_OBJECT_ID_SVIDEO,
2016 &hpd);
2017 break;
2018 case CT_RN50_POWER:
2019 DRM_INFO("Connector Table: %d (rn50-power)\n",
2020 rdev->mode_info.connector_table);
2021
2022 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2023 hpd.hpd = RADEON_HPD_NONE;
2024 radeon_add_legacy_encoder(dev,
2025 radeon_get_encoder_enum(dev,
2026 ATOM_DEVICE_CRT1_SUPPORT,
2027 1),
2028 ATOM_DEVICE_CRT1_SUPPORT);
2029 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
2030 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2031 CONNECTOR_OBJECT_ID_VGA,
2032 &hpd);
2033 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
2034 hpd.hpd = RADEON_HPD_NONE;
2035 radeon_add_legacy_encoder(dev,
2036 radeon_get_encoder_enum(dev,
2037 ATOM_DEVICE_CRT2_SUPPORT,
2038 2),
2039 ATOM_DEVICE_CRT2_SUPPORT);
2040 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
2041 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2042 CONNECTOR_OBJECT_ID_VGA,
2043 &hpd);
2044 break;
2045 case CT_MAC_X800:
2046 DRM_INFO("Connector Table: %d (mac x800)\n",
2047 rdev->mode_info.connector_table);
2048
2049 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2050 hpd.hpd = RADEON_HPD_1;
2051 radeon_add_legacy_encoder(dev,
2052 radeon_get_encoder_enum(dev,
2053 ATOM_DEVICE_DFP1_SUPPORT,
2054 0),
2055 ATOM_DEVICE_DFP1_SUPPORT);
2056 radeon_add_legacy_encoder(dev,
2057 radeon_get_encoder_enum(dev,
2058 ATOM_DEVICE_CRT1_SUPPORT,
2059 1),
2060 ATOM_DEVICE_CRT1_SUPPORT);
2061 radeon_add_legacy_connector(dev, 0,
2062 ATOM_DEVICE_DFP1_SUPPORT |
2063 ATOM_DEVICE_CRT1_SUPPORT,
2064 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2065 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2066 &hpd);
2067
2068 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2069 hpd.hpd = RADEON_HPD_2;
2070 radeon_add_legacy_encoder(dev,
2071 radeon_get_encoder_enum(dev,
2072 ATOM_DEVICE_DFP2_SUPPORT,
2073 0),
2074 ATOM_DEVICE_DFP2_SUPPORT);
2075 radeon_add_legacy_encoder(dev,
2076 radeon_get_encoder_enum(dev,
2077 ATOM_DEVICE_CRT2_SUPPORT,
2078 2),
2079 ATOM_DEVICE_CRT2_SUPPORT);
2080 radeon_add_legacy_connector(dev, 1,
2081 ATOM_DEVICE_DFP2_SUPPORT |
2082 ATOM_DEVICE_CRT2_SUPPORT,
2083 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2084 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
2085 &hpd);
2086 break;
2087 case CT_MAC_G5_9600:
2088 DRM_INFO("Connector Table: %d (mac g5 9600)\n",
2089 rdev->mode_info.connector_table);
2090
2091 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2092 hpd.hpd = RADEON_HPD_1;
2093 radeon_add_legacy_encoder(dev,
2094 radeon_get_encoder_enum(dev,
2095 ATOM_DEVICE_DFP2_SUPPORT,
2096 0),
2097 ATOM_DEVICE_DFP2_SUPPORT);
2098 radeon_add_legacy_encoder(dev,
2099 radeon_get_encoder_enum(dev,
2100 ATOM_DEVICE_CRT2_SUPPORT,
2101 2),
2102 ATOM_DEVICE_CRT2_SUPPORT);
2103 radeon_add_legacy_connector(dev, 0,
2104 ATOM_DEVICE_DFP2_SUPPORT |
2105 ATOM_DEVICE_CRT2_SUPPORT,
2106 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2107 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2108 &hpd);
2109
2110 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2111 hpd.hpd = RADEON_HPD_2;
2112 radeon_add_legacy_encoder(dev,
2113 radeon_get_encoder_enum(dev,
2114 ATOM_DEVICE_DFP1_SUPPORT,
2115 0),
2116 ATOM_DEVICE_DFP1_SUPPORT);
2117 radeon_add_legacy_encoder(dev,
2118 radeon_get_encoder_enum(dev,
2119 ATOM_DEVICE_CRT1_SUPPORT,
2120 1),
2121 ATOM_DEVICE_CRT1_SUPPORT);
2122 radeon_add_legacy_connector(dev, 1,
2123 ATOM_DEVICE_DFP1_SUPPORT |
2124 ATOM_DEVICE_CRT1_SUPPORT,
2125 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2126 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2127 &hpd);
2128
2129 ddc_i2c.valid = false;
2130 hpd.hpd = RADEON_HPD_NONE;
2131 radeon_add_legacy_encoder(dev,
2132 radeon_get_encoder_enum(dev,
2133 ATOM_DEVICE_TV1_SUPPORT,
2134 2),
2135 ATOM_DEVICE_TV1_SUPPORT);
2136 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
2137 DRM_MODE_CONNECTOR_SVIDEO,
2138 &ddc_i2c,
2139 CONNECTOR_OBJECT_ID_SVIDEO,
2140 &hpd);
2141 break;
2142 case CT_SAM440EP:
2143 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",
2144 rdev->mode_info.connector_table);
2145
2146 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);
2147 hpd.hpd = RADEON_HPD_NONE;
2148 radeon_add_legacy_encoder(dev,
2149 radeon_get_encoder_enum(dev,
2150 ATOM_DEVICE_LCD1_SUPPORT,
2151 0),
2152 ATOM_DEVICE_LCD1_SUPPORT);
2153 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
2154 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
2155 CONNECTOR_OBJECT_ID_LVDS,
2156 &hpd);
2157
2158 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2159 hpd.hpd = RADEON_HPD_1;
2160 radeon_add_legacy_encoder(dev,
2161 radeon_get_encoder_enum(dev,
2162 ATOM_DEVICE_DFP1_SUPPORT,
2163 0),
2164 ATOM_DEVICE_DFP1_SUPPORT);
2165 radeon_add_legacy_encoder(dev,
2166 radeon_get_encoder_enum(dev,
2167 ATOM_DEVICE_CRT2_SUPPORT,
2168 2),
2169 ATOM_DEVICE_CRT2_SUPPORT);
2170 radeon_add_legacy_connector(dev, 1,
2171 ATOM_DEVICE_DFP1_SUPPORT |
2172 ATOM_DEVICE_CRT2_SUPPORT,
2173 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
2174 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2175 &hpd);
2176
2177 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2178 hpd.hpd = RADEON_HPD_NONE;
2179 radeon_add_legacy_encoder(dev,
2180 radeon_get_encoder_enum(dev,
2181 ATOM_DEVICE_CRT1_SUPPORT,
2182 1),
2183 ATOM_DEVICE_CRT1_SUPPORT);
2184 radeon_add_legacy_connector(dev, 2,
2185 ATOM_DEVICE_CRT1_SUPPORT,
2186 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
2187 CONNECTOR_OBJECT_ID_VGA,
2188 &hpd);
2189
2190 ddc_i2c.valid = false;
2191 hpd.hpd = RADEON_HPD_NONE;
2192 radeon_add_legacy_encoder(dev,
2193 radeon_get_encoder_enum(dev,
2194 ATOM_DEVICE_TV1_SUPPORT,
2195 2),
2196 ATOM_DEVICE_TV1_SUPPORT);
2197 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,
2198 DRM_MODE_CONNECTOR_SVIDEO,
2199 &ddc_i2c,
2200 CONNECTOR_OBJECT_ID_SVIDEO,
2201 &hpd);
2202 break;
2203 default:
2204 DRM_INFO("Connector table: %d (invalid)\n",
2205 rdev->mode_info.connector_table);
2206 return false;
2207 }
2208
2209 radeon_link_encoder_connector(dev);
2210
2211 return true;
2212}
2213
2214static bool radeon_apply_legacy_quirks(struct drm_device *dev,
2215 int bios_index,
2216 enum radeon_combios_connector
2217 *legacy_connector,
2218 struct radeon_i2c_bus_rec *ddc_i2c,
2219 struct radeon_hpd *hpd)
2220{
2221
2222
2223
2224 if (dev->pdev->device == 0x515e &&
2225 dev->pdev->subsystem_vendor == 0x1014) {
2226 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
2227 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2228 return false;
2229 }
2230
2231
2232 if (dev->pdev->device == 0x5B60 &&
2233 dev->pdev->subsystem_vendor == 0x17af &&
2234 dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2235 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
2236 return false;
2237 }
2238
2239 return true;
2240}
2241
2242static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
2243{
2244
2245 if (dev->pdev->device == 0x5975 &&
2246 dev->pdev->subsystem_vendor == 0x1025 &&
2247 dev->pdev->subsystem_device == 0x009f)
2248 return false;
2249
2250
2251 if (dev->pdev->device == 0x5974 &&
2252 dev->pdev->subsystem_vendor == 0x103c &&
2253 dev->pdev->subsystem_device == 0x280a)
2254 return false;
2255
2256
2257 if (dev->pdev->device == 0x5955 &&
2258 dev->pdev->subsystem_vendor == 0x1462 &&
2259 dev->pdev->subsystem_device == 0x0131)
2260 return false;
2261
2262 return true;
2263}
2264
2265static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
2266{
2267 struct radeon_device *rdev = dev->dev_private;
2268 uint32_t ext_tmds_info;
2269
2270 if (rdev->flags & RADEON_IS_IGP) {
2271 if (is_dvi_d)
2272 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2273 else
2274 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2275 }
2276 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2277 if (ext_tmds_info) {
2278 uint8_t rev = RBIOS8(ext_tmds_info);
2279 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
2280 if (rev >= 3) {
2281 if (is_dvi_d)
2282 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2283 else
2284 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2285 } else {
2286 if (flags & 1) {
2287 if (is_dvi_d)
2288 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
2289 else
2290 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
2291 }
2292 }
2293 }
2294 if (is_dvi_d)
2295 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
2296 else
2297 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2298}
2299
2300bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
2301{
2302 struct radeon_device *rdev = dev->dev_private;
2303 uint32_t conn_info, entry, devices;
2304 uint16_t tmp, connector_object_id;
2305 enum radeon_combios_ddc ddc_type;
2306 enum radeon_combios_connector connector;
2307 int i = 0;
2308 struct radeon_i2c_bus_rec ddc_i2c;
2309 struct radeon_hpd hpd;
2310
2311 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
2312 if (conn_info) {
2313 for (i = 0; i < 4; i++) {
2314 entry = conn_info + 2 + i * 2;
2315
2316 if (!RBIOS16(entry))
2317 break;
2318
2319 tmp = RBIOS16(entry);
2320
2321 connector = (tmp >> 12) & 0xf;
2322
2323 ddc_type = (tmp >> 8) & 0xf;
2324 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2325
2326 switch (connector) {
2327 case CONNECTOR_PROPRIETARY_LEGACY:
2328 case CONNECTOR_DVI_I_LEGACY:
2329 case CONNECTOR_DVI_D_LEGACY:
2330 if ((tmp >> 4) & 0x1)
2331 hpd.hpd = RADEON_HPD_2;
2332 else
2333 hpd.hpd = RADEON_HPD_1;
2334 break;
2335 default:
2336 hpd.hpd = RADEON_HPD_NONE;
2337 break;
2338 }
2339
2340 if (!radeon_apply_legacy_quirks(dev, i, &connector,
2341 &ddc_i2c, &hpd))
2342 continue;
2343
2344 switch (connector) {
2345 case CONNECTOR_PROPRIETARY_LEGACY:
2346 if ((tmp >> 4) & 0x1)
2347 devices = ATOM_DEVICE_DFP2_SUPPORT;
2348 else
2349 devices = ATOM_DEVICE_DFP1_SUPPORT;
2350 radeon_add_legacy_encoder(dev,
2351 radeon_get_encoder_enum
2352 (dev, devices, 0),
2353 devices);
2354 radeon_add_legacy_connector(dev, i, devices,
2355 legacy_connector_convert
2356 [connector],
2357 &ddc_i2c,
2358 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,
2359 &hpd);
2360 break;
2361 case CONNECTOR_CRT_LEGACY:
2362 if (tmp & 0x1) {
2363 devices = ATOM_DEVICE_CRT2_SUPPORT;
2364 radeon_add_legacy_encoder(dev,
2365 radeon_get_encoder_enum
2366 (dev,
2367 ATOM_DEVICE_CRT2_SUPPORT,
2368 2),
2369 ATOM_DEVICE_CRT2_SUPPORT);
2370 } else {
2371 devices = ATOM_DEVICE_CRT1_SUPPORT;
2372 radeon_add_legacy_encoder(dev,
2373 radeon_get_encoder_enum
2374 (dev,
2375 ATOM_DEVICE_CRT1_SUPPORT,
2376 1),
2377 ATOM_DEVICE_CRT1_SUPPORT);
2378 }
2379 radeon_add_legacy_connector(dev,
2380 i,
2381 devices,
2382 legacy_connector_convert
2383 [connector],
2384 &ddc_i2c,
2385 CONNECTOR_OBJECT_ID_VGA,
2386 &hpd);
2387 break;
2388 case CONNECTOR_DVI_I_LEGACY:
2389 devices = 0;
2390 if (tmp & 0x1) {
2391 devices |= ATOM_DEVICE_CRT2_SUPPORT;
2392 radeon_add_legacy_encoder(dev,
2393 radeon_get_encoder_enum
2394 (dev,
2395 ATOM_DEVICE_CRT2_SUPPORT,
2396 2),
2397 ATOM_DEVICE_CRT2_SUPPORT);
2398 } else {
2399 devices |= ATOM_DEVICE_CRT1_SUPPORT;
2400 radeon_add_legacy_encoder(dev,
2401 radeon_get_encoder_enum
2402 (dev,
2403 ATOM_DEVICE_CRT1_SUPPORT,
2404 1),
2405 ATOM_DEVICE_CRT1_SUPPORT);
2406 }
2407 if ((tmp >> 4) & 0x1) {
2408 devices |= ATOM_DEVICE_DFP2_SUPPORT;
2409 radeon_add_legacy_encoder(dev,
2410 radeon_get_encoder_enum
2411 (dev,
2412 ATOM_DEVICE_DFP2_SUPPORT,
2413 0),
2414 ATOM_DEVICE_DFP2_SUPPORT);
2415 connector_object_id = combios_check_dl_dvi(dev, 0);
2416 } else {
2417 devices |= ATOM_DEVICE_DFP1_SUPPORT;
2418 radeon_add_legacy_encoder(dev,
2419 radeon_get_encoder_enum
2420 (dev,
2421 ATOM_DEVICE_DFP1_SUPPORT,
2422 0),
2423 ATOM_DEVICE_DFP1_SUPPORT);
2424 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2425 }
2426 radeon_add_legacy_connector(dev,
2427 i,
2428 devices,
2429 legacy_connector_convert
2430 [connector],
2431 &ddc_i2c,
2432 connector_object_id,
2433 &hpd);
2434 break;
2435 case CONNECTOR_DVI_D_LEGACY:
2436 if ((tmp >> 4) & 0x1) {
2437 devices = ATOM_DEVICE_DFP2_SUPPORT;
2438 connector_object_id = combios_check_dl_dvi(dev, 1);
2439 } else {
2440 devices = ATOM_DEVICE_DFP1_SUPPORT;
2441 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
2442 }
2443 radeon_add_legacy_encoder(dev,
2444 radeon_get_encoder_enum
2445 (dev, devices, 0),
2446 devices);
2447 radeon_add_legacy_connector(dev, i, devices,
2448 legacy_connector_convert
2449 [connector],
2450 &ddc_i2c,
2451 connector_object_id,
2452 &hpd);
2453 break;
2454 case CONNECTOR_CTV_LEGACY:
2455 case CONNECTOR_STV_LEGACY:
2456 radeon_add_legacy_encoder(dev,
2457 radeon_get_encoder_enum
2458 (dev,
2459 ATOM_DEVICE_TV1_SUPPORT,
2460 2),
2461 ATOM_DEVICE_TV1_SUPPORT);
2462 radeon_add_legacy_connector(dev, i,
2463 ATOM_DEVICE_TV1_SUPPORT,
2464 legacy_connector_convert
2465 [connector],
2466 &ddc_i2c,
2467 CONNECTOR_OBJECT_ID_SVIDEO,
2468 &hpd);
2469 break;
2470 default:
2471 DRM_ERROR("Unknown connector type: %d\n",
2472 connector);
2473 continue;
2474 }
2475
2476 }
2477 } else {
2478 uint16_t tmds_info =
2479 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
2480 if (tmds_info) {
2481 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");
2482
2483 radeon_add_legacy_encoder(dev,
2484 radeon_get_encoder_enum(dev,
2485 ATOM_DEVICE_CRT1_SUPPORT,
2486 1),
2487 ATOM_DEVICE_CRT1_SUPPORT);
2488 radeon_add_legacy_encoder(dev,
2489 radeon_get_encoder_enum(dev,
2490 ATOM_DEVICE_DFP1_SUPPORT,
2491 0),
2492 ATOM_DEVICE_DFP1_SUPPORT);
2493
2494 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
2495 hpd.hpd = RADEON_HPD_1;
2496 radeon_add_legacy_connector(dev,
2497 0,
2498 ATOM_DEVICE_CRT1_SUPPORT |
2499 ATOM_DEVICE_DFP1_SUPPORT,
2500 DRM_MODE_CONNECTOR_DVII,
2501 &ddc_i2c,
2502 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
2503 &hpd);
2504 } else {
2505 uint16_t crt_info =
2506 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
2507 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");
2508 if (crt_info) {
2509 radeon_add_legacy_encoder(dev,
2510 radeon_get_encoder_enum(dev,
2511 ATOM_DEVICE_CRT1_SUPPORT,
2512 1),
2513 ATOM_DEVICE_CRT1_SUPPORT);
2514 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
2515 hpd.hpd = RADEON_HPD_NONE;
2516 radeon_add_legacy_connector(dev,
2517 0,
2518 ATOM_DEVICE_CRT1_SUPPORT,
2519 DRM_MODE_CONNECTOR_VGA,
2520 &ddc_i2c,
2521 CONNECTOR_OBJECT_ID_VGA,
2522 &hpd);
2523 } else {
2524 DRM_DEBUG_KMS("No connector info found\n");
2525 return false;
2526 }
2527 }
2528 }
2529
2530 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2531 uint16_t lcd_info =
2532 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
2533 if (lcd_info) {
2534 uint16_t lcd_ddc_info =
2535 combios_get_table_offset(dev,
2536 COMBIOS_LCD_DDC_INFO_TABLE);
2537
2538 radeon_add_legacy_encoder(dev,
2539 radeon_get_encoder_enum(dev,
2540 ATOM_DEVICE_LCD1_SUPPORT,
2541 0),
2542 ATOM_DEVICE_LCD1_SUPPORT);
2543
2544 if (lcd_ddc_info) {
2545 ddc_type = RBIOS8(lcd_ddc_info + 2);
2546 switch (ddc_type) {
2547 case DDC_LCD:
2548 ddc_i2c =
2549 combios_setup_i2c_bus(rdev,
2550 DDC_LCD,
2551 RBIOS32(lcd_ddc_info + 3),
2552 RBIOS32(lcd_ddc_info + 7));
2553 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2554 break;
2555 case DDC_GPIO:
2556 ddc_i2c =
2557 combios_setup_i2c_bus(rdev,
2558 DDC_GPIO,
2559 RBIOS32(lcd_ddc_info + 3),
2560 RBIOS32(lcd_ddc_info + 7));
2561 radeon_i2c_add(rdev, &ddc_i2c, "LCD");
2562 break;
2563 default:
2564 ddc_i2c =
2565 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);
2566 break;
2567 }
2568 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");
2569 } else
2570 ddc_i2c.valid = false;
2571
2572 hpd.hpd = RADEON_HPD_NONE;
2573 radeon_add_legacy_connector(dev,
2574 5,
2575 ATOM_DEVICE_LCD1_SUPPORT,
2576 DRM_MODE_CONNECTOR_LVDS,
2577 &ddc_i2c,
2578 CONNECTOR_OBJECT_ID_LVDS,
2579 &hpd);
2580 }
2581 }
2582
2583
2584 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2585 uint32_t tv_info =
2586 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
2587 if (tv_info) {
2588 if (RBIOS8(tv_info + 6) == 'T') {
2589 if (radeon_apply_legacy_tv_quirks(dev)) {
2590 hpd.hpd = RADEON_HPD_NONE;
2591 ddc_i2c.valid = false;
2592 radeon_add_legacy_encoder(dev,
2593 radeon_get_encoder_enum
2594 (dev,
2595 ATOM_DEVICE_TV1_SUPPORT,
2596 2),
2597 ATOM_DEVICE_TV1_SUPPORT);
2598 radeon_add_legacy_connector(dev, 6,
2599 ATOM_DEVICE_TV1_SUPPORT,
2600 DRM_MODE_CONNECTOR_SVIDEO,
2601 &ddc_i2c,
2602 CONNECTOR_OBJECT_ID_SVIDEO,
2603 &hpd);
2604 }
2605 }
2606 }
2607 }
2608
2609 radeon_link_encoder_connector(dev);
2610
2611 return true;
2612}
2613
2614static const char *thermal_controller_names[] = {
2615 "NONE",
2616 "lm63",
2617 "adm1032",
2618};
2619
2620void radeon_combios_get_power_modes(struct radeon_device *rdev)
2621{
2622 struct drm_device *dev = rdev->ddev;
2623 u16 offset, misc, misc2 = 0;
2624 u8 rev, blocks, tmp;
2625 int state_index = 0;
2626 struct radeon_i2c_bus_rec i2c_bus;
2627
2628 rdev->pm.default_power_state_index = -1;
2629
2630
2631 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
2632 if (rdev->pm.power_state) {
2633
2634 rdev->pm.power_state[0].clock_info =
2635 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2636 rdev->pm.power_state[1].clock_info =
2637 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2638 if (!rdev->pm.power_state[0].clock_info ||
2639 !rdev->pm.power_state[1].clock_info)
2640 goto pm_failed;
2641 } else
2642 goto pm_failed;
2643
2644
2645 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
2646 if (offset) {
2647 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
2648
2649 rev = RBIOS8(offset);
2650
2651 if (rev == 0) {
2652 thermal_controller = RBIOS8(offset + 3);
2653 gpio = RBIOS8(offset + 4) & 0x3f;
2654 i2c_addr = RBIOS8(offset + 5);
2655 } else if (rev == 1) {
2656 thermal_controller = RBIOS8(offset + 4);
2657 gpio = RBIOS8(offset + 5) & 0x3f;
2658 i2c_addr = RBIOS8(offset + 6);
2659 } else if (rev == 2) {
2660 thermal_controller = RBIOS8(offset + 4);
2661 gpio = RBIOS8(offset + 5) & 0x3f;
2662 i2c_addr = RBIOS8(offset + 6);
2663 clk_bit = RBIOS8(offset + 0xa);
2664 data_bit = RBIOS8(offset + 0xb);
2665 }
2666 if ((thermal_controller > 0) && (thermal_controller < 3)) {
2667 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2668 thermal_controller_names[thermal_controller],
2669 i2c_addr >> 1);
2670 if (gpio == DDC_LCD) {
2671
2672 i2c_bus.valid = true;
2673 i2c_bus.hw_capable = true;
2674 i2c_bus.mm_i2c = true;
2675 i2c_bus.i2c_id = 0xa0;
2676 } else if (gpio == DDC_GPIO)
2677 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
2678 else
2679 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
2680 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2681 if (rdev->pm.i2c_bus) {
2682 struct i2c_board_info info = { };
2683 const char *name = thermal_controller_names[thermal_controller];
2684 info.addr = i2c_addr >> 1;
2685 strlcpy(info.type, name, sizeof(info.type));
2686 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2687 }
2688 }
2689 } else {
2690
2691
2692
2693 if ((dev->pdev->device == 0x4152) &&
2694 (dev->pdev->subsystem_vendor == 0x1043) &&
2695 (dev->pdev->subsystem_device == 0xc002)) {
2696 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
2697 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2698 if (rdev->pm.i2c_bus) {
2699 struct i2c_board_info info = { };
2700 const char *name = "f75375";
2701 info.addr = 0x28;
2702 strlcpy(info.type, name, sizeof(info.type));
2703 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
2704 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2705 name, info.addr);
2706 }
2707 }
2708 }
2709
2710 if (rdev->flags & RADEON_IS_MOBILITY) {
2711 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
2712 if (offset) {
2713 rev = RBIOS8(offset);
2714 blocks = RBIOS8(offset + 0x2);
2715
2716 rdev->pm.power_state[state_index].num_clock_modes = 1;
2717 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2718 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2719 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2720 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2721 goto default_mode;
2722 rdev->pm.power_state[state_index].type =
2723 POWER_STATE_TYPE_BATTERY;
2724 misc = RBIOS16(offset + 0x5 + 0x0);
2725 if (rev > 4)
2726 misc2 = RBIOS16(offset + 0x5 + 0xe);
2727 rdev->pm.power_state[state_index].misc = misc;
2728 rdev->pm.power_state[state_index].misc2 = misc2;
2729 if (misc & 0x4) {
2730 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2731 if (misc & 0x8)
2732 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2733 true;
2734 else
2735 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2736 false;
2737 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2738 if (rev < 6) {
2739 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2740 RBIOS16(offset + 0x5 + 0xb) * 4;
2741 tmp = RBIOS8(offset + 0x5 + 0xd);
2742 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2743 } else {
2744 u8 entries = RBIOS8(offset + 0x5 + 0xb);
2745 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);
2746 if (entries && voltage_table_offset) {
2747 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2748 RBIOS16(voltage_table_offset) * 4;
2749 tmp = RBIOS8(voltage_table_offset + 0x2);
2750 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2751 } else
2752 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2753 }
2754 switch ((misc2 & 0x700) >> 8) {
2755 case 0:
2756 default:
2757 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2758 break;
2759 case 1:
2760 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2761 break;
2762 case 2:
2763 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2764 break;
2765 case 3:
2766 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2767 break;
2768 case 4:
2769 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2770 break;
2771 }
2772 } else
2773 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2774 if (rev > 6)
2775 rdev->pm.power_state[state_index].pcie_lanes =
2776 RBIOS8(offset + 0x5 + 0x10);
2777 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2778 state_index++;
2779 } else {
2780
2781 }
2782 } else {
2783
2784 }
2785
2786default_mode:
2787
2788 rdev->pm.power_state[state_index].type =
2789 POWER_STATE_TYPE_DEFAULT;
2790 rdev->pm.power_state[state_index].num_clock_modes = 1;
2791 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2792 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2793 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2794 if ((state_index > 0) &&
2795 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2796 rdev->pm.power_state[state_index].clock_info[0].voltage =
2797 rdev->pm.power_state[0].clock_info[0].voltage;
2798 else
2799 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2800 rdev->pm.power_state[state_index].pcie_lanes = 16;
2801 rdev->pm.power_state[state_index].flags = 0;
2802 rdev->pm.default_power_state_index = state_index;
2803 rdev->pm.num_power_states = state_index + 1;
2804
2805 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2806 rdev->pm.current_clock_mode_index = 0;
2807 return;
2808
2809pm_failed:
2810 rdev->pm.default_power_state_index = state_index;
2811 rdev->pm.num_power_states = 0;
2812
2813 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2814 rdev->pm.current_clock_mode_index = 0;
2815}
2816
2817void radeon_external_tmds_setup(struct drm_encoder *encoder)
2818{
2819 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2820 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2821
2822 if (!tmds)
2823 return;
2824
2825 switch (tmds->dvo_chip) {
2826 case DVO_SIL164:
2827
2828 radeon_i2c_put_byte(tmds->i2c_bus,
2829 tmds->slave_addr,
2830 0x08, 0x30);
2831 radeon_i2c_put_byte(tmds->i2c_bus,
2832 tmds->slave_addr,
2833 0x09, 0x00);
2834 radeon_i2c_put_byte(tmds->i2c_bus,
2835 tmds->slave_addr,
2836 0x0a, 0x90);
2837 radeon_i2c_put_byte(tmds->i2c_bus,
2838 tmds->slave_addr,
2839 0x0c, 0x89);
2840 radeon_i2c_put_byte(tmds->i2c_bus,
2841 tmds->slave_addr,
2842 0x08, 0x3b);
2843 break;
2844 case DVO_SIL1178:
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857 break;
2858 default:
2859 break;
2860 }
2861
2862}
2863
2864bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2865{
2866 struct drm_device *dev = encoder->dev;
2867 struct radeon_device *rdev = dev->dev_private;
2868 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2869 uint16_t offset;
2870 uint8_t blocks, slave_addr, rev;
2871 uint32_t index, id;
2872 uint32_t reg, val, and_mask, or_mask;
2873 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2874
2875 if (!tmds)
2876 return false;
2877
2878 if (rdev->flags & RADEON_IS_IGP) {
2879 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);
2880 rev = RBIOS8(offset);
2881 if (offset) {
2882 rev = RBIOS8(offset);
2883 if (rev > 1) {
2884 blocks = RBIOS8(offset + 3);
2885 index = offset + 4;
2886 while (blocks > 0) {
2887 id = RBIOS16(index);
2888 index += 2;
2889 switch (id >> 13) {
2890 case 0:
2891 reg = (id & 0x1fff) * 4;
2892 val = RBIOS32(index);
2893 index += 4;
2894 WREG32(reg, val);
2895 break;
2896 case 2:
2897 reg = (id & 0x1fff) * 4;
2898 and_mask = RBIOS32(index);
2899 index += 4;
2900 or_mask = RBIOS32(index);
2901 index += 4;
2902 val = RREG32(reg);
2903 val = (val & and_mask) | or_mask;
2904 WREG32(reg, val);
2905 break;
2906 case 3:
2907 val = RBIOS16(index);
2908 index += 2;
2909 udelay(val);
2910 break;
2911 case 4:
2912 val = RBIOS16(index);
2913 index += 2;
2914 mdelay(val);
2915 break;
2916 case 6:
2917 slave_addr = id & 0xff;
2918 slave_addr >>= 1;
2919 index++;
2920 reg = RBIOS8(index);
2921 index++;
2922 val = RBIOS8(index);
2923 index++;
2924 radeon_i2c_put_byte(tmds->i2c_bus,
2925 slave_addr,
2926 reg, val);
2927 break;
2928 default:
2929 DRM_ERROR("Unknown id %d\n", id >> 13);
2930 break;
2931 }
2932 blocks--;
2933 }
2934 return true;
2935 }
2936 }
2937 } else {
2938 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
2939 if (offset) {
2940 index = offset + 10;
2941 id = RBIOS16(index);
2942 while (id != 0xffff) {
2943 index += 2;
2944 switch (id >> 13) {
2945 case 0:
2946 reg = (id & 0x1fff) * 4;
2947 val = RBIOS32(index);
2948 WREG32(reg, val);
2949 break;
2950 case 2:
2951 reg = (id & 0x1fff) * 4;
2952 and_mask = RBIOS32(index);
2953 index += 4;
2954 or_mask = RBIOS32(index);
2955 index += 4;
2956 val = RREG32(reg);
2957 val = (val & and_mask) | or_mask;
2958 WREG32(reg, val);
2959 break;
2960 case 4:
2961 val = RBIOS16(index);
2962 index += 2;
2963 udelay(val);
2964 break;
2965 case 5:
2966 reg = id & 0x1fff;
2967 and_mask = RBIOS32(index);
2968 index += 4;
2969 or_mask = RBIOS32(index);
2970 index += 4;
2971 val = RREG32_PLL(reg);
2972 val = (val & and_mask) | or_mask;
2973 WREG32_PLL(reg, val);
2974 break;
2975 case 6:
2976 reg = id & 0x1fff;
2977 val = RBIOS8(index);
2978 index += 1;
2979 radeon_i2c_put_byte(tmds->i2c_bus,
2980 tmds->slave_addr,
2981 reg, val);
2982 break;
2983 default:
2984 DRM_ERROR("Unknown id %d\n", id >> 13);
2985 break;
2986 }
2987 id = RBIOS16(index);
2988 }
2989 return true;
2990 }
2991 }
2992 return false;
2993}
2994
2995static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
2996{
2997 struct radeon_device *rdev = dev->dev_private;
2998
2999 if (offset) {
3000 while (RBIOS16(offset)) {
3001 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
3002 uint32_t addr = (RBIOS16(offset) & 0x1fff);
3003 uint32_t val, and_mask, or_mask;
3004 uint32_t tmp;
3005
3006 offset += 2;
3007 switch (cmd) {
3008 case 0:
3009 val = RBIOS32(offset);
3010 offset += 4;
3011 WREG32(addr, val);
3012 break;
3013 case 1:
3014 val = RBIOS32(offset);
3015 offset += 4;
3016 WREG32(addr, val);
3017 break;
3018 case 2:
3019 and_mask = RBIOS32(offset);
3020 offset += 4;
3021 or_mask = RBIOS32(offset);
3022 offset += 4;
3023 tmp = RREG32(addr);
3024 tmp &= and_mask;
3025 tmp |= or_mask;
3026 WREG32(addr, tmp);
3027 break;
3028 case 3:
3029 and_mask = RBIOS32(offset);
3030 offset += 4;
3031 or_mask = RBIOS32(offset);
3032 offset += 4;
3033 tmp = RREG32(addr);
3034 tmp &= and_mask;
3035 tmp |= or_mask;
3036 WREG32(addr, tmp);
3037 break;
3038 case 4:
3039 val = RBIOS16(offset);
3040 offset += 2;
3041 udelay(val);
3042 break;
3043 case 5:
3044 val = RBIOS16(offset);
3045 offset += 2;
3046 switch (addr) {
3047 case 8:
3048 while (val--) {
3049 if (!
3050 (RREG32_PLL
3051 (RADEON_CLK_PWRMGT_CNTL) &
3052 RADEON_MC_BUSY))
3053 break;
3054 }
3055 break;
3056 case 9:
3057 while (val--) {
3058 if ((RREG32(RADEON_MC_STATUS) &
3059 RADEON_MC_IDLE))
3060 break;
3061 }
3062 break;
3063 default:
3064 break;
3065 }
3066 break;
3067 default:
3068 break;
3069 }
3070 }
3071 }
3072}
3073
3074static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
3075{
3076 struct radeon_device *rdev = dev->dev_private;
3077
3078 if (offset) {
3079 while (RBIOS8(offset)) {
3080 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
3081 uint8_t addr = (RBIOS8(offset) & 0x3f);
3082 uint32_t val, shift, tmp;
3083 uint32_t and_mask, or_mask;
3084
3085 offset++;
3086 switch (cmd) {
3087 case 0:
3088 val = RBIOS32(offset);
3089 offset += 4;
3090 WREG32_PLL(addr, val);
3091 break;
3092 case 1:
3093 shift = RBIOS8(offset) * 8;
3094 offset++;
3095 and_mask = RBIOS8(offset) << shift;
3096 and_mask |= ~(0xff << shift);
3097 offset++;
3098 or_mask = RBIOS8(offset) << shift;
3099 offset++;
3100 tmp = RREG32_PLL(addr);
3101 tmp &= and_mask;
3102 tmp |= or_mask;
3103 WREG32_PLL(addr, tmp);
3104 break;
3105 case 2:
3106 case 3:
3107 tmp = 1000;
3108 switch (addr) {
3109 case 1:
3110 udelay(150);
3111 break;
3112 case 2:
3113 mdelay(1);
3114 break;
3115 case 3:
3116 while (tmp--) {
3117 if (!
3118 (RREG32_PLL
3119 (RADEON_CLK_PWRMGT_CNTL) &
3120 RADEON_MC_BUSY))
3121 break;
3122 }
3123 break;
3124 case 4:
3125 while (tmp--) {
3126 if (RREG32_PLL
3127 (RADEON_CLK_PWRMGT_CNTL) &
3128 RADEON_DLL_READY)
3129 break;
3130 }
3131 break;
3132 case 5:
3133 tmp =
3134 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
3135 if (tmp & RADEON_CG_NO1_DEBUG_0) {
3136#if 0
3137 uint32_t mclk_cntl =
3138 RREG32_PLL
3139 (RADEON_MCLK_CNTL);
3140 mclk_cntl &= 0xffff0000;
3141
3142 WREG32_PLL(RADEON_MCLK_CNTL,
3143 mclk_cntl);
3144 mdelay(10);
3145#endif
3146 WREG32_PLL
3147 (RADEON_CLK_PWRMGT_CNTL,
3148 tmp &
3149 ~RADEON_CG_NO1_DEBUG_0);
3150 mdelay(10);
3151 }
3152 break;
3153 default:
3154 break;
3155 }
3156 break;
3157 default:
3158 break;
3159 }
3160 }
3161 }
3162}
3163
3164static void combios_parse_ram_reset_table(struct drm_device *dev,
3165 uint16_t offset)
3166{
3167 struct radeon_device *rdev = dev->dev_private;
3168 uint32_t tmp;
3169
3170 if (offset) {
3171 uint8_t val = RBIOS8(offset);
3172 while (val != 0xff) {
3173 offset++;
3174
3175 if (val == 0x0f) {
3176 uint32_t channel_complete_mask;
3177
3178 if (ASIC_IS_R300(rdev))
3179 channel_complete_mask =
3180 R300_MEM_PWRUP_COMPLETE;
3181 else
3182 channel_complete_mask =
3183 RADEON_MEM_PWRUP_COMPLETE;
3184 tmp = 20000;
3185 while (tmp--) {
3186 if ((RREG32(RADEON_MEM_STR_CNTL) &
3187 channel_complete_mask) ==
3188 channel_complete_mask)
3189 break;
3190 }
3191 } else {
3192 uint32_t or_mask = RBIOS16(offset);
3193 offset += 2;
3194
3195 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3196 tmp &= RADEON_SDRAM_MODE_MASK;
3197 tmp |= or_mask;
3198 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3199
3200 or_mask = val << 24;
3201 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3202 tmp &= RADEON_B3MEM_RESET_MASK;
3203 tmp |= or_mask;
3204 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
3205 }
3206 val = RBIOS8(offset);
3207 }
3208 }
3209}
3210
3211static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
3212 int mem_addr_mapping)
3213{
3214 struct radeon_device *rdev = dev->dev_private;
3215 uint32_t mem_cntl;
3216 uint32_t mem_size;
3217 uint32_t addr = 0;
3218
3219 mem_cntl = RREG32(RADEON_MEM_CNTL);
3220 if (mem_cntl & RV100_HALF_MODE)
3221 ram /= 2;
3222 mem_size = ram;
3223 mem_cntl &= ~(0xff << 8);
3224 mem_cntl |= (mem_addr_mapping & 0xff) << 8;
3225 WREG32(RADEON_MEM_CNTL, mem_cntl);
3226 RREG32(RADEON_MEM_CNTL);
3227
3228
3229
3230
3231 while (ram--) {
3232 addr = ram * 1024 * 1024;
3233
3234 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3235 WREG32(RADEON_MM_DATA, 0xdeadbeef);
3236
3237 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
3238 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
3239 return 0;
3240 }
3241
3242 return mem_size;
3243}
3244
3245static void combios_write_ram_size(struct drm_device *dev)
3246{
3247 struct radeon_device *rdev = dev->dev_private;
3248 uint8_t rev;
3249 uint16_t offset;
3250 uint32_t mem_size = 0;
3251 uint32_t mem_cntl = 0;
3252
3253
3254 if (rdev->flags & RADEON_IS_IGP)
3255 return;
3256
3257
3258 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
3259 if (offset) {
3260 rev = RBIOS8(offset);
3261 if (rev < 3) {
3262 mem_cntl = RBIOS32(offset + 1);
3263 mem_size = RBIOS16(offset + 5);
3264 if ((rdev->family < CHIP_R200) &&
3265 !ASIC_IS_RN50(rdev))
3266 WREG32(RADEON_MEM_CNTL, mem_cntl);
3267 }
3268 }
3269
3270 if (!mem_size) {
3271 offset =
3272 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
3273 if (offset) {
3274 rev = RBIOS8(offset - 1);
3275 if (rev < 1) {
3276 if ((rdev->family < CHIP_R200)
3277 && !ASIC_IS_RN50(rdev)) {
3278 int ram = 0;
3279 int mem_addr_mapping = 0;
3280
3281 while (RBIOS8(offset)) {
3282 ram = RBIOS8(offset);
3283 mem_addr_mapping =
3284 RBIOS8(offset + 1);
3285 if (mem_addr_mapping != 0x25)
3286 ram *= 2;
3287 mem_size =
3288 combios_detect_ram(dev, ram,
3289 mem_addr_mapping);
3290 if (mem_size)
3291 break;
3292 offset += 2;
3293 }
3294 } else
3295 mem_size = RBIOS8(offset);
3296 } else {
3297 mem_size = RBIOS8(offset);
3298 mem_size *= 2;
3299 }
3300 }
3301 }
3302
3303 mem_size *= (1024 * 1024);
3304 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
3305}
3306
3307void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
3308{
3309 uint16_t dyn_clk_info =
3310 combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3311
3312 if (dyn_clk_info)
3313 combios_parse_pll_table(dev, dyn_clk_info);
3314}
3315
3316void radeon_combios_asic_init(struct drm_device *dev)
3317{
3318 struct radeon_device *rdev = dev->dev_private;
3319 uint16_t table;
3320
3321
3322 if (rdev->bios == NULL)
3323 return;
3324
3325
3326 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
3327 if (table)
3328 combios_parse_mmio_table(dev, table);
3329
3330
3331 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
3332 if (table)
3333 combios_parse_pll_table(dev, table);
3334
3335
3336 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
3337 if (table)
3338 combios_parse_mmio_table(dev, table);
3339
3340 if (!(rdev->flags & RADEON_IS_IGP)) {
3341
3342 table =
3343 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
3344 if (table)
3345 combios_parse_mmio_table(dev, table);
3346
3347
3348 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
3349 if (table)
3350 combios_parse_ram_reset_table(dev, table);
3351
3352
3353 table =
3354 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
3355 if (table)
3356 combios_parse_mmio_table(dev, table);
3357
3358
3359 combios_write_ram_size(dev);
3360 }
3361
3362
3363
3364
3365 if (rdev->family == CHIP_RS480 &&
3366 rdev->pdev->subsystem_vendor == 0x103c &&
3367 rdev->pdev->subsystem_device == 0x308b)
3368 return;
3369
3370
3371
3372
3373 if (rdev->family == CHIP_RS480 &&
3374 rdev->pdev->subsystem_vendor == 0x103c &&
3375 rdev->pdev->subsystem_device == 0x30a4)
3376 return;
3377
3378
3379
3380
3381 if (rdev->family == CHIP_RS480 &&
3382 rdev->pdev->subsystem_vendor == 0x103c &&
3383 rdev->pdev->subsystem_device == 0x30ae)
3384 return;
3385
3386
3387 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
3388 if (table)
3389 combios_parse_pll_table(dev, table);
3390
3391}
3392
3393void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
3394{
3395 struct radeon_device *rdev = dev->dev_private;
3396 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
3397
3398 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
3399 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3400 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
3401
3402
3403 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
3404
3405
3406 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
3407 RADEON_ACC_MODE_CHANGE);
3408
3409
3410 bios_7_scratch |= RADEON_DRV_LOADED;
3411
3412 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
3413 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3414 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
3415}
3416
3417void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3418{
3419 struct drm_device *dev = encoder->dev;
3420 struct radeon_device *rdev = dev->dev_private;
3421 uint32_t bios_6_scratch;
3422
3423 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3424
3425 if (lock)
3426 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
3427 else
3428 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
3429
3430 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3431}
3432
3433void
3434radeon_combios_connected_scratch_regs(struct drm_connector *connector,
3435 struct drm_encoder *encoder,
3436 bool connected)
3437{
3438 struct drm_device *dev = connector->dev;
3439 struct radeon_device *rdev = dev->dev_private;
3440 struct radeon_connector *radeon_connector =
3441 to_radeon_connector(connector);
3442 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3443 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
3444 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3445
3446 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3447 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3448 if (connected) {
3449 DRM_DEBUG_KMS("TV1 connected\n");
3450
3451 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
3452
3453 bios_5_scratch |= RADEON_TV1_ON;
3454 bios_5_scratch |= RADEON_ACC_REQ_TV1;
3455 } else {
3456 DRM_DEBUG_KMS("TV1 disconnected\n");
3457 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
3458 bios_5_scratch &= ~RADEON_TV1_ON;
3459 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
3460 }
3461 }
3462 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3463 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3464 if (connected) {
3465 DRM_DEBUG_KMS("LCD1 connected\n");
3466 bios_4_scratch |= RADEON_LCD1_ATTACHED;
3467 bios_5_scratch |= RADEON_LCD1_ON;
3468 bios_5_scratch |= RADEON_ACC_REQ_LCD1;
3469 } else {
3470 DRM_DEBUG_KMS("LCD1 disconnected\n");
3471 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
3472 bios_5_scratch &= ~RADEON_LCD1_ON;
3473 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
3474 }
3475 }
3476 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3477 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3478 if (connected) {
3479 DRM_DEBUG_KMS("CRT1 connected\n");
3480 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
3481 bios_5_scratch |= RADEON_CRT1_ON;
3482 bios_5_scratch |= RADEON_ACC_REQ_CRT1;
3483 } else {
3484 DRM_DEBUG_KMS("CRT1 disconnected\n");
3485 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
3486 bios_5_scratch &= ~RADEON_CRT1_ON;
3487 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
3488 }
3489 }
3490 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3491 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3492 if (connected) {
3493 DRM_DEBUG_KMS("CRT2 connected\n");
3494 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
3495 bios_5_scratch |= RADEON_CRT2_ON;
3496 bios_5_scratch |= RADEON_ACC_REQ_CRT2;
3497 } else {
3498 DRM_DEBUG_KMS("CRT2 disconnected\n");
3499 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
3500 bios_5_scratch &= ~RADEON_CRT2_ON;
3501 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
3502 }
3503 }
3504 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3505 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3506 if (connected) {
3507 DRM_DEBUG_KMS("DFP1 connected\n");
3508 bios_4_scratch |= RADEON_DFP1_ATTACHED;
3509 bios_5_scratch |= RADEON_DFP1_ON;
3510 bios_5_scratch |= RADEON_ACC_REQ_DFP1;
3511 } else {
3512 DRM_DEBUG_KMS("DFP1 disconnected\n");
3513 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
3514 bios_5_scratch &= ~RADEON_DFP1_ON;
3515 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
3516 }
3517 }
3518 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3519 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3520 if (connected) {
3521 DRM_DEBUG_KMS("DFP2 connected\n");
3522 bios_4_scratch |= RADEON_DFP2_ATTACHED;
3523 bios_5_scratch |= RADEON_DFP2_ON;
3524 bios_5_scratch |= RADEON_ACC_REQ_DFP2;
3525 } else {
3526 DRM_DEBUG_KMS("DFP2 disconnected\n");
3527 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
3528 bios_5_scratch &= ~RADEON_DFP2_ON;
3529 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
3530 }
3531 }
3532 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
3533 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3534}
3535
3536void
3537radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3538{
3539 struct drm_device *dev = encoder->dev;
3540 struct radeon_device *rdev = dev->dev_private;
3541 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3542 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
3543
3544 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3545 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
3546 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
3547 }
3548 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3549 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
3550 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
3551 }
3552 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3553 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
3554 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
3555 }
3556 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3557 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
3558 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
3559 }
3560 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3561 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
3562 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
3563 }
3564 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3565 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
3566 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
3567 }
3568 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
3569}
3570
3571void
3572radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3573{
3574 struct drm_device *dev = encoder->dev;
3575 struct radeon_device *rdev = dev->dev_private;
3576 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3577 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
3578
3579 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3580 if (on)
3581 bios_6_scratch |= RADEON_TV_DPMS_ON;
3582 else
3583 bios_6_scratch &= ~RADEON_TV_DPMS_ON;
3584 }
3585 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3586 if (on)
3587 bios_6_scratch |= RADEON_CRT_DPMS_ON;
3588 else
3589 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
3590 }
3591 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3592 if (on)
3593 bios_6_scratch |= RADEON_LCD_DPMS_ON;
3594 else
3595 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
3596 }
3597 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
3598 if (on)
3599 bios_6_scratch |= RADEON_DFP_DPMS_ON;
3600 else
3601 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
3602 }
3603 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
3604}
3605
