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26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/string.h>
29#include <linux/slab.h>
30#include <linux/i2c.h>
31
32#include "stv0900.h"
33#include "stv0900_reg.h"
34#include "stv0900_priv.h"
35#include "stv0900_init.h"
36
37int stvdebug = 1;
38module_param_named(debug, stvdebug, int, 0644);
39
40
41struct stv0900_inode {
42
43 struct stv0900_internal *internal;
44 struct stv0900_inode *next_inode;
45};
46
47
48static struct stv0900_inode *stv0900_first_inode;
49
50
51static struct stv0900_inode *find_inode(struct i2c_adapter *i2c_adap,
52 u8 i2c_addr)
53{
54 struct stv0900_inode *temp_chip = stv0900_first_inode;
55
56 if (temp_chip != NULL) {
57
58
59
60 while ((temp_chip != NULL) &&
61 ((temp_chip->internal->i2c_adap != i2c_adap) ||
62 (temp_chip->internal->i2c_addr != i2c_addr)))
63
64 temp_chip = temp_chip->next_inode;
65
66 }
67
68 return temp_chip;
69}
70
71
72static void remove_inode(struct stv0900_internal *internal)
73{
74 struct stv0900_inode *prev_node = stv0900_first_inode;
75 struct stv0900_inode *del_node = find_inode(internal->i2c_adap,
76 internal->i2c_addr);
77
78 if (del_node != NULL) {
79 if (del_node == stv0900_first_inode) {
80 stv0900_first_inode = del_node->next_inode;
81 } else {
82 while (prev_node->next_inode != del_node)
83 prev_node = prev_node->next_inode;
84
85 if (del_node->next_inode == NULL)
86 prev_node->next_inode = NULL;
87 else
88 prev_node->next_inode =
89 prev_node->next_inode->next_inode;
90 }
91
92 kfree(del_node);
93 }
94}
95
96
97static struct stv0900_inode *append_internal(struct stv0900_internal *internal)
98{
99 struct stv0900_inode *new_node = stv0900_first_inode;
100
101 if (new_node == NULL) {
102 new_node = kmalloc(sizeof(struct stv0900_inode), GFP_KERNEL);
103 stv0900_first_inode = new_node;
104 } else {
105 while (new_node->next_inode != NULL)
106 new_node = new_node->next_inode;
107
108 new_node->next_inode = kmalloc(sizeof(struct stv0900_inode),
109 GFP_KERNEL);
110 if (new_node->next_inode != NULL)
111 new_node = new_node->next_inode;
112 else
113 new_node = NULL;
114 }
115
116 if (new_node != NULL) {
117 new_node->internal = internal;
118 new_node->next_inode = NULL;
119 }
120
121 return new_node;
122}
123
124s32 ge2comp(s32 a, s32 width)
125{
126 if (width == 32)
127 return a;
128 else
129 return (a >= (1 << (width - 1))) ? (a - (1 << width)) : a;
130}
131
132void stv0900_write_reg(struct stv0900_internal *intp, u16 reg_addr,
133 u8 reg_data)
134{
135 u8 data[3];
136 int ret;
137 struct i2c_msg i2cmsg = {
138 .addr = intp->i2c_addr,
139 .flags = 0,
140 .len = 3,
141 .buf = data,
142 };
143
144 data[0] = MSB(reg_addr);
145 data[1] = LSB(reg_addr);
146 data[2] = reg_data;
147
148 ret = i2c_transfer(intp->i2c_adap, &i2cmsg, 1);
149 if (ret != 1)
150 dprintk("%s: i2c error %d\n", __func__, ret);
151}
152
153u8 stv0900_read_reg(struct stv0900_internal *intp, u16 reg)
154{
155 int ret;
156 u8 b0[] = { MSB(reg), LSB(reg) };
157 u8 buf = 0;
158 struct i2c_msg msg[] = {
159 {
160 .addr = intp->i2c_addr,
161 .flags = 0,
162 .buf = b0,
163 .len = 2,
164 }, {
165 .addr = intp->i2c_addr,
166 .flags = I2C_M_RD,
167 .buf = &buf,
168 .len = 1,
169 },
170 };
171
172 ret = i2c_transfer(intp->i2c_adap, msg, 2);
173 if (ret != 2)
174 dprintk("%s: i2c error %d, reg[0x%02x]\n",
175 __func__, ret, reg);
176
177 return buf;
178}
179
180static void extract_mask_pos(u32 label, u8 *mask, u8 *pos)
181{
182 u8 position = 0, i = 0;
183
184 (*mask) = label & 0xff;
185
186 while ((position == 0) && (i < 8)) {
187 position = ((*mask) >> i) & 0x01;
188 i++;
189 }
190
191 (*pos) = (i - 1);
192}
193
194void stv0900_write_bits(struct stv0900_internal *intp, u32 label, u8 val)
195{
196 u8 reg, mask, pos;
197
198 reg = stv0900_read_reg(intp, (label >> 16) & 0xffff);
199 extract_mask_pos(label, &mask, &pos);
200
201 val = mask & (val << pos);
202
203 reg = (reg & (~mask)) | val;
204 stv0900_write_reg(intp, (label >> 16) & 0xffff, reg);
205
206}
207
208u8 stv0900_get_bits(struct stv0900_internal *intp, u32 label)
209{
210 u8 val = 0xff;
211 u8 mask, pos;
212
213 extract_mask_pos(label, &mask, &pos);
214
215 val = stv0900_read_reg(intp, label >> 16);
216 val = (val & mask) >> pos;
217
218 return val;
219}
220
221static enum fe_stv0900_error stv0900_initialize(struct stv0900_internal *intp)
222{
223 s32 i;
224
225 if (intp == NULL)
226 return STV0900_INVALID_HANDLE;
227
228 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
229
230 if (intp->errs != STV0900_NO_ERROR)
231 return intp->errs;
232
233
234 stv0900_write_reg(intp, R0900_P1_DMDISTATE, 0x5c);
235 stv0900_write_reg(intp, R0900_P2_DMDISTATE, 0x5c);
236 msleep(3);
237 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x6c);
238 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x6f);
239 stv0900_write_reg(intp, R0900_P1_I2CRPT, 0x20);
240 stv0900_write_reg(intp, R0900_P2_I2CRPT, 0x20);
241 stv0900_write_reg(intp, R0900_NCOARSE, 0x13);
242 msleep(3);
243 stv0900_write_reg(intp, R0900_I2CCFG, 0x08);
244
245 switch (intp->clkmode) {
246 case 0:
247 case 2:
248 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20
249 | intp->clkmode);
250 break;
251 default:
252
253 i = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
254 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | i);
255 break;
256 }
257
258 msleep(3);
259 for (i = 0; i < 181; i++)
260 stv0900_write_reg(intp, STV0900_InitVal[i][0],
261 STV0900_InitVal[i][1]);
262
263 if (stv0900_read_reg(intp, R0900_MID) >= 0x20) {
264 stv0900_write_reg(intp, R0900_TSGENERAL, 0x0c);
265 for (i = 0; i < 32; i++)
266 stv0900_write_reg(intp, STV0900_Cut20_AddOnVal[i][0],
267 STV0900_Cut20_AddOnVal[i][1]);
268 }
269
270 stv0900_write_reg(intp, R0900_P1_FSPYCFG, 0x6c);
271 stv0900_write_reg(intp, R0900_P2_FSPYCFG, 0x6c);
272
273 stv0900_write_reg(intp, R0900_P1_PDELCTRL2, 0x01);
274 stv0900_write_reg(intp, R0900_P2_PDELCTRL2, 0x21);
275
276 stv0900_write_reg(intp, R0900_P1_PDELCTRL3, 0x20);
277 stv0900_write_reg(intp, R0900_P2_PDELCTRL3, 0x20);
278
279 stv0900_write_reg(intp, R0900_TSTRES0, 0x80);
280 stv0900_write_reg(intp, R0900_TSTRES0, 0x00);
281
282 return STV0900_NO_ERROR;
283}
284
285static u32 stv0900_get_mclk_freq(struct stv0900_internal *intp, u32 ext_clk)
286{
287 u32 mclk = 90000000, div = 0, ad_div = 0;
288
289 div = stv0900_get_bits(intp, F0900_M_DIV);
290 ad_div = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
291
292 mclk = (div + 1) * ext_clk / ad_div;
293
294 dprintk("%s: Calculated Mclk = %d\n", __func__, mclk);
295
296 return mclk;
297}
298
299static enum fe_stv0900_error stv0900_set_mclk(struct stv0900_internal *intp, u32 mclk)
300{
301 u32 m_div, clk_sel;
302
303 dprintk("%s: Mclk set to %d, Quartz = %d\n", __func__, mclk,
304 intp->quartz);
305
306 if (intp == NULL)
307 return STV0900_INVALID_HANDLE;
308
309 if (intp->errs)
310 return STV0900_I2C_ERROR;
311
312 clk_sel = ((stv0900_get_bits(intp, F0900_SELX1RATIO) == 1) ? 4 : 6);
313 m_div = ((clk_sel * mclk) / intp->quartz) - 1;
314 stv0900_write_bits(intp, F0900_M_DIV, m_div);
315 intp->mclk = stv0900_get_mclk_freq(intp,
316 intp->quartz);
317
318
319
320
321
322
323
324 m_div = intp->mclk / 704000;
325 stv0900_write_reg(intp, R0900_P1_F22TX, m_div);
326 stv0900_write_reg(intp, R0900_P1_F22RX, m_div);
327
328 stv0900_write_reg(intp, R0900_P2_F22TX, m_div);
329 stv0900_write_reg(intp, R0900_P2_F22RX, m_div);
330
331 if ((intp->errs))
332 return STV0900_I2C_ERROR;
333
334 return STV0900_NO_ERROR;
335}
336
337static u32 stv0900_get_err_count(struct stv0900_internal *intp, int cntr,
338 enum fe_stv0900_demod_num demod)
339{
340 u32 lsb, msb, hsb, err_val;
341
342 switch (cntr) {
343 case 0:
344 default:
345 hsb = stv0900_get_bits(intp, ERR_CNT12);
346 msb = stv0900_get_bits(intp, ERR_CNT11);
347 lsb = stv0900_get_bits(intp, ERR_CNT10);
348 break;
349 case 1:
350 hsb = stv0900_get_bits(intp, ERR_CNT22);
351 msb = stv0900_get_bits(intp, ERR_CNT21);
352 lsb = stv0900_get_bits(intp, ERR_CNT20);
353 break;
354 }
355
356 err_val = (hsb << 16) + (msb << 8) + (lsb);
357
358 return err_val;
359}
360
361static int stv0900_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
362{
363 struct stv0900_state *state = fe->demodulator_priv;
364 struct stv0900_internal *intp = state->internal;
365 enum fe_stv0900_demod_num demod = state->demod;
366
367 stv0900_write_bits(intp, I2CT_ON, enable);
368
369 return 0;
370}
371
372static void stv0900_set_ts_parallel_serial(struct stv0900_internal *intp,
373 enum fe_stv0900_clock_type path1_ts,
374 enum fe_stv0900_clock_type path2_ts)
375{
376
377 dprintk("%s\n", __func__);
378
379 if (intp->chip_id >= 0x20) {
380 switch (path1_ts) {
381 case STV0900_PARALLEL_PUNCT_CLOCK:
382 case STV0900_DVBCI_CLOCK:
383 switch (path2_ts) {
384 case STV0900_SERIAL_PUNCT_CLOCK:
385 case STV0900_SERIAL_CONT_CLOCK:
386 default:
387 stv0900_write_reg(intp, R0900_TSGENERAL,
388 0x00);
389 break;
390 case STV0900_PARALLEL_PUNCT_CLOCK:
391 case STV0900_DVBCI_CLOCK:
392 stv0900_write_reg(intp, R0900_TSGENERAL,
393 0x06);
394 stv0900_write_bits(intp,
395 F0900_P1_TSFIFO_MANSPEED, 3);
396 stv0900_write_bits(intp,
397 F0900_P2_TSFIFO_MANSPEED, 0);
398 stv0900_write_reg(intp,
399 R0900_P1_TSSPEED, 0x14);
400 stv0900_write_reg(intp,
401 R0900_P2_TSSPEED, 0x28);
402 break;
403 }
404 break;
405 case STV0900_SERIAL_PUNCT_CLOCK:
406 case STV0900_SERIAL_CONT_CLOCK:
407 default:
408 switch (path2_ts) {
409 case STV0900_SERIAL_PUNCT_CLOCK:
410 case STV0900_SERIAL_CONT_CLOCK:
411 default:
412 stv0900_write_reg(intp,
413 R0900_TSGENERAL, 0x0C);
414 break;
415 case STV0900_PARALLEL_PUNCT_CLOCK:
416 case STV0900_DVBCI_CLOCK:
417 stv0900_write_reg(intp,
418 R0900_TSGENERAL, 0x0A);
419 dprintk("%s: 0x0a\n", __func__);
420 break;
421 }
422 break;
423 }
424 } else {
425 switch (path1_ts) {
426 case STV0900_PARALLEL_PUNCT_CLOCK:
427 case STV0900_DVBCI_CLOCK:
428 switch (path2_ts) {
429 case STV0900_SERIAL_PUNCT_CLOCK:
430 case STV0900_SERIAL_CONT_CLOCK:
431 default:
432 stv0900_write_reg(intp, R0900_TSGENERAL1X,
433 0x10);
434 break;
435 case STV0900_PARALLEL_PUNCT_CLOCK:
436 case STV0900_DVBCI_CLOCK:
437 stv0900_write_reg(intp, R0900_TSGENERAL1X,
438 0x16);
439 stv0900_write_bits(intp,
440 F0900_P1_TSFIFO_MANSPEED, 3);
441 stv0900_write_bits(intp,
442 F0900_P2_TSFIFO_MANSPEED, 0);
443 stv0900_write_reg(intp, R0900_P1_TSSPEED,
444 0x14);
445 stv0900_write_reg(intp, R0900_P2_TSSPEED,
446 0x28);
447 break;
448 }
449
450 break;
451 case STV0900_SERIAL_PUNCT_CLOCK:
452 case STV0900_SERIAL_CONT_CLOCK:
453 default:
454 switch (path2_ts) {
455 case STV0900_SERIAL_PUNCT_CLOCK:
456 case STV0900_SERIAL_CONT_CLOCK:
457 default:
458 stv0900_write_reg(intp, R0900_TSGENERAL1X,
459 0x14);
460 break;
461 case STV0900_PARALLEL_PUNCT_CLOCK:
462 case STV0900_DVBCI_CLOCK:
463 stv0900_write_reg(intp, R0900_TSGENERAL1X,
464 0x12);
465 dprintk("%s: 0x12\n", __func__);
466 break;
467 }
468
469 break;
470 }
471 }
472
473 switch (path1_ts) {
474 case STV0900_PARALLEL_PUNCT_CLOCK:
475 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
476 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
477 break;
478 case STV0900_DVBCI_CLOCK:
479 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x00);
480 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
481 break;
482 case STV0900_SERIAL_PUNCT_CLOCK:
483 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
484 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x00);
485 break;
486 case STV0900_SERIAL_CONT_CLOCK:
487 stv0900_write_bits(intp, F0900_P1_TSFIFO_SERIAL, 0x01);
488 stv0900_write_bits(intp, F0900_P1_TSFIFO_DVBCI, 0x01);
489 break;
490 default:
491 break;
492 }
493
494 switch (path2_ts) {
495 case STV0900_PARALLEL_PUNCT_CLOCK:
496 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
497 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
498 break;
499 case STV0900_DVBCI_CLOCK:
500 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x00);
501 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
502 break;
503 case STV0900_SERIAL_PUNCT_CLOCK:
504 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
505 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x00);
506 break;
507 case STV0900_SERIAL_CONT_CLOCK:
508 stv0900_write_bits(intp, F0900_P2_TSFIFO_SERIAL, 0x01);
509 stv0900_write_bits(intp, F0900_P2_TSFIFO_DVBCI, 0x01);
510 break;
511 default:
512 break;
513 }
514
515 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
516 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
517 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
518 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
519}
520
521void stv0900_set_tuner(struct dvb_frontend *fe, u32 frequency,
522 u32 bandwidth)
523{
524 struct dvb_frontend_ops *frontend_ops = NULL;
525 struct dvb_tuner_ops *tuner_ops = NULL;
526
527 if (&fe->ops)
528 frontend_ops = &fe->ops;
529
530 if (&frontend_ops->tuner_ops)
531 tuner_ops = &frontend_ops->tuner_ops;
532
533 if (tuner_ops->set_frequency) {
534 if ((tuner_ops->set_frequency(fe, frequency)) < 0)
535 dprintk("%s: Invalid parameter\n", __func__);
536 else
537 dprintk("%s: Frequency=%d\n", __func__, frequency);
538
539 }
540
541 if (tuner_ops->set_bandwidth) {
542 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
543 dprintk("%s: Invalid parameter\n", __func__);
544 else
545 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
546
547 }
548}
549
550void stv0900_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
551{
552 struct dvb_frontend_ops *frontend_ops = NULL;
553 struct dvb_tuner_ops *tuner_ops = NULL;
554
555 if (&fe->ops)
556 frontend_ops = &fe->ops;
557
558 if (&frontend_ops->tuner_ops)
559 tuner_ops = &frontend_ops->tuner_ops;
560
561 if (tuner_ops->set_bandwidth) {
562 if ((tuner_ops->set_bandwidth(fe, bandwidth)) < 0)
563 dprintk("%s: Invalid parameter\n", __func__);
564 else
565 dprintk("%s: Bandwidth=%d\n", __func__, bandwidth);
566
567 }
568}
569
570u32 stv0900_get_freq_auto(struct stv0900_internal *intp, int demod)
571{
572 u32 freq, round;
573
574
575
576
577
578 freq = (stv0900_get_bits(intp, TUN_RFFREQ2) << 10) +
579 (stv0900_get_bits(intp, TUN_RFFREQ1) << 2) +
580 stv0900_get_bits(intp, TUN_RFFREQ0);
581
582 freq = (freq * 1000) / 64;
583
584 round = (stv0900_get_bits(intp, TUN_RFRESTE1) >> 2) +
585 stv0900_get_bits(intp, TUN_RFRESTE0);
586
587 round = (round * 1000) / 2048;
588
589 return freq + round;
590}
591
592void stv0900_set_tuner_auto(struct stv0900_internal *intp, u32 Frequency,
593 u32 Bandwidth, int demod)
594{
595 u32 tunerFrequency;
596
597
598
599 tunerFrequency = (Frequency * 64) / 1000;
600
601 stv0900_write_bits(intp, TUN_RFFREQ2, (tunerFrequency >> 10));
602 stv0900_write_bits(intp, TUN_RFFREQ1, (tunerFrequency >> 2) & 0xff);
603 stv0900_write_bits(intp, TUN_RFFREQ0, (tunerFrequency & 0x03));
604
605 stv0900_write_bits(intp, TUN_BW, Bandwidth / 2000000);
606
607 stv0900_write_reg(intp, TNRLD, 1);
608}
609
610static s32 stv0900_get_rf_level(struct stv0900_internal *intp,
611 const struct stv0900_table *lookup,
612 enum fe_stv0900_demod_num demod)
613{
614 s32 agc_gain = 0,
615 imin,
616 imax,
617 i,
618 rf_lvl = 0;
619
620 dprintk("%s\n", __func__);
621
622 if ((lookup == NULL) || (lookup->size <= 0))
623 return 0;
624
625 agc_gain = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
626 stv0900_get_bits(intp, AGCIQ_VALUE0));
627
628 imin = 0;
629 imax = lookup->size - 1;
630 if (INRANGE(lookup->table[imin].regval, agc_gain,
631 lookup->table[imax].regval)) {
632 while ((imax - imin) > 1) {
633 i = (imax + imin) >> 1;
634
635 if (INRANGE(lookup->table[imin].regval,
636 agc_gain,
637 lookup->table[i].regval))
638 imax = i;
639 else
640 imin = i;
641 }
642
643 rf_lvl = (s32)agc_gain - lookup->table[imin].regval;
644 rf_lvl *= (lookup->table[imax].realval -
645 lookup->table[imin].realval);
646 rf_lvl /= (lookup->table[imax].regval -
647 lookup->table[imin].regval);
648 rf_lvl += lookup->table[imin].realval;
649 } else if (agc_gain > lookup->table[0].regval)
650 rf_lvl = 5;
651 else if (agc_gain < lookup->table[lookup->size-1].regval)
652 rf_lvl = -100;
653
654 dprintk("%s: RFLevel = %d\n", __func__, rf_lvl);
655
656 return rf_lvl;
657}
658
659static int stv0900_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
660{
661 struct stv0900_state *state = fe->demodulator_priv;
662 struct stv0900_internal *internal = state->internal;
663 s32 rflevel = stv0900_get_rf_level(internal, &stv0900_rf,
664 state->demod);
665
666 rflevel = (rflevel + 100) * (65535 / 70);
667 if (rflevel < 0)
668 rflevel = 0;
669
670 if (rflevel > 65535)
671 rflevel = 65535;
672
673 *strength = rflevel;
674
675 return 0;
676}
677
678static s32 stv0900_carr_get_quality(struct dvb_frontend *fe,
679 const struct stv0900_table *lookup)
680{
681 struct stv0900_state *state = fe->demodulator_priv;
682 struct stv0900_internal *intp = state->internal;
683 enum fe_stv0900_demod_num demod = state->demod;
684
685 s32 c_n = -100,
686 regval,
687 imin,
688 imax,
689 i,
690 noise_field1,
691 noise_field0;
692
693 dprintk("%s\n", __func__);
694
695 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
696 noise_field1 = NOSPLHT_NORMED1;
697 noise_field0 = NOSPLHT_NORMED0;
698 } else {
699 noise_field1 = NOSDATAT_NORMED1;
700 noise_field0 = NOSDATAT_NORMED0;
701 }
702
703 if (stv0900_get_bits(intp, LOCK_DEFINITIF)) {
704 if ((lookup != NULL) && lookup->size) {
705 regval = 0;
706 msleep(5);
707 for (i = 0; i < 16; i++) {
708 regval += MAKEWORD(stv0900_get_bits(intp,
709 noise_field1),
710 stv0900_get_bits(intp,
711 noise_field0));
712 msleep(1);
713 }
714
715 regval /= 16;
716 imin = 0;
717 imax = lookup->size - 1;
718 if (INRANGE(lookup->table[imin].regval,
719 regval,
720 lookup->table[imax].regval)) {
721 while ((imax - imin) > 1) {
722 i = (imax + imin) >> 1;
723 if (INRANGE(lookup->table[imin].regval,
724 regval,
725 lookup->table[i].regval))
726 imax = i;
727 else
728 imin = i;
729 }
730
731 c_n = ((regval - lookup->table[imin].regval)
732 * (lookup->table[imax].realval
733 - lookup->table[imin].realval)
734 / (lookup->table[imax].regval
735 - lookup->table[imin].regval))
736 + lookup->table[imin].realval;
737 } else if (regval < lookup->table[imin].regval)
738 c_n = 1000;
739 }
740 }
741
742 return c_n;
743}
744
745static int stv0900_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
746{
747 struct stv0900_state *state = fe->demodulator_priv;
748 struct stv0900_internal *intp = state->internal;
749 enum fe_stv0900_demod_num demod = state->demod;
750 u8 err_val1, err_val0;
751 u32 header_err_val = 0;
752
753 *ucblocks = 0x0;
754 if (stv0900_get_standard(fe, demod) == STV0900_DVBS2_STANDARD) {
755
756
757
758 err_val1 = stv0900_read_reg(intp, BBFCRCKO1);
759 err_val0 = stv0900_read_reg(intp, BBFCRCKO0);
760 header_err_val = (err_val1 << 8) | err_val0;
761
762
763 err_val1 = stv0900_read_reg(intp, UPCRCKO1);
764 err_val0 = stv0900_read_reg(intp, UPCRCKO0);
765 *ucblocks = (err_val1 << 8) | err_val0;
766 *ucblocks += header_err_val;
767 }
768
769 return 0;
770}
771
772static int stv0900_read_snr(struct dvb_frontend *fe, u16 *snr)
773{
774 s32 snrlcl = stv0900_carr_get_quality(fe,
775 (const struct stv0900_table *)&stv0900_s2_cn);
776 snrlcl = (snrlcl + 30) * 384;
777 if (snrlcl < 0)
778 snrlcl = 0;
779
780 if (snrlcl > 65535)
781 snrlcl = 65535;
782
783 *snr = snrlcl;
784
785 return 0;
786}
787
788static u32 stv0900_get_ber(struct stv0900_internal *intp,
789 enum fe_stv0900_demod_num demod)
790{
791 u32 ber = 10000000, i;
792 s32 demod_state;
793
794 demod_state = stv0900_get_bits(intp, HEADER_MODE);
795
796 switch (demod_state) {
797 case STV0900_SEARCH:
798 case STV0900_PLH_DETECTED:
799 default:
800 ber = 10000000;
801 break;
802 case STV0900_DVBS_FOUND:
803 ber = 0;
804 for (i = 0; i < 5; i++) {
805 msleep(5);
806 ber += stv0900_get_err_count(intp, 0, demod);
807 }
808
809 ber /= 5;
810 if (stv0900_get_bits(intp, PRFVIT)) {
811 ber *= 9766;
812 ber = ber >> 13;
813 }
814
815 break;
816 case STV0900_DVBS2_FOUND:
817 ber = 0;
818 for (i = 0; i < 5; i++) {
819 msleep(5);
820 ber += stv0900_get_err_count(intp, 0, demod);
821 }
822
823 ber /= 5;
824 if (stv0900_get_bits(intp, PKTDELIN_LOCK)) {
825 ber *= 9766;
826 ber = ber >> 13;
827 }
828
829 break;
830 }
831
832 return ber;
833}
834
835static int stv0900_read_ber(struct dvb_frontend *fe, u32 *ber)
836{
837 struct stv0900_state *state = fe->demodulator_priv;
838 struct stv0900_internal *internal = state->internal;
839
840 *ber = stv0900_get_ber(internal, state->demod);
841
842 return 0;
843}
844
845int stv0900_get_demod_lock(struct stv0900_internal *intp,
846 enum fe_stv0900_demod_num demod, s32 time_out)
847{
848 s32 timer = 0,
849 lock = 0;
850
851 enum fe_stv0900_search_state dmd_state;
852
853 while ((timer < time_out) && (lock == 0)) {
854 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
855 dprintk("Demod State = %d\n", dmd_state);
856 switch (dmd_state) {
857 case STV0900_SEARCH:
858 case STV0900_PLH_DETECTED:
859 default:
860 lock = 0;
861 break;
862 case STV0900_DVBS2_FOUND:
863 case STV0900_DVBS_FOUND:
864 lock = stv0900_get_bits(intp, LOCK_DEFINITIF);
865 break;
866 }
867
868 if (lock == 0)
869 msleep(10);
870
871 timer += 10;
872 }
873
874 if (lock)
875 dprintk("DEMOD LOCK OK\n");
876 else
877 dprintk("DEMOD LOCK FAIL\n");
878
879 return lock;
880}
881
882void stv0900_stop_all_s2_modcod(struct stv0900_internal *intp,
883 enum fe_stv0900_demod_num demod)
884{
885 s32 regflist,
886 i;
887
888 dprintk("%s\n", __func__);
889
890 regflist = MODCODLST0;
891
892 for (i = 0; i < 16; i++)
893 stv0900_write_reg(intp, regflist + i, 0xff);
894}
895
896void stv0900_activate_s2_modcod(struct stv0900_internal *intp,
897 enum fe_stv0900_demod_num demod)
898{
899 u32 matype,
900 mod_code,
901 fmod,
902 reg_index,
903 field_index;
904
905 dprintk("%s\n", __func__);
906
907 if (intp->chip_id <= 0x11) {
908 msleep(5);
909
910 mod_code = stv0900_read_reg(intp, PLHMODCOD);
911 matype = mod_code & 0x3;
912 mod_code = (mod_code & 0x7f) >> 2;
913
914 reg_index = MODCODLSTF - mod_code / 2;
915 field_index = mod_code % 2;
916
917 switch (matype) {
918 case 0:
919 default:
920 fmod = 14;
921 break;
922 case 1:
923 fmod = 13;
924 break;
925 case 2:
926 fmod = 11;
927 break;
928 case 3:
929 fmod = 7;
930 break;
931 }
932
933 if ((INRANGE(STV0900_QPSK_12, mod_code, STV0900_8PSK_910))
934 && (matype <= 1)) {
935 if (field_index == 0)
936 stv0900_write_reg(intp, reg_index,
937 0xf0 | fmod);
938 else
939 stv0900_write_reg(intp, reg_index,
940 (fmod << 4) | 0xf);
941 }
942
943 } else if (intp->chip_id >= 0x12) {
944 for (reg_index = 0; reg_index < 7; reg_index++)
945 stv0900_write_reg(intp, MODCODLST0 + reg_index, 0xff);
946
947 stv0900_write_reg(intp, MODCODLSTE, 0xff);
948 stv0900_write_reg(intp, MODCODLSTF, 0xcf);
949 for (reg_index = 0; reg_index < 8; reg_index++)
950 stv0900_write_reg(intp, MODCODLST7 + reg_index, 0xcc);
951
952
953 }
954}
955
956void stv0900_activate_s2_modcod_single(struct stv0900_internal *intp,
957 enum fe_stv0900_demod_num demod)
958{
959 u32 reg_index;
960
961 dprintk("%s\n", __func__);
962
963 stv0900_write_reg(intp, MODCODLST0, 0xff);
964 stv0900_write_reg(intp, MODCODLST1, 0xf0);
965 stv0900_write_reg(intp, MODCODLSTF, 0x0f);
966 for (reg_index = 0; reg_index < 13; reg_index++)
967 stv0900_write_reg(intp, MODCODLST2 + reg_index, 0);
968
969}
970
971static enum dvbfe_algo stv0900_frontend_algo(struct dvb_frontend *fe)
972{
973 return DVBFE_ALGO_CUSTOM;
974}
975
976void stv0900_start_search(struct stv0900_internal *intp,
977 enum fe_stv0900_demod_num demod)
978{
979 u32 freq;
980 s16 freq_s16 ;
981
982 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
983 if (intp->chip_id == 0x10)
984 stv0900_write_reg(intp, CORRELEXP, 0xaa);
985
986 if (intp->chip_id < 0x20)
987 stv0900_write_reg(intp, CARHDR, 0x55);
988
989 if (intp->chip_id <= 0x20) {
990 if (intp->symbol_rate[0] <= 5000000) {
991 stv0900_write_reg(intp, CARCFG, 0x44);
992 stv0900_write_reg(intp, CFRUP1, 0x0f);
993 stv0900_write_reg(intp, CFRUP0, 0xff);
994 stv0900_write_reg(intp, CFRLOW1, 0xf0);
995 stv0900_write_reg(intp, CFRLOW0, 0x00);
996 stv0900_write_reg(intp, RTCS2, 0x68);
997 } else {
998 stv0900_write_reg(intp, CARCFG, 0xc4);
999 stv0900_write_reg(intp, RTCS2, 0x44);
1000 }
1001
1002 } else {
1003 if (intp->symbol_rate[demod] <= 5000000)
1004 stv0900_write_reg(intp, RTCS2, 0x68);
1005 else
1006 stv0900_write_reg(intp, RTCS2, 0x44);
1007
1008 stv0900_write_reg(intp, CARCFG, 0x46);
1009 if (intp->srch_algo[demod] == STV0900_WARM_START) {
1010 freq = 1000 << 16;
1011 freq /= (intp->mclk / 1000);
1012 freq_s16 = (s16)freq;
1013 } else {
1014 freq = (intp->srch_range[demod] / 2000);
1015 if (intp->symbol_rate[demod] <= 5000000)
1016 freq += 80;
1017 else
1018 freq += 600;
1019
1020 freq = freq << 16;
1021 freq /= (intp->mclk / 1000);
1022 freq_s16 = (s16)freq;
1023 }
1024
1025 stv0900_write_bits(intp, CFR_UP1, MSB(freq_s16));
1026 stv0900_write_bits(intp, CFR_UP0, LSB(freq_s16));
1027 freq_s16 *= (-1);
1028 stv0900_write_bits(intp, CFR_LOW1, MSB(freq_s16));
1029 stv0900_write_bits(intp, CFR_LOW0, LSB(freq_s16));
1030 }
1031
1032 stv0900_write_reg(intp, CFRINIT1, 0);
1033 stv0900_write_reg(intp, CFRINIT0, 0);
1034
1035 if (intp->chip_id >= 0x20) {
1036 stv0900_write_reg(intp, EQUALCFG, 0x41);
1037 stv0900_write_reg(intp, FFECFG, 0x41);
1038
1039 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
1040 (intp->srch_standard[demod] == STV0900_SEARCH_DSS) ||
1041 (intp->srch_standard[demod] == STV0900_AUTO_SEARCH)) {
1042 stv0900_write_reg(intp, VITSCALE,
1043 0x82);
1044 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1045 }
1046 }
1047
1048 stv0900_write_reg(intp, SFRSTEP, 0x00);
1049 stv0900_write_reg(intp, TMGTHRISE, 0xe0);
1050 stv0900_write_reg(intp, TMGTHFALL, 0xc0);
1051 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1052 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1053 stv0900_write_bits(intp, S1S2_SEQUENTIAL, 0);
1054 stv0900_write_reg(intp, RTC, 0x88);
1055 if (intp->chip_id >= 0x20) {
1056 if (intp->symbol_rate[demod] < 2000000) {
1057 if (intp->chip_id <= 0x20)
1058 stv0900_write_reg(intp, CARFREQ, 0x39);
1059 else
1060 stv0900_write_reg(intp, CARFREQ, 0x89);
1061
1062 stv0900_write_reg(intp, CARHDR, 0x40);
1063 } else if (intp->symbol_rate[demod] < 10000000) {
1064 stv0900_write_reg(intp, CARFREQ, 0x4c);
1065 stv0900_write_reg(intp, CARHDR, 0x20);
1066 } else {
1067 stv0900_write_reg(intp, CARFREQ, 0x4b);
1068 stv0900_write_reg(intp, CARHDR, 0x20);
1069 }
1070
1071 } else {
1072 if (intp->symbol_rate[demod] < 10000000)
1073 stv0900_write_reg(intp, CARFREQ, 0xef);
1074 else
1075 stv0900_write_reg(intp, CARFREQ, 0xed);
1076 }
1077
1078 switch (intp->srch_algo[demod]) {
1079 case STV0900_WARM_START:
1080 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1081 stv0900_write_reg(intp, DMDISTATE, 0x18);
1082 break;
1083 case STV0900_COLD_START:
1084 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1085 stv0900_write_reg(intp, DMDISTATE, 0x15);
1086 break;
1087 default:
1088 break;
1089 }
1090}
1091
1092u8 stv0900_get_optim_carr_loop(s32 srate, enum fe_stv0900_modcode modcode,
1093 s32 pilot, u8 chip_id)
1094{
1095 u8 aclc_value = 0x29;
1096 s32 i;
1097 const struct stv0900_car_loop_optim *cls2, *cllqs2, *cllas2;
1098
1099 dprintk("%s\n", __func__);
1100
1101 if (chip_id <= 0x12) {
1102 cls2 = FE_STV0900_S2CarLoop;
1103 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1104 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1105 } else if (chip_id == 0x20) {
1106 cls2 = FE_STV0900_S2CarLoopCut20;
1107 cllqs2 = FE_STV0900_S2LowQPCarLoopCut20;
1108 cllas2 = FE_STV0900_S2APSKCarLoopCut20;
1109 } else {
1110 cls2 = FE_STV0900_S2CarLoopCut30;
1111 cllqs2 = FE_STV0900_S2LowQPCarLoopCut30;
1112 cllas2 = FE_STV0900_S2APSKCarLoopCut30;
1113 }
1114
1115 if (modcode < STV0900_QPSK_12) {
1116 i = 0;
1117 while ((i < 3) && (modcode != cllqs2[i].modcode))
1118 i++;
1119
1120 if (i >= 3)
1121 i = 2;
1122 } else {
1123 i = 0;
1124 while ((i < 14) && (modcode != cls2[i].modcode))
1125 i++;
1126
1127 if (i >= 14) {
1128 i = 0;
1129 while ((i < 11) && (modcode != cllas2[i].modcode))
1130 i++;
1131
1132 if (i >= 11)
1133 i = 10;
1134 }
1135 }
1136
1137 if (modcode <= STV0900_QPSK_25) {
1138 if (pilot) {
1139 if (srate <= 3000000)
1140 aclc_value = cllqs2[i].car_loop_pilots_on_2;
1141 else if (srate <= 7000000)
1142 aclc_value = cllqs2[i].car_loop_pilots_on_5;
1143 else if (srate <= 15000000)
1144 aclc_value = cllqs2[i].car_loop_pilots_on_10;
1145 else if (srate <= 25000000)
1146 aclc_value = cllqs2[i].car_loop_pilots_on_20;
1147 else
1148 aclc_value = cllqs2[i].car_loop_pilots_on_30;
1149 } else {
1150 if (srate <= 3000000)
1151 aclc_value = cllqs2[i].car_loop_pilots_off_2;
1152 else if (srate <= 7000000)
1153 aclc_value = cllqs2[i].car_loop_pilots_off_5;
1154 else if (srate <= 15000000)
1155 aclc_value = cllqs2[i].car_loop_pilots_off_10;
1156 else if (srate <= 25000000)
1157 aclc_value = cllqs2[i].car_loop_pilots_off_20;
1158 else
1159 aclc_value = cllqs2[i].car_loop_pilots_off_30;
1160 }
1161
1162 } else if (modcode <= STV0900_8PSK_910) {
1163 if (pilot) {
1164 if (srate <= 3000000)
1165 aclc_value = cls2[i].car_loop_pilots_on_2;
1166 else if (srate <= 7000000)
1167 aclc_value = cls2[i].car_loop_pilots_on_5;
1168 else if (srate <= 15000000)
1169 aclc_value = cls2[i].car_loop_pilots_on_10;
1170 else if (srate <= 25000000)
1171 aclc_value = cls2[i].car_loop_pilots_on_20;
1172 else
1173 aclc_value = cls2[i].car_loop_pilots_on_30;
1174 } else {
1175 if (srate <= 3000000)
1176 aclc_value = cls2[i].car_loop_pilots_off_2;
1177 else if (srate <= 7000000)
1178 aclc_value = cls2[i].car_loop_pilots_off_5;
1179 else if (srate <= 15000000)
1180 aclc_value = cls2[i].car_loop_pilots_off_10;
1181 else if (srate <= 25000000)
1182 aclc_value = cls2[i].car_loop_pilots_off_20;
1183 else
1184 aclc_value = cls2[i].car_loop_pilots_off_30;
1185 }
1186
1187 } else {
1188 if (srate <= 3000000)
1189 aclc_value = cllas2[i].car_loop_pilots_on_2;
1190 else if (srate <= 7000000)
1191 aclc_value = cllas2[i].car_loop_pilots_on_5;
1192 else if (srate <= 15000000)
1193 aclc_value = cllas2[i].car_loop_pilots_on_10;
1194 else if (srate <= 25000000)
1195 aclc_value = cllas2[i].car_loop_pilots_on_20;
1196 else
1197 aclc_value = cllas2[i].car_loop_pilots_on_30;
1198 }
1199
1200 return aclc_value;
1201}
1202
1203u8 stv0900_get_optim_short_carr_loop(s32 srate,
1204 enum fe_stv0900_modulation modulation,
1205 u8 chip_id)
1206{
1207 const struct stv0900_short_frames_car_loop_optim *s2scl;
1208 const struct stv0900_short_frames_car_loop_optim_vs_mod *s2sclc30;
1209 s32 mod_index = 0;
1210 u8 aclc_value = 0x0b;
1211
1212 dprintk("%s\n", __func__);
1213
1214 s2scl = FE_STV0900_S2ShortCarLoop;
1215 s2sclc30 = FE_STV0900_S2ShortCarLoopCut30;
1216
1217 switch (modulation) {
1218 case STV0900_QPSK:
1219 default:
1220 mod_index = 0;
1221 break;
1222 case STV0900_8PSK:
1223 mod_index = 1;
1224 break;
1225 case STV0900_16APSK:
1226 mod_index = 2;
1227 break;
1228 case STV0900_32APSK:
1229 mod_index = 3;
1230 break;
1231 }
1232
1233 if (chip_id >= 0x30) {
1234 if (srate <= 3000000)
1235 aclc_value = s2sclc30[mod_index].car_loop_2;
1236 else if (srate <= 7000000)
1237 aclc_value = s2sclc30[mod_index].car_loop_5;
1238 else if (srate <= 15000000)
1239 aclc_value = s2sclc30[mod_index].car_loop_10;
1240 else if (srate <= 25000000)
1241 aclc_value = s2sclc30[mod_index].car_loop_20;
1242 else
1243 aclc_value = s2sclc30[mod_index].car_loop_30;
1244
1245 } else if (chip_id >= 0x20) {
1246 if (srate <= 3000000)
1247 aclc_value = s2scl[mod_index].car_loop_cut20_2;
1248 else if (srate <= 7000000)
1249 aclc_value = s2scl[mod_index].car_loop_cut20_5;
1250 else if (srate <= 15000000)
1251 aclc_value = s2scl[mod_index].car_loop_cut20_10;
1252 else if (srate <= 25000000)
1253 aclc_value = s2scl[mod_index].car_loop_cut20_20;
1254 else
1255 aclc_value = s2scl[mod_index].car_loop_cut20_30;
1256
1257 } else {
1258 if (srate <= 3000000)
1259 aclc_value = s2scl[mod_index].car_loop_cut12_2;
1260 else if (srate <= 7000000)
1261 aclc_value = s2scl[mod_index].car_loop_cut12_5;
1262 else if (srate <= 15000000)
1263 aclc_value = s2scl[mod_index].car_loop_cut12_10;
1264 else if (srate <= 25000000)
1265 aclc_value = s2scl[mod_index].car_loop_cut12_20;
1266 else
1267 aclc_value = s2scl[mod_index].car_loop_cut12_30;
1268
1269 }
1270
1271 return aclc_value;
1272}
1273
1274static
1275enum fe_stv0900_error stv0900_st_dvbs2_single(struct stv0900_internal *intp,
1276 enum fe_stv0900_demod_mode LDPC_Mode,
1277 enum fe_stv0900_demod_num demod)
1278{
1279 enum fe_stv0900_error error = STV0900_NO_ERROR;
1280 s32 reg_ind;
1281
1282 dprintk("%s\n", __func__);
1283
1284 switch (LDPC_Mode) {
1285 case STV0900_DUAL:
1286 default:
1287 if ((intp->demod_mode != STV0900_DUAL)
1288 || (stv0900_get_bits(intp, F0900_DDEMOD) != 1)) {
1289 stv0900_write_reg(intp, R0900_GENCFG, 0x1d);
1290
1291 intp->demod_mode = STV0900_DUAL;
1292
1293 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1294 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1295
1296 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1297 stv0900_write_reg(intp,
1298 R0900_P1_MODCODLST0 + reg_ind,
1299 0xff);
1300 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1301 stv0900_write_reg(intp,
1302 R0900_P1_MODCODLST7 + reg_ind,
1303 0xcc);
1304
1305 stv0900_write_reg(intp, R0900_P1_MODCODLSTE, 0xff);
1306 stv0900_write_reg(intp, R0900_P1_MODCODLSTF, 0xcf);
1307
1308 for (reg_ind = 0; reg_ind < 7; reg_ind++)
1309 stv0900_write_reg(intp,
1310 R0900_P2_MODCODLST0 + reg_ind,
1311 0xff);
1312 for (reg_ind = 0; reg_ind < 8; reg_ind++)
1313 stv0900_write_reg(intp,
1314 R0900_P2_MODCODLST7 + reg_ind,
1315 0xcc);
1316
1317 stv0900_write_reg(intp, R0900_P2_MODCODLSTE, 0xff);
1318 stv0900_write_reg(intp, R0900_P2_MODCODLSTF, 0xcf);
1319 }
1320
1321 break;
1322 case STV0900_SINGLE:
1323 if (demod == STV0900_DEMOD_2) {
1324 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_1);
1325 stv0900_activate_s2_modcod_single(intp,
1326 STV0900_DEMOD_2);
1327 stv0900_write_reg(intp, R0900_GENCFG, 0x06);
1328 } else {
1329 stv0900_stop_all_s2_modcod(intp, STV0900_DEMOD_2);
1330 stv0900_activate_s2_modcod_single(intp,
1331 STV0900_DEMOD_1);
1332 stv0900_write_reg(intp, R0900_GENCFG, 0x04);
1333 }
1334
1335 intp->demod_mode = STV0900_SINGLE;
1336
1337 stv0900_write_bits(intp, F0900_FRESFEC, 1);
1338 stv0900_write_bits(intp, F0900_FRESFEC, 0);
1339 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 1);
1340 stv0900_write_bits(intp, F0900_P1_ALGOSWRST, 0);
1341 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 1);
1342 stv0900_write_bits(intp, F0900_P2_ALGOSWRST, 0);
1343 break;
1344 }
1345
1346 return error;
1347}
1348
1349static enum fe_stv0900_error stv0900_init_internal(struct dvb_frontend *fe,
1350 struct stv0900_init_params *p_init)
1351{
1352 struct stv0900_state *state = fe->demodulator_priv;
1353 enum fe_stv0900_error error = STV0900_NO_ERROR;
1354 enum fe_stv0900_error demodError = STV0900_NO_ERROR;
1355 struct stv0900_internal *intp = NULL;
1356 int selosci, i;
1357
1358 struct stv0900_inode *temp_int = find_inode(state->i2c_adap,
1359 state->config->demod_address);
1360
1361 dprintk("%s\n", __func__);
1362
1363 if ((temp_int != NULL) && (p_init->demod_mode == STV0900_DUAL)) {
1364 state->internal = temp_int->internal;
1365 (state->internal->dmds_used)++;
1366 dprintk("%s: Find Internal Structure!\n", __func__);
1367 return STV0900_NO_ERROR;
1368 } else {
1369 state->internal = kmalloc(sizeof(struct stv0900_internal),
1370 GFP_KERNEL);
1371 if (state->internal == NULL)
1372 return STV0900_INVALID_HANDLE;
1373 temp_int = append_internal(state->internal);
1374 if (temp_int == NULL) {
1375 kfree(state->internal);
1376 state->internal = NULL;
1377 return STV0900_INVALID_HANDLE;
1378 }
1379 state->internal->dmds_used = 1;
1380 state->internal->i2c_adap = state->i2c_adap;
1381 state->internal->i2c_addr = state->config->demod_address;
1382 state->internal->clkmode = state->config->clkmode;
1383 state->internal->errs = STV0900_NO_ERROR;
1384 dprintk("%s: Create New Internal Structure!\n", __func__);
1385 }
1386
1387 if (state->internal == NULL) {
1388 error = STV0900_INVALID_HANDLE;
1389 return error;
1390 }
1391
1392 demodError = stv0900_initialize(state->internal);
1393 if (demodError == STV0900_NO_ERROR) {
1394 error = STV0900_NO_ERROR;
1395 } else {
1396 if (demodError == STV0900_INVALID_HANDLE)
1397 error = STV0900_INVALID_HANDLE;
1398 else
1399 error = STV0900_I2C_ERROR;
1400
1401 return error;
1402 }
1403
1404 intp = state->internal;
1405
1406 intp->demod_mode = p_init->demod_mode;
1407 stv0900_st_dvbs2_single(intp, intp->demod_mode, STV0900_DEMOD_1);
1408 intp->chip_id = stv0900_read_reg(intp, R0900_MID);
1409 intp->rolloff = p_init->rolloff;
1410 intp->quartz = p_init->dmd_ref_clk;
1411
1412 stv0900_write_bits(intp, F0900_P1_ROLLOFF_CONTROL, p_init->rolloff);
1413 stv0900_write_bits(intp, F0900_P2_ROLLOFF_CONTROL, p_init->rolloff);
1414
1415 intp->ts_config = p_init->ts_config;
1416 if (intp->ts_config == NULL)
1417 stv0900_set_ts_parallel_serial(intp,
1418 p_init->path1_ts_clock,
1419 p_init->path2_ts_clock);
1420 else {
1421 for (i = 0; intp->ts_config[i].addr != 0xffff; i++)
1422 stv0900_write_reg(intp,
1423 intp->ts_config[i].addr,
1424 intp->ts_config[i].val);
1425
1426 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 1);
1427 stv0900_write_bits(intp, F0900_P2_RST_HWARE, 0);
1428 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 1);
1429 stv0900_write_bits(intp, F0900_P1_RST_HWARE, 0);
1430 }
1431
1432 intp->tuner_type[0] = p_init->tuner1_type;
1433 intp->tuner_type[1] = p_init->tuner2_type;
1434
1435 switch (p_init->tuner1_type) {
1436 case 3:
1437 stv0900_write_reg(intp, R0900_P1_TNRCFG, 0x3c);
1438 stv0900_write_reg(intp, R0900_P1_TNRCFG2, 0x86);
1439 stv0900_write_reg(intp, R0900_P1_TNRCFG3, 0x18);
1440 stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27);
1441 stv0900_write_reg(intp, R0900_P1_TNRSTEPS, 0x05);
1442 stv0900_write_reg(intp, R0900_P1_TNRGAIN, 0x17);
1443 stv0900_write_reg(intp, R0900_P1_TNRADJ, 0x1f);
1444 stv0900_write_reg(intp, R0900_P1_TNRCTL2, 0x0);
1445 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 3);
1446 break;
1447
1448 default:
1449 stv0900_write_bits(intp, F0900_P1_TUN_TYPE, 6);
1450 break;
1451 }
1452
1453 stv0900_write_bits(intp, F0900_P1_TUN_MADDRESS, p_init->tun1_maddress);
1454 switch (p_init->tuner1_adc) {
1455 case 1:
1456 stv0900_write_reg(intp, R0900_TSTTNR1, 0x26);
1457 break;
1458 default:
1459 break;
1460 }
1461
1462 stv0900_write_reg(intp, R0900_P1_TNRLD, 1);
1463
1464
1465 switch (p_init->tuner2_type) {
1466 case 3:
1467 stv0900_write_reg(intp, R0900_P2_TNRCFG, 0x3c);
1468 stv0900_write_reg(intp, R0900_P2_TNRCFG2, 0x86);
1469 stv0900_write_reg(intp, R0900_P2_TNRCFG3, 0x18);
1470 stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27);
1471 stv0900_write_reg(intp, R0900_P2_TNRSTEPS, 0x05);
1472 stv0900_write_reg(intp, R0900_P2_TNRGAIN, 0x17);
1473 stv0900_write_reg(intp, R0900_P2_TNRADJ, 0x1f);
1474 stv0900_write_reg(intp, R0900_P2_TNRCTL2, 0x0);
1475 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 3);
1476 break;
1477
1478 default:
1479 stv0900_write_bits(intp, F0900_P2_TUN_TYPE, 6);
1480 break;
1481 }
1482
1483 stv0900_write_bits(intp, F0900_P2_TUN_MADDRESS, p_init->tun2_maddress);
1484 switch (p_init->tuner2_adc) {
1485 case 1:
1486 stv0900_write_reg(intp, R0900_TSTTNR3, 0x26);
1487 break;
1488 default:
1489 break;
1490 }
1491
1492 stv0900_write_reg(intp, R0900_P2_TNRLD, 1);
1493
1494 stv0900_write_bits(intp, F0900_P1_TUN_IQSWAP, p_init->tun1_iq_inv);
1495 stv0900_write_bits(intp, F0900_P2_TUN_IQSWAP, p_init->tun2_iq_inv);
1496 stv0900_set_mclk(intp, 135000000);
1497 msleep(3);
1498
1499 switch (intp->clkmode) {
1500 case 0:
1501 case 2:
1502 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | intp->clkmode);
1503 break;
1504 default:
1505 selosci = 0x02 & stv0900_read_reg(intp, R0900_SYNTCTRL);
1506 stv0900_write_reg(intp, R0900_SYNTCTRL, 0x20 | selosci);
1507 break;
1508 }
1509 msleep(3);
1510
1511 intp->mclk = stv0900_get_mclk_freq(intp, intp->quartz);
1512 if (intp->errs)
1513 error = STV0900_I2C_ERROR;
1514
1515 return error;
1516}
1517
1518static int stv0900_status(struct stv0900_internal *intp,
1519 enum fe_stv0900_demod_num demod)
1520{
1521 enum fe_stv0900_search_state demod_state;
1522 int locked = FALSE;
1523 u8 tsbitrate0_val, tsbitrate1_val;
1524 s32 bitrate;
1525
1526 demod_state = stv0900_get_bits(intp, HEADER_MODE);
1527 switch (demod_state) {
1528 case STV0900_SEARCH:
1529 case STV0900_PLH_DETECTED:
1530 default:
1531 locked = FALSE;
1532 break;
1533 case STV0900_DVBS2_FOUND:
1534 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1535 stv0900_get_bits(intp, PKTDELIN_LOCK) &&
1536 stv0900_get_bits(intp, TSFIFO_LINEOK);
1537 break;
1538 case STV0900_DVBS_FOUND:
1539 locked = stv0900_get_bits(intp, LOCK_DEFINITIF) &&
1540 stv0900_get_bits(intp, LOCKEDVIT) &&
1541 stv0900_get_bits(intp, TSFIFO_LINEOK);
1542 break;
1543 }
1544
1545 dprintk("%s: locked = %d\n", __func__, locked);
1546
1547 if (stvdebug) {
1548
1549 tsbitrate0_val = stv0900_read_reg(intp, TSBITRATE0);
1550 tsbitrate1_val = stv0900_read_reg(intp, TSBITRATE1);
1551
1552 bitrate = (stv0900_get_mclk_freq(intp, intp->quartz)/1000000)
1553 * (tsbitrate1_val << 8 | tsbitrate0_val);
1554 bitrate /= 16384;
1555 dprintk("TS bitrate = %d Mbit/sec \n", bitrate);
1556 };
1557
1558 return locked;
1559}
1560
1561static enum dvbfe_search stv0900_search(struct dvb_frontend *fe)
1562{
1563 struct stv0900_state *state = fe->demodulator_priv;
1564 struct stv0900_internal *intp = state->internal;
1565 enum fe_stv0900_demod_num demod = state->demod;
1566 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
1567
1568 struct stv0900_search_params p_search;
1569 struct stv0900_signal_info p_result = intp->result[demod];
1570
1571 enum fe_stv0900_error error = STV0900_NO_ERROR;
1572
1573 dprintk("%s: ", __func__);
1574
1575 if (!(INRANGE(100000, c->symbol_rate, 70000000)))
1576 return DVBFE_ALGO_SEARCH_FAILED;
1577
1578 if (state->config->set_ts_params)
1579 state->config->set_ts_params(fe, 0);
1580
1581 p_result.locked = FALSE;
1582 p_search.path = demod;
1583 p_search.frequency = c->frequency;
1584 p_search.symbol_rate = c->symbol_rate;
1585 p_search.search_range = 10000000;
1586 p_search.fec = STV0900_FEC_UNKNOWN;
1587 p_search.standard = STV0900_AUTO_SEARCH;
1588 p_search.iq_inversion = STV0900_IQ_AUTO;
1589 p_search.search_algo = STV0900_BLIND_SEARCH;
1590
1591 if (c->delivery_system == SYS_DVBS)
1592 p_search.standard = STV0900_SEARCH_DVBS1;
1593
1594 intp->srch_standard[demod] = p_search.standard;
1595 intp->symbol_rate[demod] = p_search.symbol_rate;
1596 intp->srch_range[demod] = p_search.search_range;
1597 intp->freq[demod] = p_search.frequency;
1598 intp->srch_algo[demod] = p_search.search_algo;
1599 intp->srch_iq_inv[demod] = p_search.iq_inversion;
1600 intp->fec[demod] = p_search.fec;
1601 if ((stv0900_algo(fe) == STV0900_RANGEOK) &&
1602 (intp->errs == STV0900_NO_ERROR)) {
1603 p_result.locked = intp->result[demod].locked;
1604 p_result.standard = intp->result[demod].standard;
1605 p_result.frequency = intp->result[demod].frequency;
1606 p_result.symbol_rate = intp->result[demod].symbol_rate;
1607 p_result.fec = intp->result[demod].fec;
1608 p_result.modcode = intp->result[demod].modcode;
1609 p_result.pilot = intp->result[demod].pilot;
1610 p_result.frame_len = intp->result[demod].frame_len;
1611 p_result.spectrum = intp->result[demod].spectrum;
1612 p_result.rolloff = intp->result[demod].rolloff;
1613 p_result.modulation = intp->result[demod].modulation;
1614 } else {
1615 p_result.locked = FALSE;
1616 switch (intp->err[demod]) {
1617 case STV0900_I2C_ERROR:
1618 error = STV0900_I2C_ERROR;
1619 break;
1620 case STV0900_NO_ERROR:
1621 default:
1622 error = STV0900_SEARCH_FAILED;
1623 break;
1624 }
1625 }
1626
1627 if ((p_result.locked == TRUE) && (error == STV0900_NO_ERROR)) {
1628 dprintk("Search Success\n");
1629 return DVBFE_ALGO_SEARCH_SUCCESS;
1630 } else {
1631 dprintk("Search Fail\n");
1632 return DVBFE_ALGO_SEARCH_FAILED;
1633 }
1634
1635}
1636
1637static int stv0900_read_status(struct dvb_frontend *fe, enum fe_status *status)
1638{
1639 struct stv0900_state *state = fe->demodulator_priv;
1640
1641 dprintk("%s: ", __func__);
1642
1643 if ((stv0900_status(state->internal, state->demod)) == TRUE) {
1644 dprintk("DEMOD LOCK OK\n");
1645 *status = FE_HAS_CARRIER
1646 | FE_HAS_VITERBI
1647 | FE_HAS_SYNC
1648 | FE_HAS_LOCK;
1649 if (state->config->set_lock_led)
1650 state->config->set_lock_led(fe, 1);
1651 } else {
1652 *status = 0;
1653 if (state->config->set_lock_led)
1654 state->config->set_lock_led(fe, 0);
1655 dprintk("DEMOD LOCK FAIL\n");
1656 }
1657
1658 return 0;
1659}
1660
1661static int stv0900_stop_ts(struct dvb_frontend *fe, int stop_ts)
1662{
1663
1664 struct stv0900_state *state = fe->demodulator_priv;
1665 struct stv0900_internal *intp = state->internal;
1666 enum fe_stv0900_demod_num demod = state->demod;
1667
1668 if (stop_ts == TRUE)
1669 stv0900_write_bits(intp, RST_HWARE, 1);
1670 else
1671 stv0900_write_bits(intp, RST_HWARE, 0);
1672
1673 return 0;
1674}
1675
1676static int stv0900_diseqc_init(struct dvb_frontend *fe)
1677{
1678 struct stv0900_state *state = fe->demodulator_priv;
1679 struct stv0900_internal *intp = state->internal;
1680 enum fe_stv0900_demod_num demod = state->demod;
1681
1682 stv0900_write_bits(intp, DISTX_MODE, state->config->diseqc_mode);
1683 stv0900_write_bits(intp, DISEQC_RESET, 1);
1684 stv0900_write_bits(intp, DISEQC_RESET, 0);
1685
1686 return 0;
1687}
1688
1689static int stv0900_init(struct dvb_frontend *fe)
1690{
1691 dprintk("%s\n", __func__);
1692
1693 stv0900_stop_ts(fe, 1);
1694 stv0900_diseqc_init(fe);
1695
1696 return 0;
1697}
1698
1699static int stv0900_diseqc_send(struct stv0900_internal *intp , u8 *data,
1700 u32 NbData, enum fe_stv0900_demod_num demod)
1701{
1702 s32 i = 0;
1703
1704 stv0900_write_bits(intp, DIS_PRECHARGE, 1);
1705 while (i < NbData) {
1706 while (stv0900_get_bits(intp, FIFO_FULL))
1707 ;
1708 stv0900_write_reg(intp, DISTXDATA, data[i]);
1709 i++;
1710 }
1711
1712 stv0900_write_bits(intp, DIS_PRECHARGE, 0);
1713 i = 0;
1714 while ((stv0900_get_bits(intp, TX_IDLE) != 1) && (i < 10)) {
1715 msleep(10);
1716 i++;
1717 }
1718
1719 return 0;
1720}
1721
1722static int stv0900_send_master_cmd(struct dvb_frontend *fe,
1723 struct dvb_diseqc_master_cmd *cmd)
1724{
1725 struct stv0900_state *state = fe->demodulator_priv;
1726
1727 return stv0900_diseqc_send(state->internal,
1728 cmd->msg,
1729 cmd->msg_len,
1730 state->demod);
1731}
1732
1733static int stv0900_send_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t burst)
1734{
1735 struct stv0900_state *state = fe->demodulator_priv;
1736 struct stv0900_internal *intp = state->internal;
1737 enum fe_stv0900_demod_num demod = state->demod;
1738 u8 data;
1739
1740
1741 switch (burst) {
1742 case SEC_MINI_A:
1743 stv0900_write_bits(intp, DISTX_MODE, 3);
1744 data = 0x00;
1745 stv0900_diseqc_send(intp, &data, 1, state->demod);
1746 break;
1747 case SEC_MINI_B:
1748 stv0900_write_bits(intp, DISTX_MODE, 2);
1749 data = 0xff;
1750 stv0900_diseqc_send(intp, &data, 1, state->demod);
1751 break;
1752 }
1753
1754 return 0;
1755}
1756
1757static int stv0900_recv_slave_reply(struct dvb_frontend *fe,
1758 struct dvb_diseqc_slave_reply *reply)
1759{
1760 struct stv0900_state *state = fe->demodulator_priv;
1761 struct stv0900_internal *intp = state->internal;
1762 enum fe_stv0900_demod_num demod = state->demod;
1763 s32 i = 0;
1764
1765 reply->msg_len = 0;
1766
1767 while ((stv0900_get_bits(intp, RX_END) != 1) && (i < 10)) {
1768 msleep(10);
1769 i++;
1770 }
1771
1772 if (stv0900_get_bits(intp, RX_END)) {
1773 reply->msg_len = stv0900_get_bits(intp, FIFO_BYTENBR);
1774
1775 for (i = 0; i < reply->msg_len; i++)
1776 reply->msg[i] = stv0900_read_reg(intp, DISRXDATA);
1777 }
1778
1779 return 0;
1780}
1781
1782static int stv0900_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t toneoff)
1783{
1784 struct stv0900_state *state = fe->demodulator_priv;
1785 struct stv0900_internal *intp = state->internal;
1786 enum fe_stv0900_demod_num demod = state->demod;
1787
1788 dprintk("%s: %s\n", __func__, ((toneoff == 0) ? "On" : "Off"));
1789
1790 switch (toneoff) {
1791 case SEC_TONE_ON:
1792
1793 stv0900_write_bits(intp, DISTX_MODE, 0);
1794 stv0900_write_bits(intp, DISEQC_RESET, 1);
1795
1796 stv0900_write_bits(intp, DISEQC_RESET, 0);
1797 break;
1798 case SEC_TONE_OFF:
1799
1800
1801 stv0900_write_bits(intp, DISTX_MODE,
1802 state->config->diseqc_mode);
1803
1804 stv0900_write_bits(intp, DISEQC_RESET, 1);
1805 stv0900_write_bits(intp, DISEQC_RESET, 0);
1806 break;
1807 default:
1808 return -EINVAL;
1809 }
1810
1811 return 0;
1812}
1813
1814static void stv0900_release(struct dvb_frontend *fe)
1815{
1816 struct stv0900_state *state = fe->demodulator_priv;
1817
1818 dprintk("%s\n", __func__);
1819
1820 if (state->config->set_lock_led)
1821 state->config->set_lock_led(fe, 0);
1822
1823 if ((--(state->internal->dmds_used)) <= 0) {
1824
1825 dprintk("%s: Actually removing\n", __func__);
1826
1827 remove_inode(state->internal);
1828 kfree(state->internal);
1829 }
1830
1831 kfree(state);
1832}
1833
1834static int stv0900_sleep(struct dvb_frontend *fe)
1835{
1836 struct stv0900_state *state = fe->demodulator_priv;
1837
1838 dprintk("%s\n", __func__);
1839
1840 if (state->config->set_lock_led)
1841 state->config->set_lock_led(fe, 0);
1842
1843 return 0;
1844}
1845
1846static int stv0900_get_frontend(struct dvb_frontend *fe)
1847{
1848 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1849 struct stv0900_state *state = fe->demodulator_priv;
1850 struct stv0900_internal *intp = state->internal;
1851 enum fe_stv0900_demod_num demod = state->demod;
1852 struct stv0900_signal_info p_result = intp->result[demod];
1853
1854 p->frequency = p_result.locked ? p_result.frequency : 0;
1855 p->symbol_rate = p_result.locked ? p_result.symbol_rate : 0;
1856 return 0;
1857}
1858
1859static struct dvb_frontend_ops stv0900_ops = {
1860 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },
1861 .info = {
1862 .name = "STV0900 frontend",
1863 .frequency_min = 950000,
1864 .frequency_max = 2150000,
1865 .frequency_stepsize = 125,
1866 .frequency_tolerance = 0,
1867 .symbol_rate_min = 1000000,
1868 .symbol_rate_max = 45000000,
1869 .symbol_rate_tolerance = 500,
1870 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
1871 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
1872 FE_CAN_FEC_7_8 | FE_CAN_QPSK |
1873 FE_CAN_2G_MODULATION |
1874 FE_CAN_FEC_AUTO
1875 },
1876 .release = stv0900_release,
1877 .init = stv0900_init,
1878 .get_frontend = stv0900_get_frontend,
1879 .sleep = stv0900_sleep,
1880 .get_frontend_algo = stv0900_frontend_algo,
1881 .i2c_gate_ctrl = stv0900_i2c_gate_ctrl,
1882 .diseqc_send_master_cmd = stv0900_send_master_cmd,
1883 .diseqc_send_burst = stv0900_send_burst,
1884 .diseqc_recv_slave_reply = stv0900_recv_slave_reply,
1885 .set_tone = stv0900_set_tone,
1886 .search = stv0900_search,
1887 .read_status = stv0900_read_status,
1888 .read_ber = stv0900_read_ber,
1889 .read_signal_strength = stv0900_read_signal_strength,
1890 .read_snr = stv0900_read_snr,
1891 .read_ucblocks = stv0900_read_ucblocks,
1892};
1893
1894struct dvb_frontend *stv0900_attach(const struct stv0900_config *config,
1895 struct i2c_adapter *i2c,
1896 int demod)
1897{
1898 struct stv0900_state *state = NULL;
1899 struct stv0900_init_params init_params;
1900 enum fe_stv0900_error err_stv0900;
1901
1902 state = kzalloc(sizeof(struct stv0900_state), GFP_KERNEL);
1903 if (state == NULL)
1904 goto error;
1905
1906 state->demod = demod;
1907 state->config = config;
1908 state->i2c_adap = i2c;
1909
1910 memcpy(&state->frontend.ops, &stv0900_ops,
1911 sizeof(struct dvb_frontend_ops));
1912 state->frontend.demodulator_priv = state;
1913
1914 switch (demod) {
1915 case 0:
1916 case 1:
1917 init_params.dmd_ref_clk = config->xtal;
1918 init_params.demod_mode = config->demod_mode;
1919 init_params.rolloff = STV0900_35;
1920 init_params.path1_ts_clock = config->path1_mode;
1921 init_params.tun1_maddress = config->tun1_maddress;
1922 init_params.tun1_iq_inv = STV0900_IQ_NORMAL;
1923 init_params.tuner1_adc = config->tun1_adc;
1924 init_params.tuner1_type = config->tun1_type;
1925 init_params.path2_ts_clock = config->path2_mode;
1926 init_params.ts_config = config->ts_config_regs;
1927 init_params.tun2_maddress = config->tun2_maddress;
1928 init_params.tuner2_adc = config->tun2_adc;
1929 init_params.tuner2_type = config->tun2_type;
1930 init_params.tun2_iq_inv = STV0900_IQ_SWAPPED;
1931
1932 err_stv0900 = stv0900_init_internal(&state->frontend,
1933 &init_params);
1934
1935 if (err_stv0900)
1936 goto error;
1937
1938 break;
1939 default:
1940 goto error;
1941 break;
1942 }
1943
1944 dprintk("%s: Attaching STV0900 demodulator(%d) \n", __func__, demod);
1945 return &state->frontend;
1946
1947error:
1948 dprintk("%s: Failed to attach STV0900 demodulator(%d) \n",
1949 __func__, demod);
1950 kfree(state);
1951 return NULL;
1952}
1953EXPORT_SYMBOL(stv0900_attach);
1954
1955MODULE_PARM_DESC(debug, "Set debug");
1956
1957MODULE_AUTHOR("Igor M. Liplianin");
1958MODULE_DESCRIPTION("ST STV0900 frontend");
1959MODULE_LICENSE("GPL");
1960
