1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include <linux/if_ether.h>
29#include <linux/delay.h>
30
31#include "e1000_mac.h"
32#include "e1000_nvm.h"
33
34
35
36
37
38
39
40
41static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
42{
43 *eecd = *eecd | E1000_EECD_SK;
44 wr32(E1000_EECD, *eecd);
45 wrfl();
46 udelay(hw->nvm.delay_usec);
47}
48
49
50
51
52
53
54
55
56static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
57{
58 *eecd = *eecd & ~E1000_EECD_SK;
59 wr32(E1000_EECD, *eecd);
60 wrfl();
61 udelay(hw->nvm.delay_usec);
62}
63
64
65
66
67
68
69
70
71
72
73
74static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
75{
76 struct e1000_nvm_info *nvm = &hw->nvm;
77 u32 eecd = rd32(E1000_EECD);
78 u32 mask;
79
80 mask = 0x01 << (count - 1);
81 if (nvm->type == e1000_nvm_eeprom_spi)
82 eecd |= E1000_EECD_DO;
83
84 do {
85 eecd &= ~E1000_EECD_DI;
86
87 if (data & mask)
88 eecd |= E1000_EECD_DI;
89
90 wr32(E1000_EECD, eecd);
91 wrfl();
92
93 udelay(nvm->delay_usec);
94
95 igb_raise_eec_clk(hw, &eecd);
96 igb_lower_eec_clk(hw, &eecd);
97
98 mask >>= 1;
99 } while (mask);
100
101 eecd &= ~E1000_EECD_DI;
102 wr32(E1000_EECD, eecd);
103}
104
105
106
107
108
109
110
111
112
113
114
115
116static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
117{
118 u32 eecd;
119 u32 i;
120 u16 data;
121
122 eecd = rd32(E1000_EECD);
123
124 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
125 data = 0;
126
127 for (i = 0; i < count; i++) {
128 data <<= 1;
129 igb_raise_eec_clk(hw, &eecd);
130
131 eecd = rd32(E1000_EECD);
132
133 eecd &= ~E1000_EECD_DI;
134 if (eecd & E1000_EECD_DO)
135 data |= 1;
136
137 igb_lower_eec_clk(hw, &eecd);
138 }
139
140 return data;
141}
142
143
144
145
146
147
148
149
150
151static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
152{
153 u32 attempts = 100000;
154 u32 i, reg = 0;
155 s32 ret_val = -E1000_ERR_NVM;
156
157 for (i = 0; i < attempts; i++) {
158 if (ee_reg == E1000_NVM_POLL_READ)
159 reg = rd32(E1000_EERD);
160 else
161 reg = rd32(E1000_EEWR);
162
163 if (reg & E1000_NVM_RW_REG_DONE) {
164 ret_val = 0;
165 break;
166 }
167
168 udelay(5);
169 }
170
171 return ret_val;
172}
173
174
175
176
177
178
179
180
181
182s32 igb_acquire_nvm(struct e1000_hw *hw)
183{
184 u32 eecd = rd32(E1000_EECD);
185 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
186 s32 ret_val = 0;
187
188
189 wr32(E1000_EECD, eecd | E1000_EECD_REQ);
190 eecd = rd32(E1000_EECD);
191
192 while (timeout) {
193 if (eecd & E1000_EECD_GNT)
194 break;
195 udelay(5);
196 eecd = rd32(E1000_EECD);
197 timeout--;
198 }
199
200 if (!timeout) {
201 eecd &= ~E1000_EECD_REQ;
202 wr32(E1000_EECD, eecd);
203 hw_dbg("Could not acquire NVM grant\n");
204 ret_val = -E1000_ERR_NVM;
205 }
206
207 return ret_val;
208}
209
210
211
212
213
214
215
216static void igb_standby_nvm(struct e1000_hw *hw)
217{
218 struct e1000_nvm_info *nvm = &hw->nvm;
219 u32 eecd = rd32(E1000_EECD);
220
221 if (nvm->type == e1000_nvm_eeprom_spi) {
222
223 eecd |= E1000_EECD_CS;
224 wr32(E1000_EECD, eecd);
225 wrfl();
226 udelay(nvm->delay_usec);
227 eecd &= ~E1000_EECD_CS;
228 wr32(E1000_EECD, eecd);
229 wrfl();
230 udelay(nvm->delay_usec);
231 }
232}
233
234
235
236
237
238
239
240static void e1000_stop_nvm(struct e1000_hw *hw)
241{
242 u32 eecd;
243
244 eecd = rd32(E1000_EECD);
245 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
246
247 eecd |= E1000_EECD_CS;
248 igb_lower_eec_clk(hw, &eecd);
249 }
250}
251
252
253
254
255
256
257
258void igb_release_nvm(struct e1000_hw *hw)
259{
260 u32 eecd;
261
262 e1000_stop_nvm(hw);
263
264 eecd = rd32(E1000_EECD);
265 eecd &= ~E1000_EECD_REQ;
266 wr32(E1000_EECD, eecd);
267}
268
269
270
271
272
273
274
275static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
276{
277 struct e1000_nvm_info *nvm = &hw->nvm;
278 u32 eecd = rd32(E1000_EECD);
279 s32 ret_val = 0;
280 u16 timeout = 0;
281 u8 spi_stat_reg;
282
283
284 if (nvm->type == e1000_nvm_eeprom_spi) {
285
286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
287 wr32(E1000_EECD, eecd);
288 wrfl();
289 udelay(1);
290 timeout = NVM_MAX_RETRY_SPI;
291
292
293
294
295
296
297
298 while (timeout) {
299 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
300 hw->nvm.opcode_bits);
301 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
302 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
303 break;
304
305 udelay(5);
306 igb_standby_nvm(hw);
307 timeout--;
308 }
309
310 if (!timeout) {
311 hw_dbg("SPI NVM Status error\n");
312 ret_val = -E1000_ERR_NVM;
313 goto out;
314 }
315 }
316
317out:
318 return ret_val;
319}
320
321
322
323
324
325
326
327
328
329
330s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
331{
332 struct e1000_nvm_info *nvm = &hw->nvm;
333 u32 i = 0;
334 s32 ret_val;
335 u16 word_in;
336 u8 read_opcode = NVM_READ_OPCODE_SPI;
337
338
339
340
341
342 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
343 (words == 0)) {
344 hw_dbg("nvm parameter(s) out of bounds\n");
345 ret_val = -E1000_ERR_NVM;
346 goto out;
347 }
348
349 ret_val = nvm->ops.acquire(hw);
350 if (ret_val)
351 goto out;
352
353 ret_val = igb_ready_nvm_eeprom(hw);
354 if (ret_val)
355 goto release;
356
357 igb_standby_nvm(hw);
358
359 if ((nvm->address_bits == 8) && (offset >= 128))
360 read_opcode |= NVM_A8_OPCODE_SPI;
361
362
363 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
364 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
365
366
367
368
369
370
371 for (i = 0; i < words; i++) {
372 word_in = igb_shift_in_eec_bits(hw, 16);
373 data[i] = (word_in >> 8) | (word_in << 8);
374 }
375
376release:
377 nvm->ops.release(hw);
378
379out:
380 return ret_val;
381}
382
383
384
385
386
387
388
389
390
391
392s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
393{
394 struct e1000_nvm_info *nvm = &hw->nvm;
395 u32 i, eerd = 0;
396 s32 ret_val = 0;
397
398
399
400
401
402 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
403 (words == 0)) {
404 hw_dbg("nvm parameter(s) out of bounds\n");
405 ret_val = -E1000_ERR_NVM;
406 goto out;
407 }
408
409 for (i = 0; i < words; i++) {
410 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
411 E1000_NVM_RW_REG_START;
412
413 wr32(E1000_EERD, eerd);
414 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
415 if (ret_val)
416 break;
417
418 data[i] = (rd32(E1000_EERD) >>
419 E1000_NVM_RW_REG_DATA);
420 }
421
422out:
423 return ret_val;
424}
425
426
427
428
429
430
431
432
433
434
435
436
437
438s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
439{
440 struct e1000_nvm_info *nvm = &hw->nvm;
441 s32 ret_val;
442 u16 widx = 0;
443
444
445
446
447
448 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
449 (words == 0)) {
450 hw_dbg("nvm parameter(s) out of bounds\n");
451 ret_val = -E1000_ERR_NVM;
452 goto out;
453 }
454
455 ret_val = hw->nvm.ops.acquire(hw);
456 if (ret_val)
457 goto out;
458
459 msleep(10);
460
461 while (widx < words) {
462 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
463
464 ret_val = igb_ready_nvm_eeprom(hw);
465 if (ret_val)
466 goto release;
467
468 igb_standby_nvm(hw);
469
470
471 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
472 nvm->opcode_bits);
473
474 igb_standby_nvm(hw);
475
476
477
478
479
480 if ((nvm->address_bits == 8) && (offset >= 128))
481 write_opcode |= NVM_A8_OPCODE_SPI;
482
483
484 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
485 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
486 nvm->address_bits);
487
488
489 while (widx < words) {
490 u16 word_out = data[widx];
491 word_out = (word_out >> 8) | (word_out << 8);
492 igb_shift_out_eec_bits(hw, word_out, 16);
493 widx++;
494
495 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
496 igb_standby_nvm(hw);
497 break;
498 }
499 }
500 }
501
502 msleep(10);
503release:
504 hw->nvm.ops.release(hw);
505
506out:
507 return ret_val;
508}
509
510
511
512
513
514
515
516
517
518
519s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
520{
521 s32 ret_val;
522 u16 nvm_data;
523 u16 pointer;
524 u16 offset;
525 u16 length;
526
527 if (part_num == NULL) {
528 hw_dbg("PBA string buffer was null\n");
529 ret_val = E1000_ERR_INVALID_ARGUMENT;
530 goto out;
531 }
532
533 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
534 if (ret_val) {
535 hw_dbg("NVM Read Error\n");
536 goto out;
537 }
538
539 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
540 if (ret_val) {
541 hw_dbg("NVM Read Error\n");
542 goto out;
543 }
544
545
546
547
548
549
550 if (nvm_data != NVM_PBA_PTR_GUARD) {
551 hw_dbg("NVM PBA number is not stored as string\n");
552
553
554 if (part_num_size < 11) {
555 hw_dbg("PBA string buffer too small\n");
556 return E1000_ERR_NO_SPACE;
557 }
558
559
560 part_num[0] = (nvm_data >> 12) & 0xF;
561 part_num[1] = (nvm_data >> 8) & 0xF;
562 part_num[2] = (nvm_data >> 4) & 0xF;
563 part_num[3] = nvm_data & 0xF;
564 part_num[4] = (pointer >> 12) & 0xF;
565 part_num[5] = (pointer >> 8) & 0xF;
566 part_num[6] = '-';
567 part_num[7] = 0;
568 part_num[8] = (pointer >> 4) & 0xF;
569 part_num[9] = pointer & 0xF;
570
571
572 part_num[10] = '\0';
573
574
575 for (offset = 0; offset < 10; offset++) {
576 if (part_num[offset] < 0xA)
577 part_num[offset] += '0';
578 else if (part_num[offset] < 0x10)
579 part_num[offset] += 'A' - 0xA;
580 }
581
582 goto out;
583 }
584
585 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
586 if (ret_val) {
587 hw_dbg("NVM Read Error\n");
588 goto out;
589 }
590
591 if (length == 0xFFFF || length == 0) {
592 hw_dbg("NVM PBA number section invalid length\n");
593 ret_val = E1000_ERR_NVM_PBA_SECTION;
594 goto out;
595 }
596
597 if (part_num_size < (((u32)length * 2) - 1)) {
598 hw_dbg("PBA string buffer too small\n");
599 ret_val = E1000_ERR_NO_SPACE;
600 goto out;
601 }
602
603
604 pointer++;
605 length--;
606
607 for (offset = 0; offset < length; offset++) {
608 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
609 if (ret_val) {
610 hw_dbg("NVM Read Error\n");
611 goto out;
612 }
613 part_num[offset * 2] = (u8)(nvm_data >> 8);
614 part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
615 }
616 part_num[offset * 2] = '\0';
617
618out:
619 return ret_val;
620}
621
622
623
624
625
626
627
628
629
630s32 igb_read_mac_addr(struct e1000_hw *hw)
631{
632 u32 rar_high;
633 u32 rar_low;
634 u16 i;
635
636 rar_high = rd32(E1000_RAH(0));
637 rar_low = rd32(E1000_RAL(0));
638
639 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
640 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
641
642 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
643 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
644
645 for (i = 0; i < ETH_ALEN; i++)
646 hw->mac.addr[i] = hw->mac.perm_addr[i];
647
648 return 0;
649}
650
651
652
653
654
655
656
657
658s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
659{
660 s32 ret_val = 0;
661 u16 checksum = 0;
662 u16 i, nvm_data;
663
664 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
665 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
666 if (ret_val) {
667 hw_dbg("NVM Read Error\n");
668 goto out;
669 }
670 checksum += nvm_data;
671 }
672
673 if (checksum != (u16) NVM_SUM) {
674 hw_dbg("NVM Checksum Invalid\n");
675 ret_val = -E1000_ERR_NVM;
676 goto out;
677 }
678
679out:
680 return ret_val;
681}
682
683
684
685
686
687
688
689
690
691s32 igb_update_nvm_checksum(struct e1000_hw *hw)
692{
693 s32 ret_val;
694 u16 checksum = 0;
695 u16 i, nvm_data;
696
697 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
698 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
699 if (ret_val) {
700 hw_dbg("NVM Read Error while updating checksum.\n");
701 goto out;
702 }
703 checksum += nvm_data;
704 }
705 checksum = (u16) NVM_SUM - checksum;
706 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
707 if (ret_val)
708 hw_dbg("NVM Write Error while updating checksum.\n");
709
710out:
711 return ret_val;
712}
713