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28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
31#include <linux/bitops.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/cpumask.h>
36#include <linux/aer.h>
37#include <linux/if_vlan.h>
38
39#ifdef CONFIG_IXGBE_PTP
40#include <linux/clocksource.h>
41#include <linux/net_tstamp.h>
42#include <linux/ptp_clock_kernel.h>
43#endif
44
45#include "ixgbe_type.h"
46#include "ixgbe_common.h"
47#include "ixgbe_dcb.h"
48#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
49#define IXGBE_FCOE
50#include "ixgbe_fcoe.h"
51#endif
52#ifdef CONFIG_IXGBE_DCA
53#include <linux/dca.h>
54#endif
55
56
57#undef pr_fmt
58#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
59
60
61#define IXGBE_DEFAULT_TXD 512
62#define IXGBE_DEFAULT_TX_WORK 256
63#define IXGBE_MAX_TXD 4096
64#define IXGBE_MIN_TXD 64
65
66#define IXGBE_DEFAULT_RXD 512
67#define IXGBE_MAX_RXD 4096
68#define IXGBE_MIN_RXD 64
69
70
71#define IXGBE_MIN_FCRTL 0x40
72#define IXGBE_MAX_FCRTL 0x7FF80
73#define IXGBE_MIN_FCRTH 0x600
74#define IXGBE_MAX_FCRTH 0x7FFF0
75#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
76#define IXGBE_MIN_FCPAUSE 0
77#define IXGBE_MAX_FCPAUSE 0xFFFF
78
79
80#define IXGBE_RXBUFFER_512 512
81#define IXGBE_MAX_RXBUFFER 16384
82
83
84
85
86
87
88
89
90#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
91
92#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
93
94
95#define IXGBE_RX_BUFFER_WRITE 16
96
97#define IXGBE_TX_FLAGS_CSUM (u32)(1)
98#define IXGBE_TX_FLAGS_HW_VLAN (u32)(1 << 1)
99#define IXGBE_TX_FLAGS_SW_VLAN (u32)(1 << 2)
100#define IXGBE_TX_FLAGS_TSO (u32)(1 << 3)
101#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 4)
102#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 5)
103#define IXGBE_TX_FLAGS_FSO (u32)(1 << 6)
104#define IXGBE_TX_FLAGS_TXSW (u32)(1 << 7)
105#define IXGBE_TX_FLAGS_TSTAMP (u32)(1 << 8)
106#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
107#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
108#define IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT 29
109#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
110
111#define IXGBE_MAX_VF_MC_ENTRIES 30
112#define IXGBE_MAX_VF_FUNCTIONS 64
113#define IXGBE_MAX_VFTA_ENTRIES 128
114#define MAX_EMULATION_MAC_ADDRS 16
115#define IXGBE_MAX_PF_MACVLANS 15
116#define VMDQ_P(p) ((p) + adapter->num_vfs)
117#define IXGBE_82599_VF_DEVICE_ID 0x10ED
118#define IXGBE_X540_VF_DEVICE_ID 0x1515
119
120struct vf_data_storage {
121 unsigned char vf_mac_addresses[ETH_ALEN];
122 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
123 u16 num_vf_mc_hashes;
124 u16 default_vf_vlan_id;
125 u16 vlans_enabled;
126 bool clear_to_send;
127 bool pf_set_mac;
128 u16 pf_vlan;
129 u16 pf_qos;
130 u16 tx_rate;
131 u16 vlan_count;
132 u8 spoofchk_enabled;
133 struct pci_dev *vfdev;
134};
135
136struct vf_macvlans {
137 struct list_head l;
138 int vf;
139 int rar_entry;
140 bool free;
141 bool is_macvlan;
142 u8 vf_macvlan[ETH_ALEN];
143};
144
145#define IXGBE_MAX_TXD_PWR 14
146#define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
147
148
149#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD)
150#define DESC_NEEDED ((MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE)) + 4)
151
152
153
154struct ixgbe_tx_buffer {
155 union ixgbe_adv_tx_desc *next_to_watch;
156 unsigned long time_stamp;
157 struct sk_buff *skb;
158 unsigned int bytecount;
159 unsigned short gso_segs;
160 __be16 protocol;
161 DEFINE_DMA_UNMAP_ADDR(dma);
162 DEFINE_DMA_UNMAP_LEN(len);
163 u32 tx_flags;
164};
165
166struct ixgbe_rx_buffer {
167 struct sk_buff *skb;
168 dma_addr_t dma;
169 struct page *page;
170 unsigned int page_offset;
171};
172
173struct ixgbe_queue_stats {
174 u64 packets;
175 u64 bytes;
176};
177
178struct ixgbe_tx_queue_stats {
179 u64 restart_queue;
180 u64 tx_busy;
181 u64 tx_done_old;
182};
183
184struct ixgbe_rx_queue_stats {
185 u64 rsc_count;
186 u64 rsc_flush;
187 u64 non_eop_descs;
188 u64 alloc_rx_page_failed;
189 u64 alloc_rx_buff_failed;
190 u64 csum_err;
191};
192
193enum ixgbe_ring_state_t {
194 __IXGBE_TX_FDIR_INIT_DONE,
195 __IXGBE_TX_DETECT_HANG,
196 __IXGBE_HANG_CHECK_ARMED,
197 __IXGBE_RX_RSC_ENABLED,
198 __IXGBE_RX_CSUM_UDP_ZERO_ERR,
199 __IXGBE_RX_FCOE,
200};
201
202#define check_for_tx_hang(ring) \
203 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
204#define set_check_for_tx_hang(ring) \
205 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
206#define clear_check_for_tx_hang(ring) \
207 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
208#define ring_is_rsc_enabled(ring) \
209 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
210#define set_ring_rsc_enabled(ring) \
211 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
212#define clear_ring_rsc_enabled(ring) \
213 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
214struct ixgbe_ring {
215 struct ixgbe_ring *next;
216 struct ixgbe_q_vector *q_vector;
217 struct net_device *netdev;
218 struct device *dev;
219 void *desc;
220 union {
221 struct ixgbe_tx_buffer *tx_buffer_info;
222 struct ixgbe_rx_buffer *rx_buffer_info;
223 };
224 unsigned long state;
225 u8 __iomem *tail;
226 dma_addr_t dma;
227 unsigned int size;
228
229 u16 count;
230
231 u8 queue_index;
232 u8 reg_idx;
233
234
235
236
237 u16 next_to_use;
238 u16 next_to_clean;
239
240 union {
241 u16 next_to_alloc;
242 struct {
243 u8 atr_sample_rate;
244 u8 atr_count;
245 };
246 };
247
248 u8 dcb_tc;
249 struct ixgbe_queue_stats stats;
250 struct u64_stats_sync syncp;
251 union {
252 struct ixgbe_tx_queue_stats tx_stats;
253 struct ixgbe_rx_queue_stats rx_stats;
254 };
255} ____cacheline_internodealigned_in_smp;
256
257enum ixgbe_ring_f_enum {
258 RING_F_NONE = 0,
259 RING_F_VMDQ,
260 RING_F_RSS,
261 RING_F_FDIR,
262#ifdef IXGBE_FCOE
263 RING_F_FCOE,
264#endif
265
266 RING_F_ARRAY_SIZE
267};
268
269#define IXGBE_MAX_RSS_INDICES 16
270#define IXGBE_MAX_VMDQ_INDICES 64
271#define IXGBE_MAX_FDIR_INDICES 64
272#ifdef IXGBE_FCOE
273#define IXGBE_MAX_FCOE_INDICES 8
274#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
275#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
276#else
277#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
278#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
279#endif
280struct ixgbe_ring_feature {
281 int indices;
282 int mask;
283} ____cacheline_internodealigned_in_smp;
284
285
286
287
288
289
290#if defined(IXGBE_FCOE) && (PAGE_SIZE < 8192)
291static inline unsigned int ixgbe_rx_pg_order(struct ixgbe_ring *ring)
292{
293 return test_bit(__IXGBE_RX_FCOE, &ring->state) ? 1 : 0;
294}
295#else
296#define ixgbe_rx_pg_order(_ring) 0
297#endif
298#define ixgbe_rx_pg_size(_ring) (PAGE_SIZE << ixgbe_rx_pg_order(_ring))
299#define ixgbe_rx_bufsz(_ring) ((PAGE_SIZE / 2) << ixgbe_rx_pg_order(_ring))
300
301struct ixgbe_ring_container {
302 struct ixgbe_ring *ring;
303 unsigned int total_bytes;
304 unsigned int total_packets;
305 u16 work_limit;
306 u8 count;
307 u8 itr;
308};
309
310
311#define ixgbe_for_each_ring(pos, head) \
312 for (pos = (head).ring; pos != NULL; pos = pos->next)
313
314#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
315 ? 8 : 1)
316#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
317
318
319
320
321struct ixgbe_q_vector {
322 struct ixgbe_adapter *adapter;
323#ifdef CONFIG_IXGBE_DCA
324 int cpu;
325#endif
326 u16 v_idx;
327
328
329 u16 itr;
330 struct ixgbe_ring_container rx, tx;
331
332 struct napi_struct napi;
333 cpumask_t affinity_mask;
334 int numa_node;
335 struct rcu_head rcu;
336 char name[IFNAMSIZ + 9];
337
338
339 struct ixgbe_ring ring[0] ____cacheline_internodealigned_in_smp;
340};
341#ifdef CONFIG_IXGBE_HWMON
342
343#define IXGBE_HWMON_TYPE_LOC 0
344#define IXGBE_HWMON_TYPE_TEMP 1
345#define IXGBE_HWMON_TYPE_CAUTION 2
346#define IXGBE_HWMON_TYPE_MAX 3
347
348struct hwmon_attr {
349 struct device_attribute dev_attr;
350 struct ixgbe_hw *hw;
351 struct ixgbe_thermal_diode_data *sensor;
352 char name[12];
353};
354
355struct hwmon_buff {
356 struct device *device;
357 struct hwmon_attr *hwmon_list;
358 unsigned int n_hwmon;
359};
360#endif
361
362
363
364
365
366#define IXGBE_MIN_RSC_ITR 24
367#define IXGBE_100K_ITR 40
368#define IXGBE_20K_ITR 200
369#define IXGBE_10K_ITR 400
370#define IXGBE_8K_ITR 500
371
372
373static inline __le32 ixgbe_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
374 const u32 stat_err_bits)
375{
376 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
377}
378
379static inline u16 ixgbe_desc_unused(struct ixgbe_ring *ring)
380{
381 u16 ntc = ring->next_to_clean;
382 u16 ntu = ring->next_to_use;
383
384 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
385}
386
387#define IXGBE_RX_DESC(R, i) \
388 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
389#define IXGBE_TX_DESC(R, i) \
390 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
391#define IXGBE_TX_CTXTDESC(R, i) \
392 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
393
394#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
395#ifdef IXGBE_FCOE
396
397#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
398#endif
399
400#define OTHER_VECTOR 1
401#define NON_Q_VECTORS (OTHER_VECTOR)
402
403#define MAX_MSIX_VECTORS_82599 64
404#define MAX_MSIX_Q_VECTORS_82599 64
405#define MAX_MSIX_VECTORS_82598 18
406#define MAX_MSIX_Q_VECTORS_82598 16
407
408#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
409#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
410
411#define MIN_MSIX_Q_VECTORS 1
412#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
413
414
415#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
416
417
418struct ixgbe_adapter {
419 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
420
421 struct net_device *netdev;
422 struct pci_dev *pdev;
423
424 unsigned long state;
425
426
427
428
429 u32 flags;
430#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
431#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
432#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
433#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
434#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
435#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
436#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
437#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
438#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
439#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
440#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
441#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
442#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
443#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
444#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
445#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
446#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
447#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
448#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
449#define IXGBE_FLAG_NEED_LINK_CONFIG (u32)(1 << 23)
450#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 24)
451#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 25)
452#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 26)
453#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 27)
454#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 28)
455#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 29)
456
457 u32 flags2;
458#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
459#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
460#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
461#define IXGBE_FLAG2_TEMP_SENSOR_EVENT (u32)(1 << 3)
462#define IXGBE_FLAG2_SEARCH_FOR_SFP (u32)(1 << 4)
463#define IXGBE_FLAG2_SFP_NEEDS_RESET (u32)(1 << 5)
464#define IXGBE_FLAG2_RESET_REQUESTED (u32)(1 << 6)
465#define IXGBE_FLAG2_FDIR_REQUIRES_REINIT (u32)(1 << 7)
466#define IXGBE_FLAG2_RSS_FIELD_IPV4_UDP (u32)(1 << 8)
467#define IXGBE_FLAG2_RSS_FIELD_IPV6_UDP (u32)(1 << 9)
468#define IXGBE_FLAG2_OVERFLOW_CHECK_ENABLED (u32)(1 << 10)
469#define IXGBE_FLAG2_PTP_PPS_ENABLED (u32)(1 << 11)
470
471
472 int num_tx_queues;
473 u16 tx_itr_setting;
474 u16 tx_work_limit;
475
476
477 int num_rx_queues;
478 u16 rx_itr_setting;
479
480
481 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
482
483 u64 restart_queue;
484 u64 lsc_int;
485 u32 tx_timeout_count;
486
487
488 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES];
489 int num_rx_pools;
490 int num_rx_queues_per_pool;
491 u64 hw_csum_rx_error;
492 u64 hw_rx_no_dma_resources;
493 u64 rsc_total_count;
494 u64 rsc_total_flush;
495 u64 non_eop_descs;
496 u32 alloc_rx_page_failed;
497 u32 alloc_rx_buff_failed;
498
499 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
500
501
502 struct ieee_pfc *ixgbe_ieee_pfc;
503 struct ieee_ets *ixgbe_ieee_ets;
504 struct ixgbe_dcb_config dcb_cfg;
505 struct ixgbe_dcb_config temp_dcb_cfg;
506 u8 dcb_set_bitmap;
507 u8 dcbx_cap;
508 enum ixgbe_fc_mode last_lfc_mode;
509
510 int num_msix_vectors;
511 int max_msix_q_vectors;
512 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
513 struct msix_entry *msix_entries;
514
515 u32 test_icr;
516 struct ixgbe_ring test_tx_ring;
517 struct ixgbe_ring test_rx_ring;
518
519
520 struct ixgbe_hw hw;
521 u16 msg_enable;
522 struct ixgbe_hw_stats stats;
523
524 u64 tx_busy;
525 unsigned int tx_ring_count;
526 unsigned int rx_ring_count;
527
528 u32 link_speed;
529 bool link_up;
530 unsigned long link_check_timeout;
531
532 struct timer_list service_timer;
533 struct work_struct service_task;
534
535 struct hlist_head fdir_filter_list;
536 unsigned long fdir_overflow;
537 union ixgbe_atr_input fdir_mask;
538 int fdir_filter_count;
539 u32 fdir_pballoc;
540 u32 atr_sample_rate;
541 spinlock_t fdir_perfect_lock;
542
543#ifdef IXGBE_FCOE
544 struct ixgbe_fcoe fcoe;
545#endif
546 u32 wol;
547
548 u16 bd_number;
549
550 u16 eeprom_verh;
551 u16 eeprom_verl;
552 u16 eeprom_cap;
553
554 u32 interrupt_event;
555 u32 led_reg;
556
557#ifdef CONFIG_IXGBE_PTP
558 struct ptp_clock *ptp_clock;
559 struct ptp_clock_info ptp_caps;
560 unsigned long last_overflow_check;
561 spinlock_t tmreg_lock;
562 struct cyclecounter cc;
563 struct timecounter tc;
564 u32 base_incval;
565 u32 cycle_speed;
566#endif
567
568
569 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
570 unsigned int num_vfs;
571 struct vf_data_storage *vfinfo;
572 int vf_rate_link_speed;
573 struct vf_macvlans vf_mvs;
574 struct vf_macvlans *mv_list;
575
576 u32 timer_event_accumulator;
577 u32 vferr_refcount;
578 struct kobject *info_kobj;
579#ifdef CONFIG_IXGBE_HWMON
580 struct hwmon_buff ixgbe_hwmon_buff;
581#endif
582};
583
584struct ixgbe_fdir_filter {
585 struct hlist_node fdir_node;
586 union ixgbe_atr_input filter;
587 u16 sw_idx;
588 u16 action;
589};
590
591enum ixgbe_state_t {
592 __IXGBE_TESTING,
593 __IXGBE_RESETTING,
594 __IXGBE_DOWN,
595 __IXGBE_SERVICE_SCHED,
596 __IXGBE_IN_SFP_INIT,
597};
598
599struct ixgbe_cb {
600 union {
601 struct sk_buff *head;
602 struct sk_buff *tail;
603 };
604 dma_addr_t dma;
605 u16 append_cnt;
606 bool page_released;
607};
608#define IXGBE_CB(skb) ((struct ixgbe_cb *)(skb)->cb)
609
610enum ixgbe_boards {
611 board_82598,
612 board_82599,
613 board_X540,
614};
615
616extern struct ixgbe_info ixgbe_82598_info;
617extern struct ixgbe_info ixgbe_82599_info;
618extern struct ixgbe_info ixgbe_X540_info;
619#ifdef CONFIG_IXGBE_DCB
620extern const struct dcbnl_rtnl_ops dcbnl_ops;
621#endif
622
623extern char ixgbe_driver_name[];
624extern const char ixgbe_driver_version[];
625#ifdef IXGBE_FCOE
626extern char ixgbe_default_device_descr[];
627#endif
628
629extern void ixgbe_up(struct ixgbe_adapter *adapter);
630extern void ixgbe_down(struct ixgbe_adapter *adapter);
631extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
632extern void ixgbe_reset(struct ixgbe_adapter *adapter);
633extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
634extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
635extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
636extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
637extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
638extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
639extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
640extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
641 struct ixgbe_ring *);
642extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
643extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
644extern int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
645 u16 subdevice_id);
646extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
647extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
648 struct ixgbe_adapter *,
649 struct ixgbe_ring *);
650extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
651 struct ixgbe_tx_buffer *);
652extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
653extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
654extern int ixgbe_poll(struct napi_struct *napi, int budget);
655extern int ethtool_ioctl(struct ifreq *ifr);
656extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
657extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl);
658extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl);
659extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
660 union ixgbe_atr_hash_dword input,
661 union ixgbe_atr_hash_dword common,
662 u8 queue);
663extern s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
664 union ixgbe_atr_input *input_mask);
665extern s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
666 union ixgbe_atr_input *input,
667 u16 soft_id, u8 queue);
668extern s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
669 union ixgbe_atr_input *input,
670 u16 soft_id);
671extern void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
672 union ixgbe_atr_input *mask);
673extern void ixgbe_set_rx_mode(struct net_device *netdev);
674#ifdef CONFIG_IXGBE_DCB
675extern void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter);
676extern int ixgbe_setup_tc(struct net_device *dev, u8 tc);
677#endif
678extern void ixgbe_tx_ctxtdesc(struct ixgbe_ring *, u32, u32, u32, u32);
679extern void ixgbe_do_reset(struct net_device *netdev);
680#ifdef CONFIG_IXGBE_HWMON
681extern void ixgbe_sysfs_exit(struct ixgbe_adapter *adapter);
682extern int ixgbe_sysfs_init(struct ixgbe_adapter *adapter);
683#endif
684#ifdef IXGBE_FCOE
685extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
686extern int ixgbe_fso(struct ixgbe_ring *tx_ring,
687 struct ixgbe_tx_buffer *first,
688 u8 *hdr_len);
689extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
690extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
691 union ixgbe_adv_rx_desc *rx_desc,
692 struct sk_buff *skb);
693extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
694 struct scatterlist *sgl, unsigned int sgc);
695extern int ixgbe_fcoe_ddp_target(struct net_device *netdev, u16 xid,
696 struct scatterlist *sgl, unsigned int sgc);
697extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
698extern int ixgbe_fcoe_enable(struct net_device *netdev);
699extern int ixgbe_fcoe_disable(struct net_device *netdev);
700#ifdef CONFIG_IXGBE_DCB
701extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
702extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
703#endif
704extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
705extern int ixgbe_fcoe_get_hbainfo(struct net_device *netdev,
706 struct netdev_fcoe_hbainfo *info);
707#endif
708
709static inline struct netdev_queue *txring_txq(const struct ixgbe_ring *ring)
710{
711 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
712}
713
714#ifdef CONFIG_IXGBE_PTP
715extern void ixgbe_ptp_init(struct ixgbe_adapter *adapter);
716extern void ixgbe_ptp_stop(struct ixgbe_adapter *adapter);
717extern void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter);
718extern void ixgbe_ptp_tx_hwtstamp(struct ixgbe_q_vector *q_vector,
719 struct sk_buff *skb);
720extern void ixgbe_ptp_rx_hwtstamp(struct ixgbe_q_vector *q_vector,
721 struct sk_buff *skb);
722extern int ixgbe_ptp_hwtstamp_ioctl(struct ixgbe_adapter *adapter,
723 struct ifreq *ifr, int cmd);
724extern void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter);
725extern void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr);
726#endif
727
728#endif
729
