1
2
3
4
5
6
7
8#ifndef _QLCNIC_H_
9#define _QLCNIC_H_
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/ioport.h>
15#include <linux/pci.h>
16#include <linux/netdevice.h>
17#include <linux/etherdevice.h>
18#include <linux/ip.h>
19#include <linux/in.h>
20#include <linux/tcp.h>
21#include <linux/skbuff.h>
22#include <linux/firmware.h>
23
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/timer.h>
27
28#include <linux/vmalloc.h>
29
30#include <linux/io.h>
31#include <asm/byteorder.h>
32#include <linux/bitops.h>
33#include <linux/if_vlan.h>
34
35#include "qlcnic_hdr.h"
36
37#define _QLCNIC_LINUX_MAJOR 5
38#define _QLCNIC_LINUX_MINOR 0
39#define _QLCNIC_LINUX_SUBVERSION 28
40#define QLCNIC_LINUX_VERSIONID "5.0.28"
41#define QLCNIC_DRV_IDC_VER 0x01
42#define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
44
45#define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
46#define _major(v) (((v) >> 24) & 0xff)
47#define _minor(v) (((v) >> 16) & 0xff)
48#define _build(v) ((v) & 0xffff)
49
50
51
52
53
54
55#define QLCNIC_DECODE_VERSION(v) \
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
57
58#define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
59#define QLCNIC_NUM_FLASH_SECTORS (64)
60#define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
61#define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
62 * QLCNIC_FLASH_SECTOR_SIZE)
63
64#define RCV_DESC_RINGSIZE(rds_ring) \
65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
66#define RCV_BUFF_RINGSIZE(rds_ring) \
67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
68#define STATUS_DESC_RINGSIZE(sds_ring) \
69 (sizeof(struct status_desc) * (sds_ring)->num_desc)
70#define TX_BUFF_RINGSIZE(tx_ring) \
71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
72#define TX_DESC_RINGSIZE(tx_ring) \
73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
74
75#define QLCNIC_P3P_A0 0x50
76#define QLCNIC_P3P_C0 0x58
77
78#define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
79
80#define FIRST_PAGE_GROUP_START 0
81#define FIRST_PAGE_GROUP_END 0x100000
82
83#define P3P_MAX_MTU (9600)
84#define P3P_MIN_MTU (68)
85#define QLCNIC_MAX_ETHERHDR 32
86
87#define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
88#define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
89#define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
90#define QLCNIC_LRO_BUFFER_EXTRA 2048
91
92
93#define TX_ETHER_PKT 0x01
94#define TX_TCP_PKT 0x02
95#define TX_UDP_PKT 0x03
96#define TX_IP_PKT 0x04
97#define TX_TCP_LSO 0x05
98#define TX_TCP_LSO6 0x06
99#define TX_TCPV6_PKT 0x0b
100#define TX_UDPV6_PKT 0x0c
101
102
103#define QLCNIC_MAX_FRAGS_PER_TX 14
104#define MAX_TSO_HEADER_DESC 2
105#define MGMT_CMD_DESC_RESV 4
106#define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
107 + MGMT_CMD_DESC_RESV)
108#define QLCNIC_MAX_TX_TIMEOUTS 2
109
110
111
112
113
114#define PHAN_INITIALIZE_FAILED 0xffff
115#define PHAN_INITIALIZE_COMPLETE 0xff01
116
117
118#define PHAN_INITIALIZE_ACK 0xf00f
119#define PHAN_PEG_RCV_INITIALIZED 0xff01
120
121#define NUM_RCV_DESC_RINGS 3
122
123#define RCV_RING_NORMAL 0
124#define RCV_RING_JUMBO 1
125
126#define MIN_CMD_DESCRIPTORS 64
127#define MIN_RCV_DESCRIPTORS 64
128#define MIN_JUMBO_DESCRIPTORS 32
129
130#define MAX_CMD_DESCRIPTORS 1024
131#define MAX_RCV_DESCRIPTORS_1G 4096
132#define MAX_RCV_DESCRIPTORS_10G 8192
133#define MAX_RCV_DESCRIPTORS_VF 2048
134#define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
135#define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
136
137#define DEFAULT_RCV_DESCRIPTORS_1G 2048
138#define DEFAULT_RCV_DESCRIPTORS_10G 4096
139#define DEFAULT_RCV_DESCRIPTORS_VF 1024
140#define MAX_RDS_RINGS 2
141
142#define get_next_index(index, length) \
143 (((index) + 1) & ((length) - 1))
144
145
146
147
148
149
150
151#define FLAGS_VLAN_TAGGED 0x10
152#define FLAGS_VLAN_OOB 0x40
153
154#define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
155 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
156#define qlcnic_set_cmd_desc_port(cmd_desc, var) \
157 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
158#define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
159 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
160
161#define qlcnic_set_tx_port(_desc, _port) \
162 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
163
164#define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
165 ((_desc)->flags_opcode |= \
166 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
167
168#define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
169 ((_desc)->nfrags__length = \
170 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
171
172struct cmd_desc_type0 {
173 u8 tcp_hdr_offset;
174 u8 ip_hdr_offset;
175 __le16 flags_opcode;
176 __le32 nfrags__length;
177
178 __le64 addr_buffer2;
179
180 __le16 reference_handle;
181 __le16 mss;
182 u8 port_ctxid;
183 u8 total_hdr_length;
184 __le16 conn_id;
185
186 __le64 addr_buffer3;
187 __le64 addr_buffer1;
188
189 __le16 buffer_length[4];
190
191 __le64 addr_buffer4;
192
193 u8 eth_addr[ETH_ALEN];
194 __le16 vlan_TCI;
195
196} __attribute__ ((aligned(64)));
197
198
199struct rcv_desc {
200 __le16 reference_handle;
201 __le16 reserved;
202 __le32 buffer_length;
203 __le64 addr_buffer;
204} __packed;
205
206
207#define QLCNIC_SYN_OFFLOAD 0x03
208#define QLCNIC_RXPKT_DESC 0x04
209#define QLCNIC_OLD_RXPKT_DESC 0x3f
210#define QLCNIC_RESPONSE_DESC 0x05
211#define QLCNIC_LRO_DESC 0x12
212
213
214#define STATUS_CKSUM_LOOP 0
215#define STATUS_CKSUM_OK 2
216
217
218#define STATUS_OWNER_HOST (0x1ULL << 56)
219#define STATUS_OWNER_PHANTOM (0x2ULL << 56)
220
221
222
223
224
225
226#define qlcnic_get_sts_port(sts_data) \
227 ((sts_data) & 0x0F)
228#define qlcnic_get_sts_status(sts_data) \
229 (((sts_data) >> 4) & 0x0F)
230#define qlcnic_get_sts_type(sts_data) \
231 (((sts_data) >> 8) & 0x0F)
232#define qlcnic_get_sts_totallength(sts_data) \
233 (((sts_data) >> 12) & 0xFFFF)
234#define qlcnic_get_sts_refhandle(sts_data) \
235 (((sts_data) >> 28) & 0xFFFF)
236#define qlcnic_get_sts_prot(sts_data) \
237 (((sts_data) >> 44) & 0x0F)
238#define qlcnic_get_sts_pkt_offset(sts_data) \
239 (((sts_data) >> 48) & 0x1F)
240#define qlcnic_get_sts_desc_cnt(sts_data) \
241 (((sts_data) >> 53) & 0x7)
242#define qlcnic_get_sts_opcode(sts_data) \
243 (((sts_data) >> 58) & 0x03F)
244
245#define qlcnic_get_lro_sts_refhandle(sts_data) \
246 ((sts_data) & 0x0FFFF)
247#define qlcnic_get_lro_sts_length(sts_data) \
248 (((sts_data) >> 16) & 0x0FFFF)
249#define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
250 (((sts_data) >> 32) & 0x0FF)
251#define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
252 (((sts_data) >> 40) & 0x0FF)
253#define qlcnic_get_lro_sts_timestamp(sts_data) \
254 (((sts_data) >> 48) & 0x1)
255#define qlcnic_get_lro_sts_type(sts_data) \
256 (((sts_data) >> 49) & 0x7)
257#define qlcnic_get_lro_sts_push_flag(sts_data) \
258 (((sts_data) >> 52) & 0x1)
259#define qlcnic_get_lro_sts_seq_number(sts_data) \
260 ((sts_data) & 0x0FFFFFFFF)
261
262
263struct status_desc {
264 __le64 status_desc_data[2];
265} __attribute__ ((aligned(16)));
266
267
268#define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
269#define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
270#define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
271#define QLCNIC_UNI_DIR_SECT_FW 0x7
272
273
274#define QLCNIC_UNI_CHIP_REV_OFF 10
275#define QLCNIC_UNI_FLAGS_OFF 11
276#define QLCNIC_UNI_BIOS_VERSION_OFF 12
277#define QLCNIC_UNI_BOOTLD_IDX_OFF 27
278#define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
279
280struct uni_table_desc{
281 u32 findex;
282 u32 num_entries;
283 u32 entry_size;
284 u32 reserved[5];
285};
286
287struct uni_data_desc{
288 u32 findex;
289 u32 size;
290 u32 reserved[5];
291};
292
293
294#define QLCNIC_FLT_LOCATION 0x3F1000
295#define QLCNIC_B0_FW_IMAGE_REGION 0x74
296#define QLCNIC_C0_FW_IMAGE_REGION 0x97
297#define QLCNIC_BOOTLD_REGION 0X72
298struct qlcnic_flt_header {
299 u16 version;
300 u16 len;
301 u16 checksum;
302 u16 reserved;
303};
304
305struct qlcnic_flt_entry {
306 u8 region;
307 u8 reserved0;
308 u8 attrib;
309 u8 reserved1;
310 u32 size;
311 u32 start_addr;
312 u32 end_addr;
313};
314
315
316#define QLCNIC_BDINFO_MAGIC 0x12345678
317
318#define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
319#define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
320#define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
321#define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
322#define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
323#define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
324#define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
325#define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
326#define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
327#define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
328#define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
329#define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
330#define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
331#define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
332
333#define QLCNIC_MSIX_TABLE_OFFSET 0x44
334
335
336#define QLCNIC_BRDCFG_START 0x4000
337#define QLCNIC_BOOTLD_START 0x10000
338#define QLCNIC_IMAGE_START 0x43000
339#define QLCNIC_USER_START 0x3E8000
340
341#define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
342#define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
343#define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
344#define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
345
346#define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
347#define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
348
349#define QLCNIC_FW_MIN_SIZE (0x3fffff)
350#define QLCNIC_UNIFIED_ROMIMAGE 0
351#define QLCNIC_FLASH_ROMIMAGE 1
352#define QLCNIC_UNKNOWN_ROMIMAGE 0xff
353
354#define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
355#define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
356
357extern char qlcnic_driver_name[];
358
359
360#define MAX_STATUS_HANDLE (64)
361
362
363
364
365
366struct qlcnic_skb_frag {
367 u64 dma;
368 u64 length;
369};
370
371
372#define QLCNIC_BUFFER_FREE 0
373#define QLCNIC_BUFFER_BUSY 1
374
375
376
377
378
379struct qlcnic_cmd_buffer {
380 struct sk_buff *skb;
381 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
382 u32 frag_count;
383};
384
385
386struct qlcnic_rx_buffer {
387 u16 ref_handle;
388 struct sk_buff *skb;
389 struct list_head list;
390 u64 dma;
391};
392
393
394#define QLCNIC_GBE 0x01
395#define QLCNIC_XGBE 0x02
396
397
398
399
400
401#define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
402#define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
403
404#define QLCNIC_INTR_DEFAULT 0x04
405#define QLCNIC_CONFIG_INTR_COALESCE 3
406
407struct qlcnic_nic_intr_coalesce {
408 u8 type;
409 u8 sts_ring_mask;
410 u16 rx_packets;
411 u16 rx_time_us;
412 u16 flag;
413 u32 timer_out;
414};
415
416struct qlcnic_dump_template_hdr {
417 __le32 type;
418 __le32 offset;
419 __le32 size;
420 __le32 cap_mask;
421 __le32 num_entries;
422 __le32 version;
423 __le32 timestamp;
424 __le32 checksum;
425 __le32 drv_cap_mask;
426 __le32 sys_info[3];
427 __le32 saved_state[16];
428 __le32 cap_sizes[8];
429 __le32 rsvd[0];
430};
431
432struct qlcnic_fw_dump {
433 u8 clr;
434 u8 enable;
435 u32 size;
436 void *data;
437 struct qlcnic_dump_template_hdr *tmpl_hdr;
438};
439
440
441
442
443
444struct qlcnic_hardware_context {
445 void __iomem *pci_base0;
446 void __iomem *ocm_win_crb;
447
448 unsigned long pci_len0;
449
450 rwlock_t crb_lock;
451 struct mutex mem_lock;
452
453 u8 revision_id;
454 u8 pci_func;
455 u8 linkup;
456 u8 loopback_state;
457 u16 port_type;
458 u16 board_type;
459
460 u8 beacon_state;
461
462 struct qlcnic_nic_intr_coalesce coal;
463 struct qlcnic_fw_dump fw_dump;
464};
465
466struct qlcnic_adapter_stats {
467 u64 xmitcalled;
468 u64 xmitfinished;
469 u64 rxdropped;
470 u64 txdropped;
471 u64 csummed;
472 u64 rx_pkts;
473 u64 lro_pkts;
474 u64 rxbytes;
475 u64 txbytes;
476 u64 lrobytes;
477 u64 lso_frames;
478 u64 xmit_on;
479 u64 xmit_off;
480 u64 skb_alloc_failure;
481 u64 null_rxbuf;
482 u64 rx_dma_map_error;
483 u64 tx_dma_map_error;
484};
485
486
487
488
489
490struct qlcnic_host_rds_ring {
491 void __iomem *crb_rcv_producer;
492 struct rcv_desc *desc_head;
493 struct qlcnic_rx_buffer *rx_buf_arr;
494 u32 num_desc;
495 u32 producer;
496 u32 dma_size;
497 u32 skb_size;
498 u32 flags;
499 struct list_head free_list;
500 spinlock_t lock;
501 dma_addr_t phys_addr;
502} ____cacheline_internodealigned_in_smp;
503
504struct qlcnic_host_sds_ring {
505 u32 consumer;
506 u32 num_desc;
507 void __iomem *crb_sts_consumer;
508
509 struct status_desc *desc_head;
510 struct qlcnic_adapter *adapter;
511 struct napi_struct napi;
512 struct list_head free_list[NUM_RCV_DESC_RINGS];
513
514 void __iomem *crb_intr_mask;
515 int irq;
516
517 dma_addr_t phys_addr;
518 char name[IFNAMSIZ+4];
519} ____cacheline_internodealigned_in_smp;
520
521struct qlcnic_host_tx_ring {
522 u32 producer;
523 u32 sw_consumer;
524 u32 num_desc;
525 void __iomem *crb_cmd_producer;
526 struct cmd_desc_type0 *desc_head;
527 struct qlcnic_cmd_buffer *cmd_buf_arr;
528 __le32 *hw_consumer;
529
530 dma_addr_t phys_addr;
531 dma_addr_t hw_cons_phys_addr;
532 struct netdev_queue *txq;
533} ____cacheline_internodealigned_in_smp;
534
535
536
537
538
539
540
541struct qlcnic_recv_context {
542 struct qlcnic_host_rds_ring *rds_rings;
543 struct qlcnic_host_sds_ring *sds_rings;
544 u32 state;
545 u16 context_id;
546 u16 virt_port;
547
548};
549
550
551
552#define QLCNIC_OS_CRB_RETRY_COUNT 4000
553#define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
554 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
555
556#define QLCNIC_CDRP_CMD_BIT 0x80000000
557
558
559
560
561
562#define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
563#define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
564
565#define QLCNIC_CDRP_RSP_OK 0x00000001
566#define QLCNIC_CDRP_RSP_FAIL 0x00000002
567#define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
568
569
570
571
572
573#define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
574#define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
575
576#define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
577#define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
578#define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
579#define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
580#define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
581#define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
582#define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
583#define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
584#define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
585#define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
586#define QLCNIC_CDRP_CMD_INTRPT_TEST 0x00000011
587#define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
588#define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
589#define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
590#define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
591#define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
592#define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
593#define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
594#define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
595#define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
596
597#define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
598#define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
599#define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
600#define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
601#define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
602#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
603#define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
604#define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
605#define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
606#define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
607#define QLCNIC_CDRP_CMD_CONFIG_PORT 0x0000002E
608#define QLCNIC_CDRP_CMD_TEMP_SIZE 0x0000002f
609#define QLCNIC_CDRP_CMD_GET_TEMP_HDR 0x00000030
610#define QLCNIC_CDRP_CMD_GET_MAC_STATS 0x00000037
611
612#define QLCNIC_RCODE_SUCCESS 0
613#define QLCNIC_RCODE_NOT_SUPPORTED 9
614#define QLCNIC_RCODE_TIMEOUT 17
615#define QLCNIC_DESTROY_CTX_RESET 0
616
617
618
619
620#define QLCNIC_CAP0_LEGACY_CONTEXT (1)
621#define QLCNIC_CAP0_LEGACY_MN (1 << 2)
622#define QLCNIC_CAP0_LSO (1 << 6)
623#define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
624#define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
625#define QLCNIC_CAP0_VALIDOFF (1 << 11)
626
627
628
629
630#define QLCNIC_HOST_CTX_STATE_FREED 0
631#define QLCNIC_HOST_CTX_STATE_ACTIVE 2
632
633
634
635
636
637struct qlcnic_hostrq_sds_ring {
638 __le64 host_phys_addr;
639 __le32 ring_size;
640 __le16 msi_index;
641 __le16 rsvd;
642} __packed;
643
644struct qlcnic_hostrq_rds_ring {
645 __le64 host_phys_addr;
646 __le64 buff_size;
647 __le32 ring_size;
648 __le32 ring_kind;
649} __packed;
650
651struct qlcnic_hostrq_rx_ctx {
652 __le64 host_rsp_dma_addr;
653 __le32 capabilities[4];
654 __le32 host_int_crb_mode;
655 __le32 host_rds_crb_mode;
656
657 __le32 rds_ring_offset;
658 __le32 sds_ring_offset;
659 __le16 num_rds_rings;
660 __le16 num_sds_rings;
661 __le16 valid_field_offset;
662 u8 txrx_sds_binding;
663 u8 msix_handler;
664 u8 reserved[128];
665
666
667
668
669 char data[0];
670} __packed;
671
672struct qlcnic_cardrsp_rds_ring{
673 __le32 host_producer_crb;
674 __le32 rsvd1;
675} __packed;
676
677struct qlcnic_cardrsp_sds_ring {
678 __le32 host_consumer_crb;
679 __le32 interrupt_crb;
680} __packed;
681
682struct qlcnic_cardrsp_rx_ctx {
683
684 __le32 rds_ring_offset;
685 __le32 sds_ring_offset;
686 __le32 host_ctx_state;
687 __le32 num_fn_per_port;
688 __le16 num_rds_rings;
689 __le16 num_sds_rings;
690 __le16 context_id;
691 u8 phys_port;
692 u8 virt_port;
693 u8 reserved[128];
694
695
696
697
698 char data[0];
699} __packed;
700
701#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
702 (sizeof(HOSTRQ_RX) + \
703 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
704 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
705
706#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
707 (sizeof(CARDRSP_RX) + \
708 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
709 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
710
711
712
713
714
715struct qlcnic_hostrq_cds_ring {
716 __le64 host_phys_addr;
717 __le32 ring_size;
718 __le32 rsvd;
719} __packed;
720
721struct qlcnic_hostrq_tx_ctx {
722 __le64 host_rsp_dma_addr;
723 __le64 cmd_cons_dma_addr;
724 __le64 dummy_dma_addr;
725 __le32 capabilities[4];
726 __le32 host_int_crb_mode;
727 __le32 rsvd1;
728 __le16 rsvd2;
729 __le16 interrupt_ctl;
730 __le16 msi_index;
731 __le16 rsvd3;
732 struct qlcnic_hostrq_cds_ring cds_ring;
733 u8 reserved[128];
734} __packed;
735
736struct qlcnic_cardrsp_cds_ring {
737 __le32 host_producer_crb;
738 __le32 interrupt_crb;
739} __packed;
740
741struct qlcnic_cardrsp_tx_ctx {
742 __le32 host_ctx_state;
743 __le16 context_id;
744 u8 phys_port;
745 u8 virt_port;
746 struct qlcnic_cardrsp_cds_ring cds_ring;
747 u8 reserved[128];
748} __packed;
749
750#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
751#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
752
753
754
755#define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
756#define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
757#define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
758#define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
759
760#define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
761#define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
762#define QLCNIC_HOST_INT_CRB_MODE_NORX 2
763#define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
764#define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
765
766
767
768
769#define MC_COUNT_P3P 38
770
771#define QLCNIC_MAC_NOOP 0
772#define QLCNIC_MAC_ADD 1
773#define QLCNIC_MAC_DEL 2
774#define QLCNIC_MAC_VLAN_ADD 3
775#define QLCNIC_MAC_VLAN_DEL 4
776
777struct qlcnic_mac_list_s {
778 struct list_head list;
779 uint8_t mac_addr[ETH_ALEN+2];
780};
781
782#define QLCNIC_HOST_REQUEST 0x13
783#define QLCNIC_REQUEST 0x14
784
785#define QLCNIC_MAC_EVENT 0x1
786
787#define QLCNIC_IP_UP 2
788#define QLCNIC_IP_DOWN 3
789
790#define QLCNIC_ILB_MODE 0x1
791#define QLCNIC_ELB_MODE 0x2
792
793#define QLCNIC_LINKEVENT 0x1
794#define QLCNIC_LB_RESPONSE 0x2
795#define QLCNIC_IS_LB_CONFIGURED(VAL) \
796 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
797
798
799
800
801#define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
802#define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
803#define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
804#define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
805#define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
806#define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
807
808#define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
809#define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
810#define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
811#define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
812
813
814
815
816
817#define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
818#define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
819
820#define VPORT_MISS_MODE_DROP 0
821#define VPORT_MISS_MODE_ACCEPT_ALL 1
822#define VPORT_MISS_MODE_ACCEPT_MULTI 2
823
824#define QLCNIC_LRO_REQUEST_CLEANUP 4
825
826
827#define QLCNIC_FW_CAPABILITY_TSO BIT_1
828#define QLCNIC_FW_CAPABILITY_BDG BIT_8
829#define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
830#define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
831#define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
832
833
834#define LINKEVENT_MODULE_NOT_PRESENT 1
835#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
836#define LINKEVENT_MODULE_OPTICAL_SRLR 3
837#define LINKEVENT_MODULE_OPTICAL_LRM 4
838#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
839#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
840#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
841#define LINKEVENT_MODULE_TWINAX 8
842
843#define LINKSPEED_10GBPS 10000
844#define LINKSPEED_1GBPS 1000
845#define LINKSPEED_100MBPS 100
846#define LINKSPEED_10MBPS 10
847
848#define LINKSPEED_ENCODED_10MBPS 0
849#define LINKSPEED_ENCODED_100MBPS 1
850#define LINKSPEED_ENCODED_1GBPS 2
851
852#define LINKEVENT_AUTONEG_DISABLED 0
853#define LINKEVENT_AUTONEG_ENABLED 1
854
855#define LINKEVENT_HALF_DUPLEX 0
856#define LINKEVENT_FULL_DUPLEX 1
857
858#define LINKEVENT_LINKSPEED_MBPS 0
859#define LINKEVENT_LINKSPEED_ENCODED 1
860
861
862
863
864
865
866
867
868
869
870
871#define qlcnic_get_nic_msg_opcode(msg_hdr) \
872 ((msg_hdr >> 32) & 0xFF)
873
874struct qlcnic_fw_msg {
875 union {
876 struct {
877 u64 hdr;
878 u64 body[7];
879 };
880 u64 words[8];
881 };
882};
883
884struct qlcnic_nic_req {
885 __le64 qhdr;
886 __le64 req_hdr;
887 __le64 words[6];
888} __packed;
889
890struct qlcnic_mac_req {
891 u8 op;
892 u8 tag;
893 u8 mac_addr[6];
894};
895
896struct qlcnic_vlan_req {
897 __le16 vlan_id;
898 __le16 rsvd[3];
899} __packed;
900
901struct qlcnic_ipaddr {
902 __be32 ipv4;
903 __be32 ipv6[4];
904};
905
906#define QLCNIC_MSI_ENABLED 0x02
907#define QLCNIC_MSIX_ENABLED 0x04
908#define QLCNIC_LRO_ENABLED 0x08
909#define QLCNIC_LRO_DISABLED 0x00
910#define QLCNIC_BRIDGE_ENABLED 0X10
911#define QLCNIC_DIAG_ENABLED 0x20
912#define QLCNIC_ESWITCH_ENABLED 0x40
913#define QLCNIC_ADAPTER_INITIALIZED 0x80
914#define QLCNIC_TAGGING_ENABLED 0x100
915#define QLCNIC_MACSPOOF 0x200
916#define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
917#define QLCNIC_PROMISC_DISABLED 0x800
918#define QLCNIC_NEED_FLR 0x1000
919#define QLCNIC_FW_RESET_OWNER 0x2000
920#define QLCNIC_FW_HANG 0x4000
921#define QLCNIC_IS_MSI_FAMILY(adapter) \
922 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
923
924#define QLCNIC_DEF_NUM_STS_DESC_RINGS 4
925#define QLCNIC_MSIX_TBL_SPACE 8192
926#define QLCNIC_PCI_REG_MSIX_TBL 0x44
927#define QLCNIC_MSIX_TBL_PGSIZE 4096
928
929#define QLCNIC_NETDEV_WEIGHT 128
930#define QLCNIC_ADAPTER_UP_MAGIC 777
931
932#define __QLCNIC_FW_ATTACHED 0
933#define __QLCNIC_DEV_UP 1
934#define __QLCNIC_RESETTING 2
935#define __QLCNIC_START_FW 4
936#define __QLCNIC_AER 5
937#define __QLCNIC_DIAG_RES_ALLOC 6
938#define __QLCNIC_LED_ENABLE 7
939
940#define QLCNIC_INTERRUPT_TEST 1
941#define QLCNIC_LOOPBACK_TEST 2
942#define QLCNIC_LED_TEST 3
943
944#define QLCNIC_FILTER_AGE 80
945#define QLCNIC_READD_AGE 20
946#define QLCNIC_LB_MAX_FILTERS 64
947
948
949#define QLCNIC_FW_NOT_RESPOND 51
950#define QLCNIC_TEST_IN_PROGRESS 52
951#define QLCNIC_UNDEFINED_ERROR 53
952#define QLCNIC_LB_CABLE_NOT_CONN 54
953
954struct qlcnic_filter {
955 struct hlist_node fnode;
956 u8 faddr[ETH_ALEN];
957 __le16 vlan_id;
958 unsigned long ftime;
959};
960
961struct qlcnic_filter_hash {
962 struct hlist_head *fhead;
963 u8 fnum;
964 u8 fmax;
965};
966
967struct qlcnic_adapter {
968 struct qlcnic_hardware_context *ahw;
969 struct qlcnic_recv_context *recv_ctx;
970 struct qlcnic_host_tx_ring *tx_ring;
971 struct net_device *netdev;
972 struct pci_dev *pdev;
973
974 unsigned long state;
975 u32 flags;
976
977 u16 num_txd;
978 u16 num_rxd;
979 u16 num_jumbo_rxd;
980 u16 max_rxd;
981 u16 max_jumbo_rxd;
982
983 u8 max_rds_rings;
984 u8 max_sds_rings;
985 u8 msix_supported;
986 u8 portnum;
987 u8 physical_port;
988 u8 reset_context;
989
990 u8 mc_enabled;
991 u8 max_mc_count;
992 u8 fw_wait_cnt;
993 u8 fw_fail_cnt;
994 u8 tx_timeo_cnt;
995 u8 need_fw_reset;
996
997 u8 has_link_events;
998 u8 fw_type;
999 u16 tx_context_id;
1000 u16 is_up;
1001
1002 u16 link_speed;
1003 u16 link_duplex;
1004 u16 link_autoneg;
1005 u16 module_type;
1006
1007 u16 op_mode;
1008 u16 switch_mode;
1009 u16 max_tx_ques;
1010 u16 max_rx_ques;
1011 u16 max_mtu;
1012 u16 pvid;
1013
1014 u32 fw_hal_version;
1015 u32 capabilities;
1016 u32 irq;
1017 u32 temp;
1018
1019 u32 int_vec_bit;
1020 u32 heartbeat;
1021
1022 u8 max_mac_filters;
1023 u8 dev_state;
1024 u8 diag_test;
1025 char diag_cnt;
1026 u8 reset_ack_timeo;
1027 u8 dev_init_timeo;
1028 u16 msg_enable;
1029
1030 u8 mac_addr[ETH_ALEN];
1031
1032 u64 dev_rst_time;
1033 u8 mac_learn;
1034 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1035
1036 struct qlcnic_npar_info *npars;
1037 struct qlcnic_eswitch *eswitch;
1038 struct qlcnic_nic_template *nic_ops;
1039
1040 struct qlcnic_adapter_stats stats;
1041 struct list_head mac_list;
1042
1043 void __iomem *tgt_mask_reg;
1044 void __iomem *tgt_status_reg;
1045 void __iomem *crb_int_state_reg;
1046 void __iomem *isr_int_vec;
1047
1048 struct msix_entry *msix_entries;
1049
1050 struct delayed_work fw_work;
1051
1052
1053 struct qlcnic_filter_hash fhash;
1054
1055 spinlock_t tx_clean_lock;
1056 spinlock_t mac_learn_lock;
1057 __le32 file_prd_off;
1058 u32 fw_version;
1059 const struct firmware *fw;
1060};
1061
1062struct qlcnic_info {
1063 __le16 pci_func;
1064 __le16 op_mode;
1065 __le16 phys_port;
1066 __le16 switch_mode;
1067
1068 __le32 capabilities;
1069 u8 max_mac_filters;
1070 u8 reserved1;
1071 __le16 max_mtu;
1072
1073 __le16 max_tx_ques;
1074 __le16 max_rx_ques;
1075 __le16 min_tx_bw;
1076 __le16 max_tx_bw;
1077 u8 reserved2[104];
1078} __packed;
1079
1080struct qlcnic_pci_info {
1081 __le16 id;
1082 __le16 active;
1083 __le16 type;
1084 __le16 default_port;
1085
1086 __le16 tx_min_bw;
1087 __le16 tx_max_bw;
1088 __le16 reserved1[2];
1089
1090 u8 mac[ETH_ALEN];
1091 u8 reserved2[106];
1092} __packed;
1093
1094struct qlcnic_npar_info {
1095 u16 pvid;
1096 u16 min_bw;
1097 u16 max_bw;
1098 u8 phy_port;
1099 u8 type;
1100 u8 active;
1101 u8 enable_pm;
1102 u8 dest_npar;
1103 u8 discard_tagged;
1104 u8 mac_override;
1105 u8 mac_anti_spoof;
1106 u8 promisc_mode;
1107 u8 offload_flags;
1108};
1109
1110struct qlcnic_eswitch {
1111 u8 port;
1112 u8 active_vports;
1113 u8 active_vlans;
1114 u8 active_ucast_filters;
1115 u8 max_ucast_filters;
1116 u8 max_active_vlans;
1117
1118 u32 flags;
1119#define QLCNIC_SWITCH_ENABLE BIT_1
1120#define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1121#define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1122#define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1123};
1124
1125
1126
1127#define QL_STATUS_INVALID_PARAM -1
1128
1129#define MAX_BW 100
1130#define MAX_VLAN_ID 4095
1131#define MIN_VLAN_ID 2
1132#define DEFAULT_MAC_LEARN 1
1133
1134#define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1135#define IS_VALID_BW(bw) (bw <= MAX_BW)
1136
1137struct qlcnic_pci_func_cfg {
1138 u16 func_type;
1139 u16 min_bw;
1140 u16 max_bw;
1141 u16 port_num;
1142 u8 pci_func;
1143 u8 func_state;
1144 u8 def_mac_addr[6];
1145};
1146
1147struct qlcnic_npar_func_cfg {
1148 u32 fw_capab;
1149 u16 port_num;
1150 u16 min_bw;
1151 u16 max_bw;
1152 u16 max_tx_queues;
1153 u16 max_rx_queues;
1154 u8 pci_func;
1155 u8 op_mode;
1156};
1157
1158struct qlcnic_pm_func_cfg {
1159 u8 pci_func;
1160 u8 action;
1161 u8 dest_npar;
1162 u8 reserved[5];
1163};
1164
1165struct qlcnic_esw_func_cfg {
1166 u16 vlan_id;
1167 u8 op_mode;
1168 u8 op_type;
1169 u8 pci_func;
1170 u8 host_vlan_tag;
1171 u8 promisc_mode;
1172 u8 discard_tagged;
1173 u8 mac_override;
1174 u8 mac_anti_spoof;
1175 u8 offload_flags;
1176 u8 reserved[5];
1177};
1178
1179#define QLCNIC_STATS_VERSION 1
1180#define QLCNIC_STATS_PORT 1
1181#define QLCNIC_STATS_ESWITCH 2
1182#define QLCNIC_QUERY_RX_COUNTER 0
1183#define QLCNIC_QUERY_TX_COUNTER 1
1184#define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1185#define QLCNIC_FILL_STATS(VAL1) \
1186 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1187#define QLCNIC_MAC_STATS 1
1188#define QLCNIC_ESW_STATS 2
1189
1190#define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1191do { \
1192 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1193 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1194 (VAL1) = (VAL2); \
1195 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1196 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1197 (VAL1) += (VAL2); \
1198} while (0)
1199
1200struct qlcnic_mac_statistics{
1201 __le64 mac_tx_frames;
1202 __le64 mac_tx_bytes;
1203 __le64 mac_tx_mcast_pkts;
1204 __le64 mac_tx_bcast_pkts;
1205 __le64 mac_tx_pause_cnt;
1206 __le64 mac_tx_ctrl_pkt;
1207 __le64 mac_tx_lt_64b_pkts;
1208 __le64 mac_tx_lt_127b_pkts;
1209 __le64 mac_tx_lt_255b_pkts;
1210 __le64 mac_tx_lt_511b_pkts;
1211 __le64 mac_tx_lt_1023b_pkts;
1212 __le64 mac_tx_lt_1518b_pkts;
1213 __le64 mac_tx_gt_1518b_pkts;
1214 __le64 rsvd1[3];
1215
1216 __le64 mac_rx_frames;
1217 __le64 mac_rx_bytes;
1218 __le64 mac_rx_mcast_pkts;
1219 __le64 mac_rx_bcast_pkts;
1220 __le64 mac_rx_pause_cnt;
1221 __le64 mac_rx_ctrl_pkt;
1222 __le64 mac_rx_lt_64b_pkts;
1223 __le64 mac_rx_lt_127b_pkts;
1224 __le64 mac_rx_lt_255b_pkts;
1225 __le64 mac_rx_lt_511b_pkts;
1226 __le64 mac_rx_lt_1023b_pkts;
1227 __le64 mac_rx_lt_1518b_pkts;
1228 __le64 mac_rx_gt_1518b_pkts;
1229 __le64 rsvd2[3];
1230
1231 __le64 mac_rx_length_error;
1232 __le64 mac_rx_length_small;
1233 __le64 mac_rx_length_large;
1234 __le64 mac_rx_jabber;
1235 __le64 mac_rx_dropped;
1236 __le64 mac_rx_crc_error;
1237 __le64 mac_align_error;
1238} __packed;
1239
1240struct __qlcnic_esw_statistics {
1241 __le16 context_id;
1242 __le16 version;
1243 __le16 size;
1244 __le16 unused;
1245 __le64 unicast_frames;
1246 __le64 multicast_frames;
1247 __le64 broadcast_frames;
1248 __le64 dropped_frames;
1249 __le64 errors;
1250 __le64 local_frames;
1251 __le64 numbytes;
1252 __le64 rsvd[3];
1253} __packed;
1254
1255struct qlcnic_esw_statistics {
1256 struct __qlcnic_esw_statistics rx;
1257 struct __qlcnic_esw_statistics tx;
1258};
1259
1260struct qlcnic_common_entry_hdr {
1261 __le32 type;
1262 __le32 offset;
1263 __le32 cap_size;
1264 u8 mask;
1265 u8 rsvd[2];
1266 u8 flags;
1267} __packed;
1268
1269struct __crb {
1270 __le32 addr;
1271 u8 stride;
1272 u8 rsvd1[3];
1273 __le32 data_size;
1274 __le32 no_ops;
1275 __le32 rsvd2[4];
1276} __packed;
1277
1278struct __ctrl {
1279 __le32 addr;
1280 u8 stride;
1281 u8 index_a;
1282 __le16 timeout;
1283 __le32 data_size;
1284 __le32 no_ops;
1285 u8 opcode;
1286 u8 index_v;
1287 u8 shl_val;
1288 u8 shr_val;
1289 __le32 val1;
1290 __le32 val2;
1291 __le32 val3;
1292} __packed;
1293
1294struct __cache {
1295 __le32 addr;
1296 __le16 stride;
1297 __le16 init_tag_val;
1298 __le32 size;
1299 __le32 no_ops;
1300 __le32 ctrl_addr;
1301 __le32 ctrl_val;
1302 __le32 read_addr;
1303 u8 read_addr_stride;
1304 u8 read_addr_num;
1305 u8 rsvd1[2];
1306} __packed;
1307
1308struct __ocm {
1309 u8 rsvd[8];
1310 __le32 size;
1311 __le32 no_ops;
1312 u8 rsvd1[8];
1313 __le32 read_addr;
1314 __le32 read_addr_stride;
1315} __packed;
1316
1317struct __mem {
1318 u8 rsvd[24];
1319 __le32 addr;
1320 __le32 size;
1321} __packed;
1322
1323struct __mux {
1324 __le32 addr;
1325 u8 rsvd[4];
1326 __le32 size;
1327 __le32 no_ops;
1328 __le32 val;
1329 __le32 val_stride;
1330 __le32 read_addr;
1331 u8 rsvd2[4];
1332} __packed;
1333
1334struct __queue {
1335 __le32 sel_addr;
1336 __le16 stride;
1337 u8 rsvd[2];
1338 __le32 size;
1339 __le32 no_ops;
1340 u8 rsvd2[8];
1341 __le32 read_addr;
1342 u8 read_addr_stride;
1343 u8 read_addr_cnt;
1344 u8 rsvd3[2];
1345} __packed;
1346
1347struct qlcnic_dump_entry {
1348 struct qlcnic_common_entry_hdr hdr;
1349 union {
1350 struct __crb crb;
1351 struct __cache cache;
1352 struct __ocm ocm;
1353 struct __mem mem;
1354 struct __mux mux;
1355 struct __queue que;
1356 struct __ctrl ctrl;
1357 } region;
1358} __packed;
1359
1360enum op_codes {
1361 QLCNIC_DUMP_NOP = 0,
1362 QLCNIC_DUMP_READ_CRB = 1,
1363 QLCNIC_DUMP_READ_MUX = 2,
1364 QLCNIC_DUMP_QUEUE = 3,
1365 QLCNIC_DUMP_BRD_CONFIG = 4,
1366 QLCNIC_DUMP_READ_OCM = 6,
1367 QLCNIC_DUMP_PEG_REG = 7,
1368 QLCNIC_DUMP_L1_DTAG = 8,
1369 QLCNIC_DUMP_L1_ITAG = 9,
1370 QLCNIC_DUMP_L1_DATA = 11,
1371 QLCNIC_DUMP_L1_INST = 12,
1372 QLCNIC_DUMP_L2_DTAG = 21,
1373 QLCNIC_DUMP_L2_ITAG = 22,
1374 QLCNIC_DUMP_L2_DATA = 23,
1375 QLCNIC_DUMP_L2_INST = 24,
1376 QLCNIC_DUMP_READ_ROM = 71,
1377 QLCNIC_DUMP_READ_MEM = 72,
1378 QLCNIC_DUMP_READ_CTRL = 98,
1379 QLCNIC_DUMP_TLHDR = 99,
1380 QLCNIC_DUMP_RDEND = 255
1381};
1382
1383#define QLCNIC_DUMP_WCRB BIT_0
1384#define QLCNIC_DUMP_RWCRB BIT_1
1385#define QLCNIC_DUMP_ANDCRB BIT_2
1386#define QLCNIC_DUMP_ORCRB BIT_3
1387#define QLCNIC_DUMP_POLLCRB BIT_4
1388#define QLCNIC_DUMP_RD_SAVE BIT_5
1389#define QLCNIC_DUMP_WRT_SAVED BIT_6
1390#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
1391#define QLCNIC_DUMP_SKIP BIT_7
1392
1393#define QLCNIC_DUMP_MASK_MIN 3
1394#define QLCNIC_DUMP_MASK_DEF 0x1f
1395#define QLCNIC_DUMP_MASK_MAX 0xff
1396#define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1397#define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1398#define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1399#define QLCNIC_FORCE_FW_RESET 0xdeaddead
1400#define QLCNIC_SET_QUIESCENT 0xadd00010
1401#define QLCNIC_RESET_QUIESCENT 0xadd00020
1402
1403struct qlcnic_dump_operations {
1404 enum op_codes opcode;
1405 u32 (*handler)(struct qlcnic_adapter *,
1406 struct qlcnic_dump_entry *, u32 *);
1407};
1408
1409struct _cdrp_cmd {
1410 u32 cmd;
1411 u32 arg1;
1412 u32 arg2;
1413 u32 arg3;
1414};
1415
1416struct qlcnic_cmd_args {
1417 struct _cdrp_cmd req;
1418 struct _cdrp_cmd rsp;
1419};
1420
1421int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1422int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1423
1424u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1425int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1426int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1427int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1428void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1429void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1430
1431#define ADDR_IN_RANGE(addr, low, high) \
1432 (((addr) < (high)) && ((addr) >= (low)))
1433
1434#define QLCRD32(adapter, off) \
1435 (qlcnic_hw_read_wx_2M(adapter, off))
1436#define QLCWR32(adapter, off, val) \
1437 (qlcnic_hw_write_wx_2M(adapter, off, val))
1438
1439int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1440void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1441
1442#define qlcnic_rom_lock(a) \
1443 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1444#define qlcnic_rom_unlock(a) \
1445 qlcnic_pcie_sem_unlock((a), 2)
1446#define qlcnic_phy_lock(a) \
1447 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1448#define qlcnic_phy_unlock(a) \
1449 qlcnic_pcie_sem_unlock((a), 3)
1450#define qlcnic_api_lock(a) \
1451 qlcnic_pcie_sem_lock((a), 5, 0)
1452#define qlcnic_api_unlock(a) \
1453 qlcnic_pcie_sem_unlock((a), 5)
1454#define qlcnic_sw_lock(a) \
1455 qlcnic_pcie_sem_lock((a), 6, 0)
1456#define qlcnic_sw_unlock(a) \
1457 qlcnic_pcie_sem_unlock((a), 6)
1458#define crb_win_lock(a) \
1459 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1460#define crb_win_unlock(a) \
1461 qlcnic_pcie_sem_unlock((a), 7)
1462
1463#define __QLCNIC_MAX_LED_RATE 0xf
1464#define __QLCNIC_MAX_LED_STATE 0x2
1465
1466int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1467int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1468int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1469void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1470void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1471int qlcnic_dump_fw(struct qlcnic_adapter *);
1472
1473
1474int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1475int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1476void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1477void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1478int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1479int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1480int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1481
1482int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1483int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1484 u8 *bytes, size_t size);
1485int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1486void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1487
1488void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1489
1490int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1491void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1492
1493int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1494void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1495
1496void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1497void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1498void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1499
1500int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1501void qlcnic_watchdog_task(struct work_struct *work);
1502void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1503 struct qlcnic_host_rds_ring *rds_ring);
1504int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1505void qlcnic_set_multi(struct net_device *netdev);
1506void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1507int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1508int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1509int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1510int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1511int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1512void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1513
1514int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1515int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1516netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1517 netdev_features_t features);
1518int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1519int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1520int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1521int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1522void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1523 struct qlcnic_host_tx_ring *tx_ring);
1524void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1525void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
1526void qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter);
1527int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode);
1528
1529
1530int qlcnic_check_loopback_buff(unsigned char *data, u8 mac[]);
1531
1532
1533int qlcnic_reset_context(struct qlcnic_adapter *);
1534void qlcnic_issue_cmd(struct qlcnic_adapter *adapter, struct qlcnic_cmd_args *);
1535void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1536int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1537netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1538int qlcnic_validate_max_rss(struct net_device *netdev, u8 max_hw, u8 val);
1539int qlcnic_set_max_rss(struct qlcnic_adapter *adapter, u8 data);
1540void qlcnic_dev_request_reset(struct qlcnic_adapter *);
1541void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1542
1543
1544int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1545int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1546int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1547int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1548
1549
1550int qlcnic_config_switch_port(struct qlcnic_adapter *,
1551 struct qlcnic_esw_func_cfg *);
1552int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1553 struct qlcnic_esw_func_cfg *);
1554int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1555int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1556 struct __qlcnic_esw_statistics *);
1557int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1558 struct __qlcnic_esw_statistics *);
1559int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1560int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1561extern int qlcnic_config_tso;
1562
1563
1564
1565
1566
1567#define QLCNIC_MAX_BOARD_NAME_LEN 100
1568struct qlcnic_brdinfo {
1569 unsigned short vendor;
1570 unsigned short device;
1571 unsigned short sub_vendor;
1572 unsigned short sub_device;
1573 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1574};
1575
1576static const struct qlcnic_brdinfo qlcnic_boards[] = {
1577 {0x1077, 0x8020, 0x1077, 0x203,
1578 "8200 Series Single Port 10GbE Converged Network Adapter "
1579 "(TCP/IP Networking)"},
1580 {0x1077, 0x8020, 0x1077, 0x207,
1581 "8200 Series Dual Port 10GbE Converged Network Adapter "
1582 "(TCP/IP Networking)"},
1583 {0x1077, 0x8020, 0x1077, 0x20b,
1584 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1585 {0x1077, 0x8020, 0x1077, 0x20c,
1586 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1587 {0x1077, 0x8020, 0x1077, 0x20f,
1588 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1589 {0x1077, 0x8020, 0x103c, 0x3733,
1590 "NC523SFP 10Gb 2-port Server Adapter"},
1591 {0x1077, 0x8020, 0x103c, 0x3346,
1592 "CN1000Q Dual Port Converged Network Adapter"},
1593 {0x1077, 0x8020, 0x1077, 0x210,
1594 "QME8242-k 10GbE Dual Port Mezzanine Card"},
1595 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1596};
1597
1598#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1599
1600static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1601{
1602 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1603 return tx_ring->sw_consumer - tx_ring->producer;
1604 else
1605 return tx_ring->sw_consumer + tx_ring->num_desc -
1606 tx_ring->producer;
1607}
1608
1609extern const struct ethtool_ops qlcnic_ethtool_ops;
1610extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
1611
1612struct qlcnic_nic_template {
1613 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1614 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1615 int (*start_firmware) (struct qlcnic_adapter *);
1616};
1617
1618#define QLCDB(adapter, lvl, _fmt, _args...) do { \
1619 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1620 printk(KERN_INFO "%s: %s: " _fmt, \
1621 dev_name(&adapter->pdev->dev), \
1622 __func__, ##_args); \
1623 } while (0)
1624
1625#endif
1626