LXR linux/drivers/net/ethernet/renesas/sh

   1/*
   2 *  SuperH Ethernet device driver
   3 *
   4 *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5 *  Copyright (C) 2008-2012 Renesas Solutions Corp.
   6 *
   7 *  This program is free software; you can redistribute it and/or modify it
   8 *  under the terms and conditions of the GNU General Public License,
   9 *  version 2, as published by the Free Software Foundation.
  10 *
  11 *  This program is distributed in the hope it will be useful, but WITHOUT
  12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 *  more details.
  15 *  You should have received a copy of the GNU General Public License along with
  16 *  this program; if not, write to the Free Software Foundation, Inc.,
  17 *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18 *
  19 *  The full GNU General Public License is included in this distribution in
  20 *  the file called "COPYING".
  21 */
  22
  23#ifndef __SH_ETH_H__
  24#define __SH_ETH_H__
  25
  26#define CARDNAME        "sh-eth"
  27#define TX_TIMEOUT      (5*HZ)
  28#define TX_RING_SIZE    64      /* Tx ring size */
  29#define RX_RING_SIZE    64      /* Rx ring size */
  30#define ETHERSMALL              60
  31#define PKT_BUF_SZ              1538
  32#define SH_ETH_TSU_TIMEOUT_MS   500
  33#define SH_ETH_TSU_CAM_ENTRIES  32
  34
  35enum {
  36        /* E-DMAC registers */
  37        EDSR = 0,
  38        EDMR,
  39        EDTRR,
  40        EDRRR,
  41        EESR,
  42        EESIPR,
  43        TDLAR,
  44        TDFAR,
  45        TDFXR,
  46        TDFFR,
  47        RDLAR,
  48        RDFAR,
  49        RDFXR,
  50        RDFFR,
  51        TRSCER,
  52        RMFCR,
  53        TFTR,
  54        FDR,
  55        RMCR,
  56        EDOCR,
  57        TFUCR,
  58        RFOCR,
  59        FCFTR,
  60        RPADIR,
  61        TRIMD,
  62        RBWAR,
  63        TBRAR,
  64
  65        /* Ether registers */
  66        ECMR,
  67        ECSR,
  68        ECSIPR,
  69        PIR,
  70        PSR,
  71        RDMLR,
  72        PIPR,
  73        RFLR,
  74        IPGR,
  75        APR,
  76        MPR,
  77        PFTCR,
  78        PFRCR,
  79        RFCR,
  80        RFCF,
  81        TPAUSER,
  82        TPAUSECR,
  83        BCFR,
  84        BCFRR,
  85        GECMR,
  86        BCULR,
  87        MAHR,
  88        MALR,
  89        TROCR,
  90        CDCR,
  91        LCCR,
  92        CNDCR,
  93        CEFCR,
  94        FRECR,
  95        TSFRCR,
  96        TLFRCR,
  97        CERCR,
  98        CEECR,
  99        MAFCR,
 100        RTRATE,
 101        CSMR,
 102        RMII_MII,
 103
 104        /* TSU Absolute address */
 105        ARSTR,
 106        TSU_CTRST,
 107        TSU_FWEN0,
 108        TSU_FWEN1,
 109        TSU_FCM,
 110        TSU_BSYSL0,
 111        TSU_BSYSL1,
 112        TSU_PRISL0,
 113        TSU_PRISL1,
 114        TSU_FWSL0,
 115        TSU_FWSL1,
 116        TSU_FWSLC,
 117        TSU_QTAG0,
 118        TSU_QTAG1,
 119        TSU_QTAGM0,
 120        TSU_QTAGM1,
 121        TSU_FWSR,
 122        TSU_FWINMK,
 123        TSU_ADQT0,
 124        TSU_ADQT1,
 125        TSU_VTAG0,
 126        TSU_VTAG1,
 127        TSU_ADSBSY,
 128        TSU_TEN,
 129        TSU_POST1,
 130        TSU_POST2,
 131        TSU_POST3,
 132        TSU_POST4,
 133        TSU_ADRH0,
 134        TSU_ADRL0,
 135        TSU_ADRH31,
 136        TSU_ADRL31,
 137
 138        TXNLCR0,
 139        TXALCR0,
 140        RXNLCR0,
 141        RXALCR0,
 142        FWNLCR0,
 143        FWALCR0,
 144        TXNLCR1,
 145        TXALCR1,
 146        RXNLCR1,
 147        RXALCR1,
 148        FWNLCR1,
 149        FWALCR1,
 150
 151        /* This value must be written at last. */
 152        SH_ETH_MAX_REGISTER_OFFSET,
 153};
 154
 155static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 156        [EDSR]  = 0x0000,
 157        [EDMR]  = 0x0400,
 158        [EDTRR] = 0x0408,
 159        [EDRRR] = 0x0410,
 160        [EESR]  = 0x0428,
 161        [EESIPR]        = 0x0430,
 162        [TDLAR] = 0x0010,
 163        [TDFAR] = 0x0014,
 164        [TDFXR] = 0x0018,
 165        [TDFFR] = 0x001c,
 166        [RDLAR] = 0x0030,
 167        [RDFAR] = 0x0034,
 168        [RDFXR] = 0x0038,
 169        [RDFFR] = 0x003c,
 170        [TRSCER]        = 0x0438,
 171        [RMFCR] = 0x0440,
 172        [TFTR]  = 0x0448,
 173        [FDR]   = 0x0450,
 174        [RMCR]  = 0x0458,
 175        [RPADIR]        = 0x0460,
 176        [FCFTR] = 0x0468,
 177        [CSMR] = 0x04E4,
 178
 179        [ECMR]  = 0x0500,
 180        [ECSR]  = 0x0510,
 181        [ECSIPR]        = 0x0518,
 182        [PIR]   = 0x0520,
 183        [PSR]   = 0x0528,
 184        [PIPR]  = 0x052c,
 185        [RFLR]  = 0x0508,
 186        [APR]   = 0x0554,
 187        [MPR]   = 0x0558,
 188        [PFTCR] = 0x055c,
 189        [PFRCR] = 0x0560,
 190        [TPAUSER]       = 0x0564,
 191        [GECMR] = 0x05b0,
 192        [BCULR] = 0x05b4,
 193        [MAHR]  = 0x05c0,
 194        [MALR]  = 0x05c8,
 195        [TROCR] = 0x0700,
 196        [CDCR]  = 0x0708,
 197        [LCCR]  = 0x0710,
 198        [CEFCR] = 0x0740,
 199        [FRECR] = 0x0748,
 200        [TSFRCR]        = 0x0750,
 201        [TLFRCR]        = 0x0758,
 202        [RFCR]  = 0x0760,
 203        [CERCR] = 0x0768,
 204        [CEECR] = 0x0770,
 205        [MAFCR] = 0x0778,
 206        [RMII_MII] =  0x0790,
 207
 208        [ARSTR] = 0x0000,
 209        [TSU_CTRST]     = 0x0004,
 210        [TSU_FWEN0]     = 0x0010,
 211        [TSU_FWEN1]     = 0x0014,
 212        [TSU_FCM]       = 0x0018,
 213        [TSU_BSYSL0]    = 0x0020,
 214        [TSU_BSYSL1]    = 0x0024,
 215        [TSU_PRISL0]    = 0x0028,
 216        [TSU_PRISL1]    = 0x002c,
 217        [TSU_FWSL0]     = 0x0030,
 218        [TSU_FWSL1]     = 0x0034,
 219        [TSU_FWSLC]     = 0x0038,
 220        [TSU_QTAG0]     = 0x0040,
 221        [TSU_QTAG1]     = 0x0044,
 222        [TSU_FWSR]      = 0x0050,
 223        [TSU_FWINMK]    = 0x0054,
 224        [TSU_ADQT0]     = 0x0048,
 225        [TSU_ADQT1]     = 0x004c,
 226        [TSU_VTAG0]     = 0x0058,
 227        [TSU_VTAG1]     = 0x005c,
 228        [TSU_ADSBSY]    = 0x0060,
 229        [TSU_TEN]       = 0x0064,
 230        [TSU_POST1]     = 0x0070,
 231        [TSU_POST2]     = 0x0074,
 232        [TSU_POST3]     = 0x0078,
 233        [TSU_POST4]     = 0x007c,
 234        [TSU_ADRH0]     = 0x0100,
 235        [TSU_ADRL0]     = 0x0104,
 236        [TSU_ADRH31]    = 0x01f8,
 237        [TSU_ADRL31]    = 0x01fc,
 238
 239        [TXNLCR0]       = 0x0080,
 240        [TXALCR0]       = 0x0084,
 241        [RXNLCR0]       = 0x0088,
 242        [RXALCR0]       = 0x008c,
 243        [FWNLCR0]       = 0x0090,
 244        [FWALCR0]       = 0x0094,
 245        [TXNLCR1]       = 0x00a0,
 246        [TXALCR1]       = 0x00a0,
 247        [RXNLCR1]       = 0x00a8,
 248        [RXALCR1]       = 0x00ac,
 249        [FWNLCR1]       = 0x00b0,
 250        [FWALCR1]       = 0x00b4,
 251};
 252
 253static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 254        [ECMR]  = 0x0100,
 255        [RFLR]  = 0x0108,
 256        [ECSR]  = 0x0110,
 257        [ECSIPR]        = 0x0118,
 258        [PIR]   = 0x0120,
 259        [PSR]   = 0x0128,
 260        [RDMLR] = 0x0140,
 261        [IPGR]  = 0x0150,
 262        [APR]   = 0x0154,
 263        [MPR]   = 0x0158,
 264        [TPAUSER]       = 0x0164,
 265        [RFCF]  = 0x0160,
 266        [TPAUSECR]      = 0x0168,
 267        [BCFRR] = 0x016c,
 268        [MAHR]  = 0x01c0,
 269        [MALR]  = 0x01c8,
 270        [TROCR] = 0x01d0,
 271        [CDCR]  = 0x01d4,
 272        [LCCR]  = 0x01d8,
 273        [CNDCR] = 0x01dc,
 274        [CEFCR] = 0x01e4,
 275        [FRECR] = 0x01e8,
 276        [TSFRCR]        = 0x01ec,
 277        [TLFRCR]        = 0x01f0,
 278        [RFCR]  = 0x01f4,
 279        [MAFCR] = 0x01f8,
 280        [RTRATE]        = 0x01fc,
 281
 282        [EDMR]  = 0x0000,
 283        [EDTRR] = 0x0008,
 284        [EDRRR] = 0x0010,
 285        [TDLAR] = 0x0018,
 286        [RDLAR] = 0x0020,
 287        [EESR]  = 0x0028,
 288        [EESIPR]        = 0x0030,
 289        [TRSCER]        = 0x0038,
 290        [RMFCR] = 0x0040,
 291        [TFTR]  = 0x0048,
 292        [FDR]   = 0x0050,
 293        [RMCR]  = 0x0058,
 294        [TFUCR] = 0x0064,
 295        [RFOCR] = 0x0068,
 296        [FCFTR] = 0x0070,
 297        [RPADIR]        = 0x0078,
 298        [TRIMD] = 0x007c,
 299        [RBWAR] = 0x00c8,
 300        [RDFAR] = 0x00cc,
 301        [TBRAR] = 0x00d4,
 302        [TDFAR] = 0x00d8,
 303};
 304
 305static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 306        [ECMR]  = 0x0160,
 307        [ECSR]  = 0x0164,
 308        [ECSIPR]        = 0x0168,
 309        [PIR]   = 0x016c,
 310        [MAHR]  = 0x0170,
 311        [MALR]  = 0x0174,
 312        [RFLR]  = 0x0178,
 313        [PSR]   = 0x017c,
 314        [TROCR] = 0x0180,
 315        [CDCR]  = 0x0184,
 316        [LCCR]  = 0x0188,
 317        [CNDCR] = 0x018c,
 318        [CEFCR] = 0x0194,
 319        [FRECR] = 0x0198,
 320        [TSFRCR]        = 0x019c,
 321        [TLFRCR]        = 0x01a0,
 322        [RFCR]  = 0x01a4,
 323        [MAFCR] = 0x01a8,
 324        [IPGR]  = 0x01b4,
 325        [APR]   = 0x01b8,
 326        [MPR]   = 0x01bc,
 327        [TPAUSER]       = 0x01c4,
 328        [BCFR]  = 0x01cc,
 329
 330        [ARSTR] = 0x0000,
 331        [TSU_CTRST]     = 0x0004,
 332        [TSU_FWEN0]     = 0x0010,
 333        [TSU_FWEN1]     = 0x0014,
 334        [TSU_FCM]       = 0x0018,
 335        [TSU_BSYSL0]    = 0x0020,
 336        [TSU_BSYSL1]    = 0x0024,
 337        [TSU_PRISL0]    = 0x0028,
 338        [TSU_PRISL1]    = 0x002c,
 339        [TSU_FWSL0]     = 0x0030,
 340        [TSU_FWSL1]     = 0x0034,
 341        [TSU_FWSLC]     = 0x0038,
 342        [TSU_QTAGM0]    = 0x0040,
 343        [TSU_QTAGM1]    = 0x0044,
 344        [TSU_ADQT0]     = 0x0048,
 345        [TSU_ADQT1]     = 0x004c,
 346        [TSU_FWSR]      = 0x0050,
 347        [TSU_FWINMK]    = 0x0054,
 348        [TSU_ADSBSY]    = 0x0060,
 349        [TSU_TEN]       = 0x0064,
 350        [TSU_POST1]     = 0x0070,
 351        [TSU_POST2]     = 0x0074,
 352        [TSU_POST3]     = 0x0078,
 353        [TSU_POST4]     = 0x007c,
 354
 355        [TXNLCR0]       = 0x0080,
 356        [TXALCR0]       = 0x0084,
 357        [RXNLCR0]       = 0x0088,
 358        [RXALCR0]       = 0x008c,
 359        [FWNLCR0]       = 0x0090,
 360        [FWALCR0]       = 0x0094,
 361        [TXNLCR1]       = 0x00a0,
 362        [TXALCR1]       = 0x00a0,
 363        [RXNLCR1]       = 0x00a8,
 364        [RXALCR1]       = 0x00ac,
 365        [FWNLCR1]       = 0x00b0,
 366        [FWALCR1]       = 0x00b4,
 367
 368        [TSU_ADRH0]     = 0x0100,
 369        [TSU_ADRL0]     = 0x0104,
 370        [TSU_ADRL31]    = 0x01fc,
 371
 372};
 373
 374/* Driver's parameters */
 375#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 376#define SH4_SKB_RX_ALIGN        32
 377#else
 378#define SH2_SH3_SKB_RX_ALIGN    2
 379#endif
 380
 381/*
 382 * Register's bits
 383 */
 384#if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
 385    defined(CONFIG_ARCH_R8A7740)
 386/* EDSR */
 387enum EDSR_BIT {
 388        EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 389};
 390#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 391
 392/* GECMR */
 393enum GECMR_BIT {
 394        GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 395};
 396#endif
 397
 398/* EDMR */
 399enum DMAC_M_BIT {
 400        EDMR_EL = 0x40, /* Litte endian */
 401        EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 402        EDMR_SRST_GETHER = 0x03,
 403        EDMR_SRST_ETHER = 0x01,
 404};
 405
 406/* EDTRR */
 407enum DMAC_T_BIT {
 408        EDTRR_TRNS_GETHER = 0x03,
 409        EDTRR_TRNS_ETHER = 0x01,
 410};
 411
 412/* EDRRR*/
 413enum EDRRR_R_BIT {
 414        EDRRR_R = 0x01,
 415};
 416
 417/* TPAUSER */
 418enum TPAUSER_BIT {
 419        TPAUSER_TPAUSE = 0x0000ffff,
 420        TPAUSER_UNLIMITED = 0,
 421};
 422
 423/* BCFR */
 424enum BCFR_BIT {
 425        BCFR_RPAUSE = 0x0000ffff,
 426        BCFR_UNLIMITED = 0,
 427};
 428
 429/* PIR */
 430enum PIR_BIT {
 431        PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 432};
 433
 434/* PSR */
 435enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 436
 437/* EESR */
 438enum EESR_BIT {
 439        EESR_TWB1       = 0x80000000,
 440        EESR_TWB        = 0x40000000,   /* same as TWB0 */
 441        EESR_TC1        = 0x20000000,
 442        EESR_TUC        = 0x10000000,
 443        EESR_ROC        = 0x08000000,
 444        EESR_TABT       = 0x04000000,
 445        EESR_RABT       = 0x02000000,
 446        EESR_RFRMER     = 0x01000000,   /* same as RFCOF */
 447        EESR_ADE        = 0x00800000,
 448        EESR_ECI        = 0x00400000,
 449        EESR_FTC        = 0x00200000,   /* same as TC or TC0 */
 450        EESR_TDE        = 0x00100000,
 451        EESR_TFE        = 0x00080000,   /* same as TFUF */
 452        EESR_FRC        = 0x00040000,   /* same as FR */
 453        EESR_RDE        = 0x00020000,
 454        EESR_RFE        = 0x00010000,
 455        EESR_CND        = 0x00000800,
 456        EESR_DLC        = 0x00000400,
 457        EESR_CD         = 0x00000200,
 458        EESR_RTO        = 0x00000100,
 459        EESR_RMAF       = 0x00000080,
 460        EESR_CEEF       = 0x00000040,
 461        EESR_CELF       = 0x00000020,
 462        EESR_RRF        = 0x00000010,
 463        EESR_RTLF       = 0x00000008,
 464        EESR_RTSF       = 0x00000004,
 465        EESR_PRE        = 0x00000002,
 466        EESR_CERF       = 0x00000001,
 467};
 468
 469#define DEFAULT_TX_CHECK        (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
 470                                 EESR_RTO)
 471#define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | \
 472                                 EESR_RDE | EESR_RFRMER | EESR_ADE | \
 473                                 EESR_TFE | EESR_TDE | EESR_ECI)
 474#define DEFAULT_TX_ERROR_CHECK  (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
 475                                 EESR_TFE)
 476
 477/* EESIPR */
 478enum DMAC_IM_BIT {
 479        DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 480        DMAC_M_RABT = 0x02000000,
 481        DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 482        DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 483        DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 484        DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 485        DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 486        DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 487        DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 488        DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 489        DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 490        DMAC_M_RINT1 = 0x00000001,
 491};
 492
 493/* Receive descriptor bit */
 494enum RD_STS_BIT {
 495        RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
 496        RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 497        RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 498        RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 499        RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 500        RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 501        RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 502        RD_RFS1 = 0x00000001,
 503};
 504#define RDF1ST  RD_RFP1
 505#define RDFEND  RD_RFP0
 506#define RD_RFP  (RD_RFP1|RD_RFP0)
 507
 508/* FCFTR */
 509enum FCFTR_BIT {
 510        FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 511        FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 512        FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 513};
 514#define DEFAULT_FIFO_F_D_RFF    (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
 515#define DEFAULT_FIFO_F_D_RFD    (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
 516
 517/* Transfer descriptor bit */
 518enum TD_STS_BIT {
 519        TD_TACT = 0x80000000,
 520        TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 521        TD_TFP0 = 0x10000000,
 522};
 523#define TDF1ST  TD_TFP1
 524#define TDFEND  TD_TFP0
 525#define TD_TFP  (TD_TFP1|TD_TFP0)
 526
 527/* RMCR */
 528#define DEFAULT_RMCR_VALUE      0x00000000
 529
 530/* ECMR */
 531enum FELIC_MODE_BIT {
 532        ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 533        ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 534        ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 535        ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 536        ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 537        ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
 538        ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
 539};
 540
 541/* ECSR */
 542enum ECSR_STATUS_BIT {
 543        ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 544        ECSR_LCHNG = 0x04,
 545        ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 546};
 547
 548#define DEFAULT_ECSR_INIT       (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
 549                                 ECSR_ICD | ECSIPR_MPDIP)
 550
 551/* ECSIPR */
 552enum ECSIPR_STATUS_MASK_BIT {
 553        ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 554        ECSIPR_LCHNGIP = 0x04,
 555        ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 556};
 557
 558#define DEFAULT_ECSIPR_INIT     (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
 559                                 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 560
 561/* APR */
 562enum APR_BIT {
 563        APR_AP = 0x00000001,
 564};
 565
 566/* MPR */
 567enum MPR_BIT {
 568        MPR_MP = 0x00000001,
 569};
 570
 571/* TRSCER */
 572enum DESC_I_BIT {
 573        DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 574        DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 575        DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 576        DESC_I_RINT1 = 0x0001,
 577};
 578
 579/* RPADIR */
 580enum RPADIR_BIT {
 581        RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 582        RPADIR_PADR = 0x0003f,
 583};
 584
 585/* FDR */
 586#define DEFAULT_FDR_INIT        0x00000707
 587
 588enum phy_offsets {
 589        PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
 590        PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
 591        PHY_16 = 16,
 592};
 593
 594/* PHY_CTRL */
 595enum PHY_CTRL_BIT {
 596        PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
 597        PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
 598        PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
 599};
 600#define DM9161_PHY_C_ANEGEN 0   /* auto nego special */
 601
 602/* PHY_STAT */
 603enum PHY_STAT_BIT {
 604        PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
 605        PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
 606        PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
 607        PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
 608};
 609
 610/* PHY_ANA */
 611enum PHY_ANA_BIT {
 612        PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
 613        PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
 614        PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
 615        PHY_A_SEL = 0x001e,
 616};
 617/* PHY_ANL */
 618enum PHY_ANL_BIT {
 619        PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
 620        PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
 621        PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
 622        PHY_L_SEL = 0x001f,
 623};
 624
 625/* PHY_ANE */
 626enum PHY_ANE_BIT {
 627        PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
 628        PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
 629};
 630
 631/* DM9161 */
 632enum PHY_16_BIT {
 633        PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
 634        PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
 635        PHY_16_TXselect = 0x0400,
 636        PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
 637        PHY_16_Force100LNK = 0x0080,
 638        PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
 639        PHY_16_RPDCTR_EN = 0x0010,
 640        PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
 641        PHY_16_Sleepmode = 0x0002,
 642        PHY_16_RemoteLoopOut = 0x0001,
 643};
 644
 645#define POST_RX         0x08
 646#define POST_FW         0x04
 647#define POST0_RX        (POST_RX)
 648#define POST0_FW        (POST_FW)
 649#define POST1_RX        (POST_RX >> 2)
 650#define POST1_FW        (POST_FW >> 2)
 651#define POST_ALL        (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
 652
 653/* ARSTR */
 654enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 655
 656/* TSU_FWEN0 */
 657enum TSU_FWEN0_BIT {
 658        TSU_FWEN0_0 = 0x00000001,
 659};
 660
 661/* TSU_ADSBSY */
 662enum TSU_ADSBSY_BIT {
 663        TSU_ADSBSY_0 = 0x00000001,
 664};
 665
 666/* TSU_TEN */
 667enum TSU_TEN_BIT {
 668        TSU_TEN_0 = 0x80000000,
 669};
 670
 671/* TSU_FWSL0 */
 672enum TSU_FWSL0_BIT {
 673        TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 674        TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 675        TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 676};
 677
 678/* TSU_FWSLC */
 679enum TSU_FWSLC_BIT {
 680        TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 681        TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 682        TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 683        TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 684        TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 685};
 686
 687/* TSU_VTAGn */
 688#define TSU_VTAG_ENABLE         0x80000000
 689#define TSU_VTAG_VID_MASK       0x00000fff
 690
 691/*
 692 * The sh ether Tx buffer descriptors.
 693 * This structure should be 20 bytes.
 694 */
 695struct sh_eth_txdesc {
 696        u32 status;             /* TD0 */
 697#if defined(__LITTLE_ENDIAN)
 698        u16 pad0;               /* TD1 */
 699        u16 buffer_length;      /* TD1 */
 700#else
 701        u16 buffer_length;      /* TD1 */
 702        u16 pad0;               /* TD1 */
 703#endif
 704        u32 addr;               /* TD2 */
 705        u32 pad1;               /* padding data */
 706} __attribute__((aligned(2), packed));
 707
 708/*
 709 * The sh ether Rx buffer descriptors.
 710 * This structure should be 20 bytes.
 711 */
 712struct sh_eth_rxdesc {
 713        u32 status;             /* RD0 */
 714#if defined(__LITTLE_ENDIAN)
 715        u16 frame_length;       /* RD1 */
 716        u16 buffer_length;      /* RD1 */
 717#else
 718        u16 buffer_length;      /* RD1 */
 719        u16 frame_length;       /* RD1 */
 720#endif
 721        u32 addr;               /* RD2 */
 722        u32 pad0;               /* padding data */
 723} __attribute__((aligned(2), packed));
 724
 725/* This structure is used by each CPU dependency handling. */
 726struct sh_eth_cpu_data {
 727        /* optional functions */
 728        void (*chip_reset)(struct net_device *ndev);
 729        void (*set_duplex)(struct net_device *ndev);
 730        void (*set_rate)(struct net_device *ndev);
 731
 732        /* mandatory initialize value */
 733        unsigned long eesipr_value;
 734
 735        /* optional initialize value */
 736        unsigned long ecsr_value;
 737        unsigned long ecsipr_value;
 738        unsigned long fdr_value;
 739        unsigned long fcftr_value;
 740        unsigned long rpadir_value;
 741        unsigned long rmcr_value;
 742
 743        /* interrupt checking mask */
 744        unsigned long tx_check;
 745        unsigned long eesr_err_check;
 746        unsigned long tx_error_check;
 747
 748        /* hardware features */
 749        unsigned no_psr:1;              /* EtherC DO NOT have PSR */
 750        unsigned apr:1;                 /* EtherC have APR */
 751        unsigned mpr:1;                 /* EtherC have MPR */
 752        unsigned tpauser:1;             /* EtherC have TPAUSER */
 753        unsigned bculr:1;               /* EtherC have BCULR */
 754        unsigned tsu:1;                 /* EtherC have TSU */
 755        unsigned hw_swap:1;             /* E-DMAC have DE bit in EDMR */
 756        unsigned rpadir:1;              /* E-DMAC have RPADIR */
 757        unsigned no_trimd:1;            /* E-DMAC DO NOT have TRIMD */
 758        unsigned no_ade:1;      /* E-DMAC DO NOT have ADE bit in EESR */
 759        unsigned hw_crc:1;      /* E-DMAC have CSMR */
 760};
 761
 762struct sh_eth_private {
 763        struct platform_device *pdev;
 764        struct sh_eth_cpu_data *cd;
 765        const u16 *reg_offset;
 766        void __iomem *addr;
 767        void __iomem *tsu_addr;
 768        dma_addr_t rx_desc_dma;
 769        dma_addr_t tx_desc_dma;
 770        struct sh_eth_rxdesc *rx_ring;
 771        struct sh_eth_txdesc *tx_ring;
 772        struct sk_buff **rx_skbuff;
 773        struct sk_buff **tx_skbuff;
 774        struct timer_list timer;
 775        spinlock_t lock;
 776        u32 cur_rx, dirty_rx;   /* Producer/consumer ring indices */
 777        u32 cur_tx, dirty_tx;
 778        u32 rx_buf_sz;          /* Based on MTU+slack. */
 779        int edmac_endian;
 780        /* MII transceiver section. */
 781        u32 phy_id;                                     /* PHY ID */
 782        struct mii_bus *mii_bus;        /* MDIO bus control */
 783        struct phy_device *phydev;      /* PHY device control */
 784        enum phy_state link;
 785        phy_interface_t phy_interface;
 786        int msg_enable;
 787        int speed;
 788        int duplex;
 789        u32 rx_int_var, tx_int_var;     /* interrupt control variables */
 790        char post_rx;           /* POST receive */
 791        char post_fw;           /* POST forward */
 792        struct net_device_stats tsu_stats;      /* TSU forward status */
 793        int port;               /* for TSU */
 794        int vlan_num_ids;       /* for VLAN tag filter */
 795
 796        unsigned no_ether_link:1;
 797        unsigned ether_link_active_low:1;
 798};
 799
 800static inline void sh_eth_soft_swap(char *src, int len)
 801{
 802#ifdef __LITTLE_ENDIAN__
 803        u32 *p = (u32 *)src;
 804        u32 *maxp;
 805        maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 806
 807        for (; p < maxp; p++)
 808                *p = swab32(*p);
 809#endif
 810}
 811
 812static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
 813                                int enum_index)
 814{
 815        struct sh_eth_private *mdp = netdev_priv(ndev);
 816
 817        iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
 818}
 819
 820static inline unsigned long sh_eth_read(struct net_device *ndev,
 821                                        int enum_index)
 822{
 823        struct sh_eth_private *mdp = netdev_priv(ndev);
 824
 825        return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
 826}
 827
 828static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
 829                                          int enum_index)
 830{
 831        return mdp->tsu_addr + mdp->reg_offset[enum_index];
 832}
 833
 834static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
 835                                unsigned long data, int enum_index)
 836{
 837        iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
 838}
 839
 840static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
 841                                        int enum_index)
 842{
 843        return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
 844}
 845
 846#endif  /* #ifndef __SH_ETH_H__ */
 847