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6
7#include "qla_def.h"
8#include "qla_gbl.h"
9
10#include <linux/delay.h>
11#include <linux/slab.h>
12#include <linux/vmalloc.h>
13
14#include "qla_devtbl.h"
15
16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
18#endif
19
20#include <target/target_core_base.h>
21#include "qla_target.h"
22
23
24
25
26static int qla2x00_isp_firmware(scsi_qla_host_t *);
27static int qla2x00_setup_chip(scsi_qla_host_t *);
28static int qla2x00_init_rings(scsi_qla_host_t *);
29static int qla2x00_fw_ready(scsi_qla_host_t *);
30static int qla2x00_configure_hba(scsi_qla_host_t *);
31static int qla2x00_configure_loop(scsi_qla_host_t *);
32static int qla2x00_configure_local_loop(scsi_qla_host_t *);
33static int qla2x00_configure_fabric(scsi_qla_host_t *);
34static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
35static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
36 uint16_t *);
37
38static int qla2x00_restart_isp(scsi_qla_host_t *);
39
40static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
41static int qla84xx_init_chip(scsi_qla_host_t *);
42static int qla25xx_init_queues(struct qla_hw_data *);
43
44
45
46void
47qla2x00_sp_timeout(unsigned long __data)
48{
49 srb_t *sp = (srb_t *)__data;
50 struct srb_iocb *iocb;
51 fc_port_t *fcport = sp->fcport;
52 struct qla_hw_data *ha = fcport->vha->hw;
53 struct req_que *req;
54 unsigned long flags;
55
56 spin_lock_irqsave(&ha->hardware_lock, flags);
57 req = ha->req_q_map[0];
58 req->outstanding_cmds[sp->handle] = NULL;
59 iocb = &sp->u.iocb_cmd;
60 iocb->timeout(sp);
61 sp->free(fcport->vha, sp);
62 spin_unlock_irqrestore(&ha->hardware_lock, flags);
63}
64
65void
66qla2x00_sp_free(void *data, void *ptr)
67{
68 srb_t *sp = (srb_t *)ptr;
69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
70 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
71
72 del_timer(&iocb->timer);
73 mempool_free(sp, vha->hw->srb_mempool);
74
75 QLA_VHA_MARK_NOT_BUSY(vha);
76}
77
78
79
80static inline unsigned long
81qla2x00_get_async_timeout(struct scsi_qla_host *vha)
82{
83 unsigned long tmo;
84 struct qla_hw_data *ha = vha->hw;
85
86
87 tmo = ha->r_a_tov / 10 * 2;
88 if (!IS_FWI2_CAPABLE(ha)) {
89
90
91
92
93 tmo = ha->login_timeout;
94 }
95 return tmo;
96}
97
98static void
99qla2x00_async_iocb_timeout(void *data)
100{
101 srb_t *sp = (srb_t *)data;
102 fc_port_t *fcport = sp->fcport;
103
104 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
105 "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
106 sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
107 fcport->d_id.b.al_pa);
108
109 fcport->flags &= ~FCF_ASYNC_SENT;
110 if (sp->type == SRB_LOGIN_CMD) {
111 struct srb_iocb *lio = &sp->u.iocb_cmd;
112 qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
113
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
117 qla2x00_post_async_login_done_work(fcport->vha, fcport,
118 lio->u.logio.data);
119 }
120}
121
122static void
123qla2x00_async_login_sp_done(void *data, void *ptr, int res)
124{
125 srb_t *sp = (srb_t *)ptr;
126 struct srb_iocb *lio = &sp->u.iocb_cmd;
127 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
128
129 if (!test_bit(UNLOADING, &vha->dpc_flags))
130 qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
131 lio->u.logio.data);
132 sp->free(sp->fcport->vha, sp);
133}
134
135int
136qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
137 uint16_t *data)
138{
139 srb_t *sp;
140 struct srb_iocb *lio;
141 int rval;
142
143 rval = QLA_FUNCTION_FAILED;
144 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
145 if (!sp)
146 goto done;
147
148 sp->type = SRB_LOGIN_CMD;
149 sp->name = "login";
150 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
151
152 lio = &sp->u.iocb_cmd;
153 lio->timeout = qla2x00_async_iocb_timeout;
154 sp->done = qla2x00_async_login_sp_done;
155 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
156 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
157 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
158 rval = qla2x00_start_sp(sp);
159 if (rval != QLA_SUCCESS)
160 goto done_free_sp;
161
162 ql_dbg(ql_dbg_disc, vha, 0x2072,
163 "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
164 "retries=%d.\n", sp->handle, fcport->loop_id,
165 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
166 fcport->login_retry);
167 return rval;
168
169done_free_sp:
170 sp->free(fcport->vha, sp);
171done:
172 return rval;
173}
174
175static void
176qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
177{
178 srb_t *sp = (srb_t *)ptr;
179 struct srb_iocb *lio = &sp->u.iocb_cmd;
180 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
181
182 if (!test_bit(UNLOADING, &vha->dpc_flags))
183 qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
184 lio->u.logio.data);
185 sp->free(sp->fcport->vha, sp);
186}
187
188int
189qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
190{
191 srb_t *sp;
192 struct srb_iocb *lio;
193 int rval;
194
195 rval = QLA_FUNCTION_FAILED;
196 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
197 if (!sp)
198 goto done;
199
200 sp->type = SRB_LOGOUT_CMD;
201 sp->name = "logout";
202 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
203
204 lio = &sp->u.iocb_cmd;
205 lio->timeout = qla2x00_async_iocb_timeout;
206 sp->done = qla2x00_async_logout_sp_done;
207 rval = qla2x00_start_sp(sp);
208 if (rval != QLA_SUCCESS)
209 goto done_free_sp;
210
211 ql_dbg(ql_dbg_disc, vha, 0x2070,
212 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
213 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
214 fcport->d_id.b.area, fcport->d_id.b.al_pa);
215 return rval;
216
217done_free_sp:
218 sp->free(fcport->vha, sp);
219done:
220 return rval;
221}
222
223static void
224qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
225{
226 srb_t *sp = (srb_t *)ptr;
227 struct srb_iocb *lio = &sp->u.iocb_cmd;
228 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
229
230 if (!test_bit(UNLOADING, &vha->dpc_flags))
231 qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
232 lio->u.logio.data);
233 sp->free(sp->fcport->vha, sp);
234}
235
236int
237qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
238 uint16_t *data)
239{
240 srb_t *sp;
241 struct srb_iocb *lio;
242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
245 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
246 if (!sp)
247 goto done;
248
249 sp->type = SRB_ADISC_CMD;
250 sp->name = "adisc";
251 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
252
253 lio = &sp->u.iocb_cmd;
254 lio->timeout = qla2x00_async_iocb_timeout;
255 sp->done = qla2x00_async_adisc_sp_done;
256 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
257 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
258 rval = qla2x00_start_sp(sp);
259 if (rval != QLA_SUCCESS)
260 goto done_free_sp;
261
262 ql_dbg(ql_dbg_disc, vha, 0x206f,
263 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
264 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
265 fcport->d_id.b.area, fcport->d_id.b.al_pa);
266 return rval;
267
268done_free_sp:
269 sp->free(fcport->vha, sp);
270done:
271 return rval;
272}
273
274static void
275qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
276{
277 srb_t *sp = (srb_t *)ptr;
278 struct srb_iocb *iocb = &sp->u.iocb_cmd;
279 struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
280 uint32_t flags;
281 uint16_t lun;
282 int rval;
283
284 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
285 flags = iocb->u.tmf.flags;
286 lun = (uint16_t)iocb->u.tmf.lun;
287
288
289 rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
290 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
291 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
292
293 if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
294 ql_dbg(ql_dbg_taskm, vha, 0x8030,
295 "TM IOCB failed (%x).\n", rval);
296 }
297 }
298 sp->free(sp->fcport->vha, sp);
299}
300
301int
302qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
303 uint32_t tag)
304{
305 struct scsi_qla_host *vha = fcport->vha;
306 srb_t *sp;
307 struct srb_iocb *tcf;
308 int rval;
309
310 rval = QLA_FUNCTION_FAILED;
311 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
312 if (!sp)
313 goto done;
314
315 sp->type = SRB_TM_CMD;
316 sp->name = "tmf";
317 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
318
319 tcf = &sp->u.iocb_cmd;
320 tcf->u.tmf.flags = tm_flags;
321 tcf->u.tmf.lun = lun;
322 tcf->u.tmf.data = tag;
323 tcf->timeout = qla2x00_async_iocb_timeout;
324 sp->done = qla2x00_async_tm_cmd_done;
325
326 rval = qla2x00_start_sp(sp);
327 if (rval != QLA_SUCCESS)
328 goto done_free_sp;
329
330 ql_dbg(ql_dbg_taskm, vha, 0x802f,
331 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
332 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
333 fcport->d_id.b.area, fcport->d_id.b.al_pa);
334 return rval;
335
336done_free_sp:
337 sp->free(fcport->vha, sp);
338done:
339 return rval;
340}
341
342void
343qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
344 uint16_t *data)
345{
346 int rval;
347
348 switch (data[0]) {
349 case MBS_COMMAND_COMPLETE:
350
351
352
353
354
355 rval = qla2x00_get_port_database(vha, fcport, 0);
356 if (rval == QLA_NOT_LOGGED_IN) {
357 fcport->flags &= ~FCF_ASYNC_SENT;
358 fcport->flags |= FCF_LOGIN_NEEDED;
359 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
360 break;
361 }
362
363 if (rval != QLA_SUCCESS) {
364 qla2x00_post_async_logout_work(vha, fcport, NULL);
365 qla2x00_post_async_login_work(vha, fcport, NULL);
366 break;
367 }
368 if (fcport->flags & FCF_FCP2_DEVICE) {
369 qla2x00_post_async_adisc_work(vha, fcport, data);
370 break;
371 }
372 qla2x00_update_fcport(vha, fcport);
373 break;
374 case MBS_COMMAND_ERROR:
375 fcport->flags &= ~FCF_ASYNC_SENT;
376 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
377 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
378 else
379 qla2x00_mark_device_lost(vha, fcport, 1, 0);
380 break;
381 case MBS_PORT_ID_USED:
382 fcport->loop_id = data[1];
383 qla2x00_post_async_logout_work(vha, fcport, NULL);
384 qla2x00_post_async_login_work(vha, fcport, NULL);
385 break;
386 case MBS_LOOP_ID_USED:
387 fcport->loop_id++;
388 rval = qla2x00_find_new_loop_id(vha, fcport);
389 if (rval != QLA_SUCCESS) {
390 fcport->flags &= ~FCF_ASYNC_SENT;
391 qla2x00_mark_device_lost(vha, fcport, 1, 0);
392 break;
393 }
394 qla2x00_post_async_login_work(vha, fcport, NULL);
395 break;
396 }
397 return;
398}
399
400void
401qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
402 uint16_t *data)
403{
404 qla2x00_mark_device_lost(vha, fcport, 1, 0);
405 return;
406}
407
408void
409qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
410 uint16_t *data)
411{
412 if (data[0] == MBS_COMMAND_COMPLETE) {
413 qla2x00_update_fcport(vha, fcport);
414
415 return;
416 }
417
418
419 fcport->flags &= ~FCF_ASYNC_SENT;
420 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
421 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
422 else
423 qla2x00_mark_device_lost(vha, fcport, 1, 0);
424
425 return;
426}
427
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430
431
432
433
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435
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439
440
441
442int
443qla2x00_initialize_adapter(scsi_qla_host_t *vha)
444{
445 int rval;
446 struct qla_hw_data *ha = vha->hw;
447 struct req_que *req = ha->req_q_map[0];
448
449
450 vha->flags.online = 0;
451 ha->flags.chip_reset_done = 0;
452 vha->flags.reset_active = 0;
453 ha->flags.pci_channel_io_perm_failure = 0;
454 ha->flags.eeh_busy = 0;
455 ha->flags.thermal_supported = 1;
456 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
457 atomic_set(&vha->loop_state, LOOP_DOWN);
458 vha->device_flags = DFLG_NO_CABLE;
459 vha->dpc_flags = 0;
460 vha->flags.management_server_logged_in = 0;
461 vha->marker_needed = 0;
462 ha->isp_abort_cnt = 0;
463 ha->beacon_blink_led = 0;
464
465 set_bit(0, ha->req_qid_map);
466 set_bit(0, ha->rsp_qid_map);
467
468 ql_dbg(ql_dbg_init, vha, 0x0040,
469 "Configuring PCI space...\n");
470 rval = ha->isp_ops->pci_config(vha);
471 if (rval) {
472 ql_log(ql_log_warn, vha, 0x0044,
473 "Unable to configure PCI space.\n");
474 return (rval);
475 }
476
477 ha->isp_ops->reset_chip(vha);
478
479 rval = qla2xxx_get_flash_info(vha);
480 if (rval) {
481 ql_log(ql_log_fatal, vha, 0x004f,
482 "Unable to validate FLASH data.\n");
483 return (rval);
484 }
485
486 ha->isp_ops->get_flash_version(vha, req->ring);
487 ql_dbg(ql_dbg_init, vha, 0x0061,
488 "Configure NVRAM parameters...\n");
489
490 ha->isp_ops->nvram_config(vha);
491
492 if (ha->flags.disable_serdes) {
493
494 ql_log(ql_log_info, vha, 0x0077,
495 "Masking HBA WWPN "
496 "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
497 vha->port_name[0], vha->port_name[1],
498 vha->port_name[2], vha->port_name[3],
499 vha->port_name[4], vha->port_name[5],
500 vha->port_name[6], vha->port_name[7]);
501 return QLA_FUNCTION_FAILED;
502 }
503
504 ql_dbg(ql_dbg_init, vha, 0x0078,
505 "Verifying loaded RISC code...\n");
506
507 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
508 rval = ha->isp_ops->chip_diag(vha);
509 if (rval)
510 return (rval);
511 rval = qla2x00_setup_chip(vha);
512 if (rval)
513 return (rval);
514 }
515
516 if (IS_QLA84XX(ha)) {
517 ha->cs84xx = qla84xx_get_chip(vha);
518 if (!ha->cs84xx) {
519 ql_log(ql_log_warn, vha, 0x00d0,
520 "Unable to configure ISP84XX.\n");
521 return QLA_FUNCTION_FAILED;
522 }
523 }
524
525 if (qla_ini_mode_enabled(vha))
526 rval = qla2x00_init_rings(vha);
527
528 ha->flags.chip_reset_done = 1;
529
530 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
531
532 rval = qla84xx_init_chip(vha);
533 if (rval != QLA_SUCCESS) {
534 ql_log(ql_log_warn, vha, 0x00d4,
535 "Unable to initialize ISP84XX.\n");
536 qla84xx_put_chip(vha);
537 }
538 }
539
540 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
541 qla24xx_read_fcp_prio_cfg(vha);
542
543 return (rval);
544}
545
546
547
548
549
550
551
552int
553qla2100_pci_config(scsi_qla_host_t *vha)
554{
555 uint16_t w;
556 unsigned long flags;
557 struct qla_hw_data *ha = vha->hw;
558 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
559
560 pci_set_master(ha->pdev);
561 pci_try_set_mwi(ha->pdev);
562
563 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
564 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
565 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
566
567 pci_disable_rom(ha->pdev);
568
569
570 spin_lock_irqsave(&ha->hardware_lock, flags);
571 ha->pci_attr = RD_REG_WORD(®->ctrl_status);
572 spin_unlock_irqrestore(&ha->hardware_lock, flags);
573
574 return QLA_SUCCESS;
575}
576
577
578
579
580
581
582
583int
584qla2300_pci_config(scsi_qla_host_t *vha)
585{
586 uint16_t w;
587 unsigned long flags = 0;
588 uint32_t cnt;
589 struct qla_hw_data *ha = vha->hw;
590 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
591
592 pci_set_master(ha->pdev);
593 pci_try_set_mwi(ha->pdev);
594
595 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
596 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
597
598 if (IS_QLA2322(ha) || IS_QLA6322(ha))
599 w &= ~PCI_COMMAND_INTX_DISABLE;
600 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
601
602
603
604
605
606
607
608
609 if (IS_QLA2300(ha)) {
610 spin_lock_irqsave(&ha->hardware_lock, flags);
611
612
613 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
614 for (cnt = 0; cnt < 30000; cnt++) {
615 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
616 break;
617
618 udelay(10);
619 }
620
621
622 WRT_REG_WORD(®->ctrl_status, 0x20);
623 RD_REG_WORD(®->ctrl_status);
624
625
626 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
627
628 if (ha->fb_rev == FPM_2300)
629 pci_clear_mwi(ha->pdev);
630
631
632 WRT_REG_WORD(®->ctrl_status, 0x0);
633 RD_REG_WORD(®->ctrl_status);
634
635
636 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
637 for (cnt = 0; cnt < 30000; cnt++) {
638 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0)
639 break;
640
641 udelay(10);
642 }
643
644 spin_unlock_irqrestore(&ha->hardware_lock, flags);
645 }
646
647 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
648
649 pci_disable_rom(ha->pdev);
650
651
652 spin_lock_irqsave(&ha->hardware_lock, flags);
653 ha->pci_attr = RD_REG_WORD(®->ctrl_status);
654 spin_unlock_irqrestore(&ha->hardware_lock, flags);
655
656 return QLA_SUCCESS;
657}
658
659
660
661
662
663
664
665int
666qla24xx_pci_config(scsi_qla_host_t *vha)
667{
668 uint16_t w;
669 unsigned long flags = 0;
670 struct qla_hw_data *ha = vha->hw;
671 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
672
673 pci_set_master(ha->pdev);
674 pci_try_set_mwi(ha->pdev);
675
676 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
677 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
678 w &= ~PCI_COMMAND_INTX_DISABLE;
679 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
680
681 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
682
683
684 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
685 pcix_set_mmrbc(ha->pdev, 2048);
686
687
688 if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
689 pcie_set_readrq(ha->pdev, 2048);
690
691 pci_disable_rom(ha->pdev);
692
693 ha->chip_revision = ha->pdev->revision;
694
695
696 spin_lock_irqsave(&ha->hardware_lock, flags);
697 ha->pci_attr = RD_REG_DWORD(®->ctrl_status);
698 spin_unlock_irqrestore(&ha->hardware_lock, flags);
699
700 return QLA_SUCCESS;
701}
702
703
704
705
706
707
708
709int
710qla25xx_pci_config(scsi_qla_host_t *vha)
711{
712 uint16_t w;
713 struct qla_hw_data *ha = vha->hw;
714
715 pci_set_master(ha->pdev);
716 pci_try_set_mwi(ha->pdev);
717
718 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
719 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
720 w &= ~PCI_COMMAND_INTX_DISABLE;
721 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
722
723
724 if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
725 pcie_set_readrq(ha->pdev, 2048);
726
727 pci_disable_rom(ha->pdev);
728
729 ha->chip_revision = ha->pdev->revision;
730
731 return QLA_SUCCESS;
732}
733
734
735
736
737
738
739
740static int
741qla2x00_isp_firmware(scsi_qla_host_t *vha)
742{
743 int rval;
744 uint16_t loop_id, topo, sw_cap;
745 uint8_t domain, area, al_pa;
746 struct qla_hw_data *ha = vha->hw;
747
748
749 rval = QLA_FUNCTION_FAILED;
750
751 if (ha->flags.disable_risc_code_load) {
752 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
753
754
755 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
756 if (rval == QLA_SUCCESS) {
757
758 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
759 &area, &domain, &topo, &sw_cap);
760 }
761 }
762
763 if (rval)
764 ql_dbg(ql_dbg_init, vha, 0x007a,
765 "**** Load RISC code ****.\n");
766
767 return (rval);
768}
769
770
771
772
773
774
775
776void
777qla2x00_reset_chip(scsi_qla_host_t *vha)
778{
779 unsigned long flags = 0;
780 struct qla_hw_data *ha = vha->hw;
781 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
782 uint32_t cnt;
783 uint16_t cmd;
784
785 if (unlikely(pci_channel_offline(ha->pdev)))
786 return;
787
788 ha->isp_ops->disable_intrs(ha);
789
790 spin_lock_irqsave(&ha->hardware_lock, flags);
791
792
793 cmd = 0;
794 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
795 cmd &= ~PCI_COMMAND_MASTER;
796 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
797
798 if (!IS_QLA2100(ha)) {
799
800 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
801 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
802 for (cnt = 0; cnt < 30000; cnt++) {
803 if ((RD_REG_WORD(®->hccr) &
804 HCCR_RISC_PAUSE) != 0)
805 break;
806 udelay(100);
807 }
808 } else {
809 RD_REG_WORD(®->hccr);
810 udelay(10);
811 }
812
813
814 WRT_REG_WORD(®->ctrl_status, 0x20);
815 RD_REG_WORD(®->ctrl_status);
816
817
818 WRT_REG_WORD(®->fpm_diag_config, 0x100);
819 RD_REG_WORD(®->fpm_diag_config);
820
821
822 if (!IS_QLA2200(ha)) {
823 WRT_REG_WORD(®->fpm_diag_config, 0x0);
824 RD_REG_WORD(®->fpm_diag_config);
825 }
826
827
828 WRT_REG_WORD(®->ctrl_status, 0x10);
829 RD_REG_WORD(®->ctrl_status);
830
831
832 if (IS_QLA2200(ha)) {
833 WRT_FB_CMD_REG(ha, reg, 0xa000);
834 RD_FB_CMD_REG(ha, reg);
835 } else {
836 WRT_FB_CMD_REG(ha, reg, 0x00fc);
837
838
839 for (cnt = 0; cnt < 3000; cnt++) {
840 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
841 break;
842 udelay(100);
843 }
844 }
845
846
847 WRT_REG_WORD(®->ctrl_status, 0);
848 RD_REG_WORD(®->ctrl_status);
849
850
851 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
852 RD_REG_WORD(®->hccr);
853
854
855 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
856 RD_REG_WORD(®->hccr);
857 }
858
859 WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT);
860 WRT_REG_WORD(®->hccr, HCCR_CLR_HOST_INT);
861
862
863 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
864
865
866 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
867
868
869
870
871
872 udelay(20);
873 for (cnt = 30000; cnt; cnt--) {
874 if ((RD_REG_WORD(®->ctrl_status) &
875 CSR_ISP_SOFT_RESET) == 0)
876 break;
877 udelay(100);
878 }
879 } else
880 udelay(10);
881
882
883 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
884
885 WRT_REG_WORD(®->semaphore, 0);
886
887
888 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
889 RD_REG_WORD(®->hccr);
890
891 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
892 for (cnt = 0; cnt < 30000; cnt++) {
893 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
894 break;
895
896 udelay(100);
897 }
898 } else
899 udelay(100);
900
901
902 cmd |= PCI_COMMAND_MASTER;
903 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
904
905
906 if (!IS_QLA2100(ha)) {
907 WRT_REG_WORD(®->hccr, HCCR_DISABLE_PARITY_PAUSE);
908 RD_REG_WORD(®->hccr);
909 }
910
911 spin_unlock_irqrestore(&ha->hardware_lock, flags);
912}
913
914
915
916
917
918
919int
920qla81xx_reset_mpi(scsi_qla_host_t *vha)
921{
922 uint16_t mb[4] = {0x1010, 0, 1, 0};
923
924 if (!IS_QLA81XX(vha->hw))
925 return QLA_SUCCESS;
926
927 return qla81xx_write_mpi_register(vha, mb);
928}
929
930
931
932
933
934
935
936static inline void
937qla24xx_reset_risc(scsi_qla_host_t *vha)
938{
939 unsigned long flags = 0;
940 struct qla_hw_data *ha = vha->hw;
941 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
942 uint32_t cnt, d2;
943 uint16_t wd;
944 static int abts_cnt;
945
946 spin_lock_irqsave(&ha->hardware_lock, flags);
947
948
949 WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
950 for (cnt = 0; cnt < 30000; cnt++) {
951 if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
952 break;
953
954 udelay(10);
955 }
956
957 WRT_REG_DWORD(®->ctrl_status,
958 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
959 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
960
961 udelay(100);
962
963 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
964 for (cnt = 10000 ; cnt && d2; cnt--) {
965 udelay(5);
966 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
967 barrier();
968 }
969
970
971 d2 = RD_REG_DWORD(®->ctrl_status);
972 for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
973 udelay(5);
974 d2 = RD_REG_DWORD(®->ctrl_status);
975 barrier();
976 }
977
978
979 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
980 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
981 if (++abts_cnt < 5) {
982 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
983 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
984 } else {
985
986
987
988
989 abts_cnt = 0;
990 vha->flags.online = 0;
991 }
992 }
993 }
994
995 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
996 RD_REG_DWORD(®->hccr);
997
998 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
999 RD_REG_DWORD(®->hccr);
1000
1001 WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET);
1002 RD_REG_DWORD(®->hccr);
1003
1004 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1005 for (cnt = 6000000 ; cnt && d2; cnt--) {
1006 udelay(5);
1007 d2 = (uint32_t) RD_REG_WORD(®->mailbox0);
1008 barrier();
1009 }
1010
1011 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1012
1013 if (IS_NOPOLLING_TYPE(ha))
1014 ha->isp_ops->enable_intrs(ha);
1015}
1016
1017
1018
1019
1020
1021
1022
1023void
1024qla24xx_reset_chip(scsi_qla_host_t *vha)
1025{
1026 struct qla_hw_data *ha = vha->hw;
1027
1028 if (pci_channel_offline(ha->pdev) &&
1029 ha->flags.pci_channel_io_perm_failure) {
1030 return;
1031 }
1032
1033 ha->isp_ops->disable_intrs(ha);
1034
1035
1036 qla24xx_reset_risc(vha);
1037}
1038
1039
1040
1041
1042
1043
1044
1045int
1046qla2x00_chip_diag(scsi_qla_host_t *vha)
1047{
1048 int rval;
1049 struct qla_hw_data *ha = vha->hw;
1050 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1051 unsigned long flags = 0;
1052 uint16_t data;
1053 uint32_t cnt;
1054 uint16_t mb[5];
1055 struct req_que *req = ha->req_q_map[0];
1056
1057
1058 rval = QLA_FUNCTION_FAILED;
1059
1060 ql_dbg(ql_dbg_init, vha, 0x007b,
1061 "Testing device at %lx.\n", (u_long)®->flash_address);
1062
1063 spin_lock_irqsave(&ha->hardware_lock, flags);
1064
1065
1066 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
1067
1068
1069
1070
1071
1072 udelay(20);
1073 data = qla2x00_debounce_register(®->ctrl_status);
1074 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
1075 udelay(5);
1076 data = RD_REG_WORD(®->ctrl_status);
1077 barrier();
1078 }
1079
1080 if (!cnt)
1081 goto chip_diag_failed;
1082
1083 ql_dbg(ql_dbg_init, vha, 0x007c,
1084 "Reset register cleared by chip reset.\n");
1085
1086
1087 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
1088 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
1089
1090
1091 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1092 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
1093 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
1094 udelay(5);
1095 data = RD_MAILBOX_REG(ha, reg, 0);
1096 barrier();
1097 }
1098 } else
1099 udelay(10);
1100
1101 if (!cnt)
1102 goto chip_diag_failed;
1103
1104
1105 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
1106
1107 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
1108 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
1109 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
1110 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
1111 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
1112 mb[3] != PROD_ID_3) {
1113 ql_log(ql_log_warn, vha, 0x0062,
1114 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
1115 mb[1], mb[2], mb[3]);
1116
1117 goto chip_diag_failed;
1118 }
1119 ha->product_id[0] = mb[1];
1120 ha->product_id[1] = mb[2];
1121 ha->product_id[2] = mb[3];
1122 ha->product_id[3] = mb[4];
1123
1124
1125 if (req->length > 1024)
1126 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
1127 else
1128 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
1129 req->length;
1130
1131 if (IS_QLA2200(ha) &&
1132 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
1133
1134 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1135
1136 ha->device_type |= DT_ISP2200A;
1137 ha->fw_transfer_size = 128;
1138 }
1139
1140
1141 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1142
1143 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
1144 rval = qla2x00_mbx_reg_test(vha);
1145 if (rval)
1146 ql_log(ql_log_warn, vha, 0x0080,
1147 "Failed mailbox send register test.\n");
1148 else
1149
1150 rval = QLA_SUCCESS;
1151 spin_lock_irqsave(&ha->hardware_lock, flags);
1152
1153chip_diag_failed:
1154 if (rval)
1155 ql_log(ql_log_info, vha, 0x0081,
1156 "Chip diagnostics **** FAILED ****.\n");
1157
1158 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1159
1160 return (rval);
1161}
1162
1163
1164
1165
1166
1167
1168
1169int
1170qla24xx_chip_diag(scsi_qla_host_t *vha)
1171{
1172 int rval;
1173 struct qla_hw_data *ha = vha->hw;
1174 struct req_que *req = ha->req_q_map[0];
1175
1176 if (IS_QLA82XX(ha))
1177 return QLA_SUCCESS;
1178
1179 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
1180
1181 rval = qla2x00_mbx_reg_test(vha);
1182 if (rval) {
1183 ql_log(ql_log_warn, vha, 0x0082,
1184 "Failed mailbox send register test.\n");
1185 } else {
1186
1187 rval = QLA_SUCCESS;
1188 }
1189
1190 return rval;
1191}
1192
1193void
1194qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
1195{
1196 int rval;
1197 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
1198 eft_size, fce_size, mq_size;
1199 dma_addr_t tc_dma;
1200 void *tc;
1201 struct qla_hw_data *ha = vha->hw;
1202 struct req_que *req = ha->req_q_map[0];
1203 struct rsp_que *rsp = ha->rsp_q_map[0];
1204
1205 if (ha->fw_dump) {
1206 ql_dbg(ql_dbg_init, vha, 0x00bd,
1207 "Firmware dump already allocated.\n");
1208 return;
1209 }
1210
1211 ha->fw_dumped = 0;
1212 fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
1213 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
1214 fixed_size = sizeof(struct qla2100_fw_dump);
1215 } else if (IS_QLA23XX(ha)) {
1216 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
1217 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
1218 sizeof(uint16_t);
1219 } else if (IS_FWI2_CAPABLE(ha)) {
1220 if (IS_QLA83XX(ha))
1221 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
1222 else if (IS_QLA81XX(ha))
1223 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
1224 else if (IS_QLA25XX(ha))
1225 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
1226 else
1227 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
1228 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
1229 sizeof(uint32_t);
1230 if (ha->mqenable) {
1231 if (!IS_QLA83XX(ha))
1232 mq_size = sizeof(struct qla2xxx_mq_chain);
1233
1234
1235
1236
1237 mq_size += ha->max_req_queues *
1238 (req->length * sizeof(request_t));
1239 mq_size += ha->max_rsp_queues *
1240 (rsp->length * sizeof(response_t));
1241 }
1242 if (ha->tgt.atio_q_length)
1243 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
1244
1245 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
1246 goto try_eft;
1247
1248 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
1249 GFP_KERNEL);
1250 if (!tc) {
1251 ql_log(ql_log_warn, vha, 0x00be,
1252 "Unable to allocate (%d KB) for FCE.\n",
1253 FCE_SIZE / 1024);
1254 goto try_eft;
1255 }
1256
1257 memset(tc, 0, FCE_SIZE);
1258 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
1259 ha->fce_mb, &ha->fce_bufs);
1260 if (rval) {
1261 ql_log(ql_log_warn, vha, 0x00bf,
1262 "Unable to initialize FCE (%d).\n", rval);
1263 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
1264 tc_dma);
1265 ha->flags.fce_enabled = 0;
1266 goto try_eft;
1267 }
1268 ql_dbg(ql_dbg_init, vha, 0x00c0,
1269 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
1270
1271 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
1272 ha->flags.fce_enabled = 1;
1273 ha->fce_dma = tc_dma;
1274 ha->fce = tc;
1275try_eft:
1276
1277 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
1278 GFP_KERNEL);
1279 if (!tc) {
1280 ql_log(ql_log_warn, vha, 0x00c1,
1281 "Unable to allocate (%d KB) for EFT.\n",
1282 EFT_SIZE / 1024);
1283 goto cont_alloc;
1284 }
1285
1286 memset(tc, 0, EFT_SIZE);
1287 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
1288 if (rval) {
1289 ql_log(ql_log_warn, vha, 0x00c2,
1290 "Unable to initialize EFT (%d).\n", rval);
1291 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
1292 tc_dma);
1293 goto cont_alloc;
1294 }
1295 ql_dbg(ql_dbg_init, vha, 0x00c3,
1296 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
1297
1298 eft_size = EFT_SIZE;
1299 ha->eft_dma = tc_dma;
1300 ha->eft = tc;
1301 }
1302cont_alloc:
1303 req_q_size = req->length * sizeof(request_t);
1304 rsp_q_size = rsp->length * sizeof(response_t);
1305
1306 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
1307 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
1308 ha->chain_offset = dump_size;
1309 dump_size += mq_size + fce_size;
1310
1311 ha->fw_dump = vmalloc(dump_size);
1312 if (!ha->fw_dump) {
1313 ql_log(ql_log_warn, vha, 0x00c4,
1314 "Unable to allocate (%d KB) for firmware dump.\n",
1315 dump_size / 1024);
1316
1317 if (ha->fce) {
1318 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
1319 ha->fce_dma);
1320 ha->fce = NULL;
1321 ha->fce_dma = 0;
1322 }
1323
1324 if (ha->eft) {
1325 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
1326 ha->eft_dma);
1327 ha->eft = NULL;
1328 ha->eft_dma = 0;
1329 }
1330 return;
1331 }
1332 ql_dbg(ql_dbg_init, vha, 0x00c5,
1333 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
1334
1335 ha->fw_dump_len = dump_size;
1336 ha->fw_dump->signature[0] = 'Q';
1337 ha->fw_dump->signature[1] = 'L';
1338 ha->fw_dump->signature[2] = 'G';
1339 ha->fw_dump->signature[3] = 'C';
1340 ha->fw_dump->version = __constant_htonl(1);
1341
1342 ha->fw_dump->fixed_size = htonl(fixed_size);
1343 ha->fw_dump->mem_size = htonl(mem_size);
1344 ha->fw_dump->req_q_size = htonl(req_q_size);
1345 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
1346
1347 ha->fw_dump->eft_size = htonl(eft_size);
1348 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
1349 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
1350
1351 ha->fw_dump->header_size =
1352 htonl(offsetof(struct qla2xxx_fw_dump, isp));
1353}
1354
1355static int
1356qla81xx_mpi_sync(scsi_qla_host_t *vha)
1357{
1358#define MPS_MASK 0xe0
1359 int rval;
1360 uint16_t dc;
1361 uint32_t dw;
1362
1363 if (!IS_QLA81XX(vha->hw))
1364 return QLA_SUCCESS;
1365
1366 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
1367 if (rval != QLA_SUCCESS) {
1368 ql_log(ql_log_warn, vha, 0x0105,
1369 "Unable to acquire semaphore.\n");
1370 goto done;
1371 }
1372
1373 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
1374 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
1375 if (rval != QLA_SUCCESS) {
1376 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
1377 goto done_release;
1378 }
1379
1380 dc &= MPS_MASK;
1381 if (dc == (dw & MPS_MASK))
1382 goto done_release;
1383
1384 dw &= ~MPS_MASK;
1385 dw |= dc;
1386 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
1387 if (rval != QLA_SUCCESS) {
1388 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
1389 }
1390
1391done_release:
1392 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
1393 if (rval != QLA_SUCCESS) {
1394 ql_log(ql_log_warn, vha, 0x006d,
1395 "Unable to release semaphore.\n");
1396 }
1397
1398done:
1399 return rval;
1400}
1401
1402
1403
1404
1405
1406
1407
1408static int
1409qla2x00_setup_chip(scsi_qla_host_t *vha)
1410{
1411 int rval;
1412 uint32_t srisc_address = 0;
1413 struct qla_hw_data *ha = vha->hw;
1414 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1415 unsigned long flags;
1416 uint16_t fw_major_version;
1417
1418 if (IS_QLA82XX(ha)) {
1419 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1420 if (rval == QLA_SUCCESS) {
1421 qla2x00_stop_firmware(vha);
1422 goto enable_82xx_npiv;
1423 } else
1424 goto failed;
1425 }
1426
1427 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1428
1429 spin_lock_irqsave(&ha->hardware_lock, flags);
1430 WRT_REG_WORD(®->hccr, (HCCR_ENABLE_PARITY + 0x0));
1431 RD_REG_WORD(®->hccr);
1432 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1433 }
1434
1435 qla81xx_mpi_sync(vha);
1436
1437
1438 rval = ha->isp_ops->load_risc(vha, &srisc_address);
1439 if (rval == QLA_SUCCESS) {
1440 ql_dbg(ql_dbg_init, vha, 0x00c9,
1441 "Verifying Checksum of loaded RISC code.\n");
1442
1443 rval = qla2x00_verify_checksum(vha, srisc_address);
1444 if (rval == QLA_SUCCESS) {
1445
1446 ql_dbg(ql_dbg_init, vha, 0x00ca,
1447 "Starting firmware.\n");
1448
1449 rval = qla2x00_execute_fw(vha, srisc_address);
1450
1451 if (rval == QLA_SUCCESS) {
1452enable_82xx_npiv:
1453 fw_major_version = ha->fw_major_version;
1454 if (IS_QLA82XX(ha))
1455 qla82xx_check_md_needed(vha);
1456 else
1457 rval = qla2x00_get_fw_version(vha);
1458 if (rval != QLA_SUCCESS)
1459 goto failed;
1460 ha->flags.npiv_supported = 0;
1461 if (IS_QLA2XXX_MIDTYPE(ha) &&
1462 (ha->fw_attributes & BIT_2)) {
1463 ha->flags.npiv_supported = 1;
1464 if ((!ha->max_npiv_vports) ||
1465 ((ha->max_npiv_vports + 1) %
1466 MIN_MULTI_ID_FABRIC))
1467 ha->max_npiv_vports =
1468 MIN_MULTI_ID_FABRIC - 1;
1469 }
1470 qla2x00_get_resource_cnts(vha, NULL,
1471 &ha->fw_xcb_count, NULL, NULL,
1472 &ha->max_npiv_vports, NULL);
1473
1474 if (!fw_major_version && ql2xallocfwdump
1475 && !IS_QLA82XX(ha))
1476 qla2x00_alloc_fw_dump(vha);
1477 }
1478 } else {
1479 ql_log(ql_log_fatal, vha, 0x00cd,
1480 "ISP Firmware failed checksum.\n");
1481 goto failed;
1482 }
1483 }
1484
1485 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
1486
1487 spin_lock_irqsave(&ha->hardware_lock, flags);
1488 if (IS_QLA2300(ha))
1489
1490 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x1);
1491 else
1492
1493 WRT_REG_WORD(®->hccr, HCCR_ENABLE_PARITY + 0x7);
1494 RD_REG_WORD(®->hccr);
1495 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1496 }
1497
1498 if (IS_QLA83XX(ha))
1499 goto skip_fac_check;
1500
1501 if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1502 uint32_t size;
1503
1504 rval = qla81xx_fac_get_sector_size(vha, &size);
1505 if (rval == QLA_SUCCESS) {
1506 ha->flags.fac_supported = 1;
1507 ha->fdt_block_size = size << 2;
1508 } else {
1509 ql_log(ql_log_warn, vha, 0x00ce,
1510 "Unsupported FAC firmware (%d.%02d.%02d).\n",
1511 ha->fw_major_version, ha->fw_minor_version,
1512 ha->fw_subminor_version);
1513skip_fac_check:
1514 if (IS_QLA83XX(ha)) {
1515 ha->flags.fac_supported = 0;
1516 rval = QLA_SUCCESS;
1517 }
1518 }
1519 }
1520failed:
1521 if (rval) {
1522 ql_log(ql_log_fatal, vha, 0x00cf,
1523 "Setup chip ****FAILED****.\n");
1524 }
1525
1526 return (rval);
1527}
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538void
1539qla2x00_init_response_q_entries(struct rsp_que *rsp)
1540{
1541 uint16_t cnt;
1542 response_t *pkt;
1543
1544 rsp->ring_ptr = rsp->ring;
1545 rsp->ring_index = 0;
1546 rsp->status_srb = NULL;
1547 pkt = rsp->ring_ptr;
1548 for (cnt = 0; cnt < rsp->length; cnt++) {
1549 pkt->signature = RESPONSE_PROCESSED;
1550 pkt++;
1551 }
1552}
1553
1554
1555
1556
1557
1558
1559
1560void
1561qla2x00_update_fw_options(scsi_qla_host_t *vha)
1562{
1563 uint16_t swing, emphasis, tx_sens, rx_sens;
1564 struct qla_hw_data *ha = vha->hw;
1565
1566 memset(ha->fw_options, 0, sizeof(ha->fw_options));
1567 qla2x00_get_fw_options(vha, ha->fw_options);
1568
1569 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1570 return;
1571
1572
1573 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
1574 "Serial link options.\n");
1575 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
1576 (uint8_t *)&ha->fw_seriallink_options,
1577 sizeof(ha->fw_seriallink_options));
1578
1579 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1580 if (ha->fw_seriallink_options[3] & BIT_2) {
1581 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
1582
1583
1584 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1585 emphasis = (ha->fw_seriallink_options[2] &
1586 (BIT_4 | BIT_3)) >> 3;
1587 tx_sens = ha->fw_seriallink_options[0] &
1588 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1589 rx_sens = (ha->fw_seriallink_options[0] &
1590 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1591 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
1592 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1593 if (rx_sens == 0x0)
1594 rx_sens = 0x3;
1595 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
1596 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1597 ha->fw_options[10] |= BIT_5 |
1598 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1599 (tx_sens & (BIT_1 | BIT_0));
1600
1601
1602 swing = (ha->fw_seriallink_options[2] &
1603 (BIT_7 | BIT_6 | BIT_5)) >> 5;
1604 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1605 tx_sens = ha->fw_seriallink_options[1] &
1606 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1607 rx_sens = (ha->fw_seriallink_options[1] &
1608 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
1609 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
1610 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
1611 if (rx_sens == 0x0)
1612 rx_sens = 0x3;
1613 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
1614 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
1615 ha->fw_options[11] |= BIT_5 |
1616 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1617 (tx_sens & (BIT_1 | BIT_0));
1618 }
1619
1620
1621
1622 ha->fw_options[3] |= BIT_13;
1623
1624
1625 if (ha->flags.enable_led_scheme)
1626 ha->fw_options[2] |= BIT_12;
1627
1628
1629 if (IS_QLA6312(ha))
1630 ha->fw_options[2] |= BIT_13;
1631
1632
1633 qla2x00_set_fw_options(vha, ha->fw_options);
1634}
1635
1636void
1637qla24xx_update_fw_options(scsi_qla_host_t *vha)
1638{
1639 int rval;
1640 struct qla_hw_data *ha = vha->hw;
1641
1642 if (IS_QLA82XX(ha))
1643 return;
1644
1645
1646 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
1647 return;
1648
1649 rval = qla2x00_set_serdes_params(vha,
1650 le16_to_cpu(ha->fw_seriallink_options24[1]),
1651 le16_to_cpu(ha->fw_seriallink_options24[2]),
1652 le16_to_cpu(ha->fw_seriallink_options24[3]));
1653 if (rval != QLA_SUCCESS) {
1654 ql_log(ql_log_warn, vha, 0x0104,
1655 "Unable to update Serial Link options (%x).\n", rval);
1656 }
1657}
1658
1659void
1660qla2x00_config_rings(struct scsi_qla_host *vha)
1661{
1662 struct qla_hw_data *ha = vha->hw;
1663 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1664 struct req_que *req = ha->req_q_map[0];
1665 struct rsp_que *rsp = ha->rsp_q_map[0];
1666
1667
1668 ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
1669 ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
1670 ha->init_cb->request_q_length = cpu_to_le16(req->length);
1671 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
1672 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1673 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1674 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1675 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1676
1677 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
1678 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
1679 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
1680 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
1681 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg));
1682}
1683
1684void
1685qla24xx_config_rings(struct scsi_qla_host *vha)
1686{
1687 struct qla_hw_data *ha = vha->hw;
1688 device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
1689 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
1690 struct qla_msix_entry *msix;
1691 struct init_cb_24xx *icb;
1692 uint16_t rid = 0;
1693 struct req_que *req = ha->req_q_map[0];
1694 struct rsp_que *rsp = ha->rsp_q_map[0];
1695
1696
1697 icb = (struct init_cb_24xx *)ha->init_cb;
1698 icb->request_q_outpointer = __constant_cpu_to_le16(0);
1699 icb->response_q_inpointer = __constant_cpu_to_le16(0);
1700 icb->request_q_length = cpu_to_le16(req->length);
1701 icb->response_q_length = cpu_to_le16(rsp->length);
1702 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1703 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1704 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1705 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1706
1707
1708 icb->atio_q_inpointer = __constant_cpu_to_le16(0);
1709 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
1710 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
1711 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
1712
1713 if (ha->mqenable || IS_QLA83XX(ha)) {
1714 icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
1715 icb->rid = __constant_cpu_to_le16(rid);
1716 if (ha->flags.msix_enabled) {
1717 msix = &ha->msix_entries[1];
1718 ql_dbg(ql_dbg_init, vha, 0x00fd,
1719 "Registering vector 0x%x for base que.\n",
1720 msix->entry);
1721 icb->msix = cpu_to_le16(msix->entry);
1722 }
1723
1724 if (MSB(rid))
1725 icb->firmware_options_2 |=
1726 __constant_cpu_to_le32(BIT_19);
1727
1728 if (LSB(rid))
1729 icb->firmware_options_2 |=
1730 __constant_cpu_to_le32(BIT_18);
1731
1732
1733 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
1734 (ha->flags.msix_enabled)) {
1735 icb->firmware_options_2 &=
1736 __constant_cpu_to_le32(~BIT_22);
1737 ha->flags.disable_msix_handshake = 1;
1738 ql_dbg(ql_dbg_init, vha, 0x00fe,
1739 "MSIX Handshake Disable Mode turned on.\n");
1740 } else {
1741 icb->firmware_options_2 |=
1742 __constant_cpu_to_le32(BIT_22);
1743 }
1744 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
1745
1746 WRT_REG_DWORD(®->isp25mq.req_q_in, 0);
1747 WRT_REG_DWORD(®->isp25mq.req_q_out, 0);
1748 WRT_REG_DWORD(®->isp25mq.rsp_q_in, 0);
1749 WRT_REG_DWORD(®->isp25mq.rsp_q_out, 0);
1750 } else {
1751 WRT_REG_DWORD(®->isp24.req_q_in, 0);
1752 WRT_REG_DWORD(®->isp24.req_q_out, 0);
1753 WRT_REG_DWORD(®->isp24.rsp_q_in, 0);
1754 WRT_REG_DWORD(®->isp24.rsp_q_out, 0);
1755 }
1756 qlt_24xx_config_rings(vha, reg);
1757
1758
1759 RD_REG_DWORD(&ioreg->hccr);
1760}
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771static int
1772qla2x00_init_rings(scsi_qla_host_t *vha)
1773{
1774 int rval;
1775 unsigned long flags = 0;
1776 int cnt, que;
1777 struct qla_hw_data *ha = vha->hw;
1778 struct req_que *req;
1779 struct rsp_que *rsp;
1780 struct mid_init_cb_24xx *mid_init_cb =
1781 (struct mid_init_cb_24xx *) ha->init_cb;
1782
1783 spin_lock_irqsave(&ha->hardware_lock, flags);
1784
1785
1786 for (que = 0; que < ha->max_req_queues; que++) {
1787 req = ha->req_q_map[que];
1788 if (!req)
1789 continue;
1790 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
1791 req->outstanding_cmds[cnt] = NULL;
1792
1793 req->current_outstanding_cmd = 1;
1794
1795
1796 req->ring_ptr = req->ring;
1797 req->ring_index = 0;
1798 req->cnt = req->length;
1799 }
1800
1801 for (que = 0; que < ha->max_rsp_queues; que++) {
1802 rsp = ha->rsp_q_map[que];
1803 if (!rsp)
1804 continue;
1805
1806 qla2x00_init_response_q_entries(rsp);
1807 }
1808
1809 spin_lock(&ha->vport_slock);
1810
1811 spin_unlock(&ha->vport_slock);
1812
1813 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
1814 ha->tgt.atio_ring_index = 0;
1815
1816 qlt_init_atio_q_entries(vha);
1817
1818 ha->isp_ops->config_rings(vha);
1819
1820 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1821
1822
1823 ha->isp_ops->update_fw_options(vha);
1824
1825 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
1826
1827 if (ha->flags.npiv_supported) {
1828 if (ha->operating_mode == LOOP)
1829 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
1830 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
1831 }
1832
1833 if (IS_FWI2_CAPABLE(ha)) {
1834 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
1835 mid_init_cb->init_cb.execution_throttle =
1836 cpu_to_le16(ha->fw_xcb_count);
1837 }
1838
1839 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
1840 if (rval) {
1841 ql_log(ql_log_fatal, vha, 0x00d2,
1842 "Init Firmware **** FAILED ****.\n");
1843 } else {
1844 ql_dbg(ql_dbg_init, vha, 0x00d3,
1845 "Init Firmware -- success.\n");
1846 }
1847
1848 return (rval);
1849}
1850
1851
1852
1853
1854
1855
1856
1857static int
1858qla2x00_fw_ready(scsi_qla_host_t *vha)
1859{
1860 int rval;
1861 unsigned long wtime, mtime, cs84xx_time;
1862 uint16_t min_wait;
1863 uint16_t wait_time;
1864 uint16_t state[5];
1865 struct qla_hw_data *ha = vha->hw;
1866
1867 rval = QLA_SUCCESS;
1868
1869
1870 min_wait = 20;
1871
1872
1873
1874
1875
1876 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
1877 wait_time = min_wait;
1878 }
1879
1880
1881 mtime = jiffies + (min_wait * HZ);
1882
1883
1884 wtime = jiffies + (wait_time * HZ);
1885
1886
1887 if (!vha->flags.init_done)
1888 ql_log(ql_log_info, vha, 0x801e,
1889 "Waiting for LIP to complete.\n");
1890
1891 do {
1892 rval = qla2x00_get_firmware_state(vha, state);
1893 if (rval == QLA_SUCCESS) {
1894 if (state[0] < FSTATE_LOSS_OF_SYNC) {
1895 vha->device_flags &= ~DFLG_NO_CABLE;
1896 }
1897 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
1898 ql_dbg(ql_dbg_taskm, vha, 0x801f,
1899 "fw_state=%x 84xx=%x.\n", state[0],
1900 state[2]);
1901 if ((state[2] & FSTATE_LOGGED_IN) &&
1902 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
1903 ql_dbg(ql_dbg_taskm, vha, 0x8028,
1904 "Sending verify iocb.\n");
1905
1906 cs84xx_time = jiffies;
1907 rval = qla84xx_init_chip(vha);
1908 if (rval != QLA_SUCCESS) {
1909 ql_log(ql_log_warn,
1910 vha, 0x8007,
1911 "Init chip failed.\n");
1912 break;
1913 }
1914
1915
1916 cs84xx_time = jiffies - cs84xx_time;
1917 wtime += cs84xx_time;
1918 mtime += cs84xx_time;
1919 ql_dbg(ql_dbg_taskm, vha, 0x8008,
1920 "Increasing wait time by %ld. "
1921 "New time %ld.\n", cs84xx_time,
1922 wtime);
1923 }
1924 } else if (state[0] == FSTATE_READY) {
1925 ql_dbg(ql_dbg_taskm, vha, 0x8037,
1926 "F/W Ready - OK.\n");
1927
1928 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1929 &ha->login_timeout, &ha->r_a_tov);
1930
1931 rval = QLA_SUCCESS;
1932 break;
1933 }
1934
1935 rval = QLA_FUNCTION_FAILED;
1936
1937 if (atomic_read(&vha->loop_down_timer) &&
1938 state[0] != FSTATE_READY) {
1939
1940
1941
1942 if (time_after_eq(jiffies, mtime)) {
1943 ql_log(ql_log_info, vha, 0x8038,
1944 "Cable is unplugged...\n");
1945
1946 vha->device_flags |= DFLG_NO_CABLE;
1947 break;
1948 }
1949 }
1950 } else {
1951
1952 if (time_after_eq(jiffies, mtime) ||
1953 ha->flags.isp82xx_fw_hung)
1954 break;
1955 }
1956
1957 if (time_after_eq(jiffies, wtime))
1958 break;
1959
1960
1961 msleep(500);
1962 } while (1);
1963
1964 ql_dbg(ql_dbg_taskm, vha, 0x803a,
1965 "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
1966 state[1], state[2], state[3], state[4], jiffies);
1967
1968 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
1969 ql_log(ql_log_warn, vha, 0x803b,
1970 "Firmware ready **** FAILED ****.\n");
1971 }
1972
1973 return (rval);
1974}
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989static int
1990qla2x00_configure_hba(scsi_qla_host_t *vha)
1991{
1992 int rval;
1993 uint16_t loop_id;
1994 uint16_t topo;
1995 uint16_t sw_cap;
1996 uint8_t al_pa;
1997 uint8_t area;
1998 uint8_t domain;
1999 char connect_type[22];
2000 struct qla_hw_data *ha = vha->hw;
2001
2002
2003 rval = qla2x00_get_adapter_id(vha,
2004 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
2005 if (rval != QLA_SUCCESS) {
2006 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
2007 IS_CNA_CAPABLE(ha) ||
2008 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
2009 ql_dbg(ql_dbg_disc, vha, 0x2008,
2010 "Loop is in a transition state.\n");
2011 } else {
2012 ql_log(ql_log_warn, vha, 0x2009,
2013 "Unable to get host loop ID.\n");
2014 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2015 }
2016 return (rval);
2017 }
2018
2019 if (topo == 4) {
2020 ql_log(ql_log_info, vha, 0x200a,
2021 "Cannot get topology - retrying.\n");
2022 return (QLA_FUNCTION_FAILED);
2023 }
2024
2025 vha->loop_id = loop_id;
2026
2027
2028 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
2029 ha->operating_mode = LOOP;
2030 ha->switch_cap = 0;
2031
2032 switch (topo) {
2033 case 0:
2034 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
2035 ha->current_topology = ISP_CFG_NL;
2036 strcpy(connect_type, "(Loop)");
2037 break;
2038
2039 case 1:
2040 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2041 ha->switch_cap = sw_cap;
2042 ha->current_topology = ISP_CFG_FL;
2043 strcpy(connect_type, "(FL_Port)");
2044 break;
2045
2046 case 2:
2047 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
2048 ha->operating_mode = P2P;
2049 ha->current_topology = ISP_CFG_N;
2050 strcpy(connect_type, "(N_Port-to-N_Port)");
2051 break;
2052
2053 case 3:
2054 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2055 ha->switch_cap = sw_cap;
2056 ha->operating_mode = P2P;
2057 ha->current_topology = ISP_CFG_F;
2058 strcpy(connect_type, "(F_Port)");
2059 break;
2060
2061 default:
2062 ql_dbg(ql_dbg_disc, vha, 0x200f,
2063 "HBA in unknown topology %x, using NL.\n", topo);
2064 ha->current_topology = ISP_CFG_NL;
2065 strcpy(connect_type, "(Loop)");
2066 break;
2067 }
2068
2069
2070
2071 vha->d_id.b.domain = domain;
2072 vha->d_id.b.area = area;
2073 vha->d_id.b.al_pa = al_pa;
2074
2075 spin_lock(&ha->vport_slock);
2076 qlt_update_vp_map(vha, SET_AL_PA);
2077 spin_unlock(&ha->vport_slock);
2078
2079 if (!vha->flags.init_done)
2080 ql_log(ql_log_info, vha, 0x2010,
2081 "Topology - %s, Host Loop address 0x%x.\n",
2082 connect_type, vha->loop_id);
2083
2084 if (rval) {
2085 ql_log(ql_log_warn, vha, 0x2011,
2086 "%s FAILED\n", __func__);
2087 } else {
2088 ql_dbg(ql_dbg_disc, vha, 0x2012,
2089 "%s success\n", __func__);
2090 }
2091
2092 return(rval);
2093}
2094
2095inline void
2096qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
2097 char *def)
2098{
2099 char *st, *en;
2100 uint16_t index;
2101 struct qla_hw_data *ha = vha->hw;
2102 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
2103 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
2104
2105 if (memcmp(model, BINZERO, len) != 0) {
2106 strncpy(ha->model_number, model, len);
2107 st = en = ha->model_number;
2108 en += len - 1;
2109 while (en > st) {
2110 if (*en != 0x20 && *en != 0x00)
2111 break;
2112 *en-- = '\0';
2113 }
2114
2115 index = (ha->pdev->subsystem_device & 0xff);
2116 if (use_tbl &&
2117 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2118 index < QLA_MODEL_NAMES)
2119 strncpy(ha->model_desc,
2120 qla2x00_model_name[index * 2 + 1],
2121 sizeof(ha->model_desc) - 1);
2122 } else {
2123 index = (ha->pdev->subsystem_device & 0xff);
2124 if (use_tbl &&
2125 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
2126 index < QLA_MODEL_NAMES) {
2127 strcpy(ha->model_number,
2128 qla2x00_model_name[index * 2]);
2129 strncpy(ha->model_desc,
2130 qla2x00_model_name[index * 2 + 1],
2131 sizeof(ha->model_desc) - 1);
2132 } else {
2133 strcpy(ha->model_number, def);
2134 }
2135 }
2136 if (IS_FWI2_CAPABLE(ha))
2137 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
2138 sizeof(ha->model_desc));
2139}
2140
2141
2142
2143
2144static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
2145{
2146#ifdef CONFIG_SPARC
2147 struct qla_hw_data *ha = vha->hw;
2148 struct pci_dev *pdev = ha->pdev;
2149 struct device_node *dp = pci_device_to_OF_node(pdev);
2150 const u8 *val;
2151 int len;
2152
2153 val = of_get_property(dp, "port-wwn", &len);
2154 if (val && len >= WWN_SIZE)
2155 memcpy(nv->port_name, val, WWN_SIZE);
2156
2157 val = of_get_property(dp, "node-wwn", &len);
2158 if (val && len >= WWN_SIZE)
2159 memcpy(nv->node_name, val, WWN_SIZE);
2160#endif
2161}
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176int
2177qla2x00_nvram_config(scsi_qla_host_t *vha)
2178{
2179 int rval;
2180 uint8_t chksum = 0;
2181 uint16_t cnt;
2182 uint8_t *dptr1, *dptr2;
2183 struct qla_hw_data *ha = vha->hw;
2184 init_cb_t *icb = ha->init_cb;
2185 nvram_t *nv = ha->nvram;
2186 uint8_t *ptr = ha->nvram;
2187 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2188
2189 rval = QLA_SUCCESS;
2190
2191
2192 ha->nvram_size = sizeof(nvram_t);
2193 ha->nvram_base = 0;
2194 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
2195 if ((RD_REG_WORD(®->ctrl_status) >> 14) == 1)
2196 ha->nvram_base = 0x80;
2197
2198
2199 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
2200 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
2201 chksum += *ptr++;
2202
2203 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
2204 "Contents of NVRAM.\n");
2205 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
2206 (uint8_t *)nv, ha->nvram_size);
2207
2208
2209 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
2210 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
2211
2212 ql_log(ql_log_warn, vha, 0x0064,
2213 "Inconsistent NVRAM "
2214 "detected: checksum=0x%x id=%c version=0x%x.\n",
2215 chksum, nv->id[0], nv->nvram_version);
2216 ql_log(ql_log_warn, vha, 0x0065,
2217 "Falling back to "
2218 "functioning (yet invalid -- WWPN) defaults.\n");
2219
2220
2221
2222
2223 memset(nv, 0, ha->nvram_size);
2224 nv->parameter_block_version = ICB_VERSION;
2225
2226 if (IS_QLA23XX(ha)) {
2227 nv->firmware_options[0] = BIT_2 | BIT_1;
2228 nv->firmware_options[1] = BIT_7 | BIT_5;
2229 nv->add_firmware_options[0] = BIT_5;
2230 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2231 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2232 nv->special_options[1] = BIT_7;
2233 } else if (IS_QLA2200(ha)) {
2234 nv->firmware_options[0] = BIT_2 | BIT_1;
2235 nv->firmware_options[1] = BIT_7 | BIT_5;
2236 nv->add_firmware_options[0] = BIT_5;
2237 nv->add_firmware_options[1] = BIT_5 | BIT_4;
2238 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2239 } else if (IS_QLA2100(ha)) {
2240 nv->firmware_options[0] = BIT_3 | BIT_1;
2241 nv->firmware_options[1] = BIT_5;
2242 nv->frame_payload_size = __constant_cpu_to_le16(1024);
2243 }
2244
2245 nv->max_iocb_allocation = __constant_cpu_to_le16(256);
2246 nv->execution_throttle = __constant_cpu_to_le16(16);
2247 nv->retry_count = 8;
2248 nv->retry_delay = 1;
2249
2250 nv->port_name[0] = 33;
2251 nv->port_name[3] = 224;
2252 nv->port_name[4] = 139;
2253
2254 qla2xxx_nvram_wwn_from_ofw(vha, nv);
2255
2256 nv->login_timeout = 4;
2257
2258
2259
2260
2261 nv->host_p[1] = BIT_2;
2262 nv->reset_delay = 5;
2263 nv->port_down_retry_count = 8;
2264 nv->max_luns_per_target = __constant_cpu_to_le16(8);
2265 nv->link_down_timeout = 60;
2266
2267 rval = 1;
2268 }
2269
2270#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
2271
2272
2273
2274
2275
2276
2277 if (ia64_platform_is("sn2")) {
2278 nv->frame_payload_size = __constant_cpu_to_le16(2048);
2279 if (IS_QLA23XX(ha))
2280 nv->special_options[1] = BIT_7;
2281 }
2282#endif
2283
2284
2285 memset(icb, 0, ha->init_cb_size);
2286
2287
2288
2289
2290 nv->firmware_options[0] |= (BIT_6 | BIT_1);
2291 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
2292 nv->firmware_options[1] |= (BIT_5 | BIT_0);
2293 nv->firmware_options[1] &= ~BIT_4;
2294
2295 if (IS_QLA23XX(ha)) {
2296 nv->firmware_options[0] |= BIT_2;
2297 nv->firmware_options[0] &= ~BIT_3;
2298 nv->special_options[0] &= ~BIT_6;
2299 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
2300
2301 if (IS_QLA2300(ha)) {
2302 if (ha->fb_rev == FPM_2310) {
2303 strcpy(ha->model_number, "QLA2310");
2304 } else {
2305 strcpy(ha->model_number, "QLA2300");
2306 }
2307 } else {
2308 qla2x00_set_model_info(vha, nv->model_number,
2309 sizeof(nv->model_number), "QLA23xx");
2310 }
2311 } else if (IS_QLA2200(ha)) {
2312 nv->firmware_options[0] |= BIT_2;
2313
2314
2315
2316
2317 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
2318 (BIT_5 | BIT_4)) {
2319
2320 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
2321 nv->add_firmware_options[0] |= BIT_5;
2322 }
2323 strcpy(ha->model_number, "QLA22xx");
2324 } else {
2325 strcpy(ha->model_number, "QLA2100");
2326 }
2327
2328
2329
2330
2331 dptr1 = (uint8_t *)icb;
2332 dptr2 = (uint8_t *)&nv->parameter_block_version;
2333 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
2334 while (cnt--)
2335 *dptr1++ = *dptr2++;
2336
2337
2338 dptr1 = (uint8_t *)icb->add_firmware_options;
2339 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
2340 while (cnt--)
2341 *dptr1++ = *dptr2++;
2342
2343
2344 if (nv->host_p[1] & BIT_7) {
2345 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
2346 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
2347 }
2348
2349
2350 if ((icb->firmware_options[1] & BIT_6) == 0) {
2351
2352
2353
2354
2355 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
2356 icb->node_name[0] &= 0xF0;
2357 }
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367 if (nv->host_p[0] & BIT_7)
2368 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
2369 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
2370
2371 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
2372 ha->flags.disable_risc_code_load = 0;
2373 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
2374 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
2375 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
2376 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
2377 ha->flags.disable_serdes = 0;
2378
2379 ha->operating_mode =
2380 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
2381
2382 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
2383 sizeof(ha->fw_seriallink_options));
2384
2385
2386 ha->serial0 = icb->port_name[5];
2387 ha->serial1 = icb->port_name[6];
2388 ha->serial2 = icb->port_name[7];
2389 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
2390 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
2391
2392 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
2393
2394 ha->retry_count = nv->retry_count;
2395
2396
2397 if (nv->login_timeout != ql2xlogintimeout)
2398 nv->login_timeout = ql2xlogintimeout;
2399 if (nv->login_timeout < 4)
2400 nv->login_timeout = 4;
2401 ha->login_timeout = nv->login_timeout;
2402 icb->login_timeout = nv->login_timeout;
2403
2404
2405 ha->r_a_tov = 100;
2406
2407 ha->loop_reset_delay = nv->reset_delay;
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419 if (nv->link_down_timeout == 0) {
2420 ha->loop_down_abort_time =
2421 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
2422 } else {
2423 ha->link_down_timeout = nv->link_down_timeout;
2424 ha->loop_down_abort_time =
2425 (LOOP_DOWN_TIME - ha->link_down_timeout);
2426 }
2427
2428
2429
2430
2431 ha->port_down_retry_count = nv->port_down_retry_count;
2432 if (qlport_down_retry)
2433 ha->port_down_retry_count = qlport_down_retry;
2434
2435 ha->login_retry_count = nv->retry_count;
2436 if (ha->port_down_retry_count == nv->port_down_retry_count &&
2437 ha->port_down_retry_count > 3)
2438 ha->login_retry_count = ha->port_down_retry_count;
2439 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
2440 ha->login_retry_count = ha->port_down_retry_count;
2441 if (ql2xloginretrycount)
2442 ha->login_retry_count = ql2xloginretrycount;
2443
2444 icb->lun_enables = __constant_cpu_to_le16(0);
2445 icb->command_resource_count = 0;
2446 icb->immediate_notify_resource_count = 0;
2447 icb->timeout = __constant_cpu_to_le16(0);
2448
2449 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
2450
2451 icb->firmware_options[0] &= ~BIT_3;
2452 icb->add_firmware_options[0] &=
2453 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2454 icb->add_firmware_options[0] |= BIT_2;
2455 icb->response_accumulation_timer = 3;
2456 icb->interrupt_delay_timer = 5;
2457
2458 vha->flags.process_response_queue = 1;
2459 } else {
2460
2461 if (!vha->flags.init_done) {
2462 ha->zio_mode = icb->add_firmware_options[0] &
2463 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2464 ha->zio_timer = icb->interrupt_delay_timer ?
2465 icb->interrupt_delay_timer: 2;
2466 }
2467 icb->add_firmware_options[0] &=
2468 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
2469 vha->flags.process_response_queue = 0;
2470 if (ha->zio_mode != QLA_ZIO_DISABLED) {
2471 ha->zio_mode = QLA_ZIO_MODE_6;
2472
2473 ql_log(ql_log_info, vha, 0x0068,
2474 "ZIO mode %d enabled; timer delay (%d us).\n",
2475 ha->zio_mode, ha->zio_timer * 100);
2476
2477 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
2478 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
2479 vha->flags.process_response_queue = 1;
2480 }
2481 }
2482
2483 if (rval) {
2484 ql_log(ql_log_warn, vha, 0x0069,
2485 "NVRAM configuration failed.\n");
2486 }
2487 return (rval);
2488}
2489
2490static void
2491qla2x00_rport_del(void *data)
2492{
2493 fc_port_t *fcport = data;
2494 struct fc_rport *rport;
2495 scsi_qla_host_t *vha = fcport->vha;
2496 unsigned long flags;
2497
2498 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
2499 rport = fcport->drport ? fcport->drport: fcport->rport;
2500 fcport->drport = NULL;
2501 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2502 if (rport) {
2503 fc_remote_port_delete(rport);
2504
2505
2506
2507
2508 qlt_fc_port_deleted(vha, fcport);
2509 }
2510}
2511
2512
2513
2514
2515
2516
2517
2518
2519fc_port_t *
2520qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
2521{
2522 fc_port_t *fcport;
2523
2524 fcport = kzalloc(sizeof(fc_port_t), flags);
2525 if (!fcport)
2526 return NULL;
2527
2528
2529 fcport->vha = vha;
2530 fcport->port_type = FCT_UNKNOWN;
2531 fcport->loop_id = FC_NO_LOOP_ID;
2532 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
2533 fcport->supported_classes = FC_COS_UNSPECIFIED;
2534 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
2535
2536 return fcport;
2537}
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551static int
2552qla2x00_configure_loop(scsi_qla_host_t *vha)
2553{
2554 int rval;
2555 unsigned long flags, save_flags;
2556 struct qla_hw_data *ha = vha->hw;
2557 rval = QLA_SUCCESS;
2558
2559
2560 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
2561 rval = qla2x00_configure_hba(vha);
2562 if (rval != QLA_SUCCESS) {
2563 ql_dbg(ql_dbg_disc, vha, 0x2013,
2564 "Unable to configure HBA.\n");
2565 return (rval);
2566 }
2567 }
2568
2569 save_flags = flags = vha->dpc_flags;
2570 ql_dbg(ql_dbg_disc, vha, 0x2014,
2571 "Configure loop -- dpc flags = 0x%lx.\n", flags);
2572
2573
2574
2575
2576
2577 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2578 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
2579
2580 qla2x00_get_data_rate(vha);
2581
2582
2583 if (ha->current_topology == ISP_CFG_FL &&
2584 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2585
2586 set_bit(RSCN_UPDATE, &flags);
2587
2588 } else if (ha->current_topology == ISP_CFG_F &&
2589 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
2590
2591 set_bit(RSCN_UPDATE, &flags);
2592 clear_bit(LOCAL_LOOP_UPDATE, &flags);
2593
2594 } else if (ha->current_topology == ISP_CFG_N) {
2595 clear_bit(RSCN_UPDATE, &flags);
2596
2597 } else if (!vha->flags.online ||
2598 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
2599
2600 set_bit(RSCN_UPDATE, &flags);
2601 set_bit(LOCAL_LOOP_UPDATE, &flags);
2602 }
2603
2604 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
2605 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2606 ql_dbg(ql_dbg_disc, vha, 0x2015,
2607 "Loop resync needed, failing.\n");
2608 rval = QLA_FUNCTION_FAILED;
2609 } else
2610 rval = qla2x00_configure_local_loop(vha);
2611 }
2612
2613 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
2614 if (LOOP_TRANSITION(vha)) {
2615 ql_dbg(ql_dbg_disc, vha, 0x201e,
2616 "Needs RSCN update and loop transition.\n");
2617 rval = QLA_FUNCTION_FAILED;
2618 }
2619 else
2620 rval = qla2x00_configure_fabric(vha);
2621 }
2622
2623 if (rval == QLA_SUCCESS) {
2624 if (atomic_read(&vha->loop_down_timer) ||
2625 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2626 rval = QLA_FUNCTION_FAILED;
2627 } else {
2628 atomic_set(&vha->loop_state, LOOP_READY);
2629 ql_dbg(ql_dbg_disc, vha, 0x2069,
2630 "LOOP READY.\n");
2631 }
2632 }
2633
2634 if (rval) {
2635 ql_dbg(ql_dbg_disc, vha, 0x206a,
2636 "%s *** FAILED ***.\n", __func__);
2637 } else {
2638 ql_dbg(ql_dbg_disc, vha, 0x206b,
2639 "%s: exiting normally.\n", __func__);
2640 }
2641
2642
2643 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
2644 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
2645 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2646 if (test_bit(RSCN_UPDATE, &save_flags)) {
2647 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2648 }
2649 }
2650
2651 return (rval);
2652}
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666static int
2667qla2x00_configure_local_loop(scsi_qla_host_t *vha)
2668{
2669 int rval, rval2;
2670 int found_devs;
2671 int found;
2672 fc_port_t *fcport, *new_fcport;
2673
2674 uint16_t index;
2675 uint16_t entries;
2676 char *id_iter;
2677 uint16_t loop_id;
2678 uint8_t domain, area, al_pa;
2679 struct qla_hw_data *ha = vha->hw;
2680
2681 found_devs = 0;
2682 new_fcport = NULL;
2683 entries = MAX_FIBRE_DEVICES_LOOP;
2684
2685 ql_dbg(ql_dbg_disc, vha, 0x2016,
2686 "Getting FCAL position map.\n");
2687 if (ql2xextended_error_logging & ql_dbg_disc)
2688 qla2x00_get_fcal_position_map(vha, NULL);
2689
2690
2691 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
2692 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
2693 &entries);
2694 if (rval != QLA_SUCCESS)
2695 goto cleanup_allocation;
2696
2697 ql_dbg(ql_dbg_disc, vha, 0x2017,
2698 "Entries in ID list (%d).\n", entries);
2699 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
2700 (uint8_t *)ha->gid_list,
2701 entries * sizeof(struct gid_list_info));
2702
2703
2704 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
2705 if (new_fcport == NULL) {
2706 ql_log(ql_log_warn, vha, 0x2018,
2707 "Memory allocation failed for fcport.\n");
2708 rval = QLA_MEMORY_ALLOC_FAILED;
2709 goto cleanup_allocation;
2710 }
2711 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2712
2713
2714
2715
2716 list_for_each_entry(fcport, &vha->vp_fcports, list) {
2717 if (atomic_read(&fcport->state) == FCS_ONLINE &&
2718 fcport->port_type != FCT_BROADCAST &&
2719 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
2720
2721 ql_dbg(ql_dbg_disc, vha, 0x2019,
2722 "Marking port lost loop_id=0x%04x.\n",
2723 fcport->loop_id);
2724
2725 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
2726 }
2727 }
2728
2729
2730 id_iter = (char *)ha->gid_list;
2731 for (index = 0; index < entries; index++) {
2732 domain = ((struct gid_list_info *)id_iter)->domain;
2733 area = ((struct gid_list_info *)id_iter)->area;
2734 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
2735 if (IS_QLA2100(ha) || IS_QLA2200(ha))
2736 loop_id = (uint16_t)
2737 ((struct gid_list_info *)id_iter)->loop_id_2100;
2738 else
2739 loop_id = le16_to_cpu(
2740 ((struct gid_list_info *)id_iter)->loop_id);
2741 id_iter += ha->gid_list_info_size;
2742
2743
2744 if ((domain & 0xf0) == 0xf0)
2745 continue;
2746
2747
2748 if (area && domain &&
2749 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
2750 continue;
2751
2752
2753 if (loop_id > LAST_LOCAL_LOOP_ID)
2754 continue;
2755
2756
2757 new_fcport->d_id.b.domain = domain;
2758 new_fcport->d_id.b.area = area;
2759 new_fcport->d_id.b.al_pa = al_pa;
2760 new_fcport->loop_id = loop_id;
2761 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
2762 if (rval2 != QLA_SUCCESS) {
2763 ql_dbg(ql_dbg_disc, vha, 0x201a,
2764 "Failed to retrieve fcport information "
2765 "-- get_port_database=%x, loop_id=0x%04x.\n",
2766 rval2, new_fcport->loop_id);
2767 ql_dbg(ql_dbg_disc, vha, 0x201b,
2768 "Scheduling resync.\n");
2769 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2770 continue;
2771 }
2772
2773
2774 found = 0;
2775 fcport = NULL;
2776 list_for_each_entry(fcport, &vha->vp_fcports, list) {
2777 if (memcmp(new_fcport->port_name, fcport->port_name,
2778 WWN_SIZE))
2779 continue;
2780
2781 fcport->flags &= ~FCF_FABRIC_DEVICE;
2782 fcport->loop_id = new_fcport->loop_id;
2783 fcport->port_type = new_fcport->port_type;
2784 fcport->d_id.b24 = new_fcport->d_id.b24;
2785 memcpy(fcport->node_name, new_fcport->node_name,
2786 WWN_SIZE);
2787
2788 found++;
2789 break;
2790 }
2791
2792 if (!found) {
2793
2794 list_add_tail(&new_fcport->list, &vha->vp_fcports);
2795
2796
2797 fcport = new_fcport;
2798 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
2799 if (new_fcport == NULL) {
2800 ql_log(ql_log_warn, vha, 0x201c,
2801 "Failed to allocate memory for fcport.\n");
2802 rval = QLA_MEMORY_ALLOC_FAILED;
2803 goto cleanup_allocation;
2804 }
2805 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
2806 }
2807
2808
2809 fcport->fp_speed = ha->link_data_rate;
2810
2811 qla2x00_update_fcport(vha, fcport);
2812
2813 found_devs++;
2814 }
2815
2816cleanup_allocation:
2817 kfree(new_fcport);
2818
2819 if (rval != QLA_SUCCESS) {
2820 ql_dbg(ql_dbg_disc, vha, 0x201d,
2821 "Configure local loop error exit: rval=%x.\n", rval);
2822 }
2823
2824 return (rval);
2825}
2826
2827static void
2828qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
2829{
2830 char *link_speed;
2831 int rval;
2832 uint16_t mb[4];
2833 struct qla_hw_data *ha = vha->hw;
2834
2835 if (!IS_IIDMA_CAPABLE(ha))
2836 return;
2837
2838 if (atomic_read(&fcport->state) != FCS_ONLINE)
2839 return;
2840
2841 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
2842 fcport->fp_speed > ha->link_data_rate)
2843 return;
2844
2845 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
2846 mb);
2847 if (rval != QLA_SUCCESS) {
2848 ql_dbg(ql_dbg_disc, vha, 0x2004,
2849 "Unable to adjust iIDMA "
2850 "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
2851 "%04x.\n", fcport->port_name[0], fcport->port_name[1],
2852 fcport->port_name[2], fcport->port_name[3],
2853 fcport->port_name[4], fcport->port_name[5],
2854 fcport->port_name[6], fcport->port_name[7], rval,
2855 fcport->fp_speed, mb[0], mb[1]);
2856 } else {
2857 link_speed = qla2x00_get_link_speed_str(ha);
2858 ql_dbg(ql_dbg_disc, vha, 0x2005,
2859 "iIDMA adjusted to %s GB/s "
2860 "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
2861 fcport->port_name[0], fcport->port_name[1],
2862 fcport->port_name[2], fcport->port_name[3],
2863 fcport->port_name[4], fcport->port_name[5],
2864 fcport->port_name[6], fcport->port_name[7]);
2865 }
2866}
2867
2868static void
2869qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
2870{
2871 struct fc_rport_identifiers rport_ids;
2872 struct fc_rport *rport;
2873 unsigned long flags;
2874
2875 qla2x00_rport_del(fcport);
2876
2877 rport_ids.node_name = wwn_to_u64(fcport->node_name);
2878 rport_ids.port_name = wwn_to_u64(fcport->port_name);
2879 rport_ids.port_id = fcport->d_id.b.domain << 16 |
2880 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
2881 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
2882 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
2883 if (!rport) {
2884 ql_log(ql_log_warn, vha, 0x2006,
2885 "Unable to allocate fc remote port.\n");
2886 return;
2887 }
2888
2889
2890
2891
2892 qlt_fc_port_added(vha, fcport);
2893
2894 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
2895 *((fc_port_t **)rport->dd_data) = fcport;
2896 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
2897
2898 rport->supported_classes = fcport->supported_classes;
2899
2900 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
2901 if (fcport->port_type == FCT_INITIATOR)
2902 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
2903 if (fcport->port_type == FCT_TARGET)
2904 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
2905 fc_remote_port_rolechg(rport, rport_ids.roles);
2906}
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923void
2924qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
2925{
2926 fcport->vha = vha;
2927 fcport->login_retry = 0;
2928 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
2929
2930 qla2x00_iidma_fcport(vha, fcport);
2931 qla24xx_update_fcport_fcp_prio(vha, fcport);
2932 qla2x00_reg_remote_port(vha, fcport);
2933 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
2934}
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947static int
2948qla2x00_configure_fabric(scsi_qla_host_t *vha)
2949{
2950 int rval;
2951 fc_port_t *fcport;
2952 uint16_t next_loopid;
2953 uint16_t mb[MAILBOX_REGISTER_COUNT];
2954 uint16_t loop_id;
2955 LIST_HEAD(new_fcports);
2956 struct qla_hw_data *ha = vha->hw;
2957 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2958
2959
2960 if (IS_FWI2_CAPABLE(ha))
2961 loop_id = NPH_F_PORT;
2962 else
2963 loop_id = SNS_FL_PORT;
2964 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
2965 if (rval != QLA_SUCCESS) {
2966 ql_dbg(ql_dbg_disc, vha, 0x201f,
2967 "MBX_GET_PORT_NAME failed, No FL Port.\n");
2968
2969 vha->device_flags &= ~SWITCH_FOUND;
2970 return (QLA_SUCCESS);
2971 }
2972 vha->device_flags |= SWITCH_FOUND;
2973
2974 do {
2975
2976 if (ql2xfdmienable &&
2977 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
2978 qla2x00_fdmi_register(vha);
2979
2980
2981 if (IS_FWI2_CAPABLE(ha))
2982 loop_id = NPH_SNS;
2983 else
2984 loop_id = SIMPLE_NAME_SERVER;
2985 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
2986 0xfc, mb, BIT_1|BIT_0);
2987 if (rval != QLA_SUCCESS) {
2988 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2989 break;
2990 }
2991 if (mb[0] != MBS_COMMAND_COMPLETE) {
2992 ql_dbg(ql_dbg_disc, vha, 0x2042,
2993 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
2994 "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
2995 mb[2], mb[6], mb[7]);
2996 return (QLA_SUCCESS);
2997 }
2998
2999 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
3000 if (qla2x00_rft_id(vha)) {
3001
3002 ql_dbg(ql_dbg_disc, vha, 0x2045,
3003 "Register FC-4 TYPE failed.\n");
3004 }
3005 if (qla2x00_rff_id(vha)) {
3006
3007 ql_dbg(ql_dbg_disc, vha, 0x2049,
3008 "Register FC-4 Features failed.\n");
3009 }
3010 if (qla2x00_rnn_id(vha)) {
3011
3012 ql_dbg(ql_dbg_disc, vha, 0x204f,
3013 "Register Node Name failed.\n");
3014 } else if (qla2x00_rsnn_nn(vha)) {
3015
3016 ql_dbg(ql_dbg_disc, vha, 0x2053,
3017 "Register Symobilic Node Name failed.\n");
3018 }
3019 }
3020
3021 rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
3022 if (rval != QLA_SUCCESS)
3023 break;
3024
3025
3026 list_splice_tail_init(&new_fcports, &vha->vp_fcports);
3027
3028
3029 next_loopid = ha->min_external_loopid;
3030
3031 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3032 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3033 break;
3034
3035 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
3036 continue;
3037
3038
3039 if (fcport->scan_state != QLA_FCPORT_SCAN_FOUND &&
3040 atomic_read(&fcport->state) == FCS_ONLINE) {
3041 qla2x00_mark_device_lost(vha, fcport,
3042 ql2xplogiabsentdevice, 0);
3043 if (fcport->loop_id != FC_NO_LOOP_ID &&
3044 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3045 fcport->port_type != FCT_INITIATOR &&
3046 fcport->port_type != FCT_BROADCAST) {
3047 ha->isp_ops->fabric_logout(vha,
3048 fcport->loop_id,
3049 fcport->d_id.b.domain,
3050 fcport->d_id.b.area,
3051 fcport->d_id.b.al_pa);
3052 }
3053 continue;
3054 }
3055 fcport->scan_state = QLA_FCPORT_SCAN_NONE;
3056
3057
3058 if ((fcport->flags & FCF_LOGIN_NEEDED) != 0 &&
3059 atomic_read(&vha->loop_down_timer) == 0) {
3060 if (fcport->loop_id == FC_NO_LOOP_ID) {
3061 fcport->loop_id = next_loopid;
3062 rval = qla2x00_find_new_loop_id(
3063 base_vha, fcport);
3064 if (rval != QLA_SUCCESS) {
3065
3066 continue;
3067 }
3068 }
3069 }
3070
3071
3072 qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
3073 }
3074 } while (0);
3075
3076 if (rval) {
3077 ql_dbg(ql_dbg_disc, vha, 0x2068,
3078 "Configure fabric error exit rval=%d.\n", rval);
3079 }
3080
3081 return (rval);
3082}
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097static int
3098qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
3099 struct list_head *new_fcports)
3100{
3101 int rval;
3102 uint16_t loop_id;
3103 fc_port_t *fcport, *new_fcport, *fcptemp;
3104 int found;
3105
3106 sw_info_t *swl;
3107 int swl_idx;
3108 int first_dev, last_dev;
3109 port_id_t wrap = {}, nxt_d_id;
3110 struct qla_hw_data *ha = vha->hw;
3111 struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
3112 struct scsi_qla_host *tvp;
3113
3114 rval = QLA_SUCCESS;
3115
3116
3117 if (!ha->swl)
3118 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
3119 GFP_KERNEL);
3120 swl = ha->swl;
3121 if (!swl) {
3122
3123 ql_dbg(ql_dbg_disc, vha, 0x2054,
3124 "GID_PT allocations failed, fallback on GA_NXT.\n");
3125 } else {
3126 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
3127 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
3128 swl = NULL;
3129 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
3130 swl = NULL;
3131 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
3132 swl = NULL;
3133 } else if (ql2xiidmaenable &&
3134 qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
3135 qla2x00_gpsc(vha, swl);
3136 }
3137
3138
3139 if (swl)
3140 qla2x00_gff_id(vha, swl);
3141 }
3142 swl_idx = 0;
3143
3144
3145 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3146 if (new_fcport == NULL) {
3147 ql_log(ql_log_warn, vha, 0x205e,
3148 "Failed to allocate memory for fcport.\n");
3149 return (QLA_MEMORY_ALLOC_FAILED);
3150 }
3151 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3152
3153 first_dev = 1;
3154 last_dev = 0;
3155
3156
3157 loop_id = ha->min_external_loopid;
3158 for (; loop_id <= ha->max_loop_id; loop_id++) {
3159 if (qla2x00_is_reserved_id(vha, loop_id))
3160 continue;
3161
3162 if (ha->current_topology == ISP_CFG_FL &&
3163 (atomic_read(&vha->loop_down_timer) ||
3164 LOOP_TRANSITION(vha))) {
3165 atomic_set(&vha->loop_down_timer, 0);
3166 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3167 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
3168 break;
3169 }
3170
3171 if (swl != NULL) {
3172 if (last_dev) {
3173 wrap.b24 = new_fcport->d_id.b24;
3174 } else {
3175 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
3176 memcpy(new_fcport->node_name,
3177 swl[swl_idx].node_name, WWN_SIZE);
3178 memcpy(new_fcport->port_name,
3179 swl[swl_idx].port_name, WWN_SIZE);
3180 memcpy(new_fcport->fabric_port_name,
3181 swl[swl_idx].fabric_port_name, WWN_SIZE);
3182 new_fcport->fp_speed = swl[swl_idx].fp_speed;
3183 new_fcport->fc4_type = swl[swl_idx].fc4_type;
3184
3185 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
3186 last_dev = 1;
3187 }
3188 swl_idx++;
3189 }
3190 } else {
3191
3192 rval = qla2x00_ga_nxt(vha, new_fcport);
3193 if (rval != QLA_SUCCESS) {
3194 ql_log(ql_log_warn, vha, 0x2064,
3195 "SNS scan failed -- assuming "
3196 "zero-entry result.\n");
3197 list_for_each_entry_safe(fcport, fcptemp,
3198 new_fcports, list) {
3199 list_del(&fcport->list);
3200 kfree(fcport);
3201 }
3202 rval = QLA_SUCCESS;
3203 break;
3204 }
3205 }
3206
3207
3208 if (first_dev) {
3209 wrap.b24 = new_fcport->d_id.b24;
3210 first_dev = 0;
3211 } else if (new_fcport->d_id.b24 == wrap.b24) {
3212 ql_dbg(ql_dbg_disc, vha, 0x2065,
3213 "Device wrap (%02x%02x%02x).\n",
3214 new_fcport->d_id.b.domain,
3215 new_fcport->d_id.b.area,
3216 new_fcport->d_id.b.al_pa);
3217 break;
3218 }
3219
3220
3221 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
3222 continue;
3223
3224
3225 found = 0;
3226 if (ha->num_vhosts) {
3227 unsigned long flags;
3228
3229 spin_lock_irqsave(&ha->vport_slock, flags);
3230 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
3231 if (new_fcport->d_id.b24 == vp->d_id.b24) {
3232 found = 1;
3233 break;
3234 }
3235 }
3236 spin_unlock_irqrestore(&ha->vport_slock, flags);
3237
3238 if (found)
3239 continue;
3240 }
3241
3242
3243 if (((new_fcport->d_id.b24 & 0xffff00) ==
3244 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
3245 ISP_CFG_FL)
3246 continue;
3247
3248
3249 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
3250 continue;
3251
3252
3253 if (ql2xgffidenable &&
3254 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
3255 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
3256 continue;
3257
3258
3259 found = 0;
3260 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3261 if (memcmp(new_fcport->port_name, fcport->port_name,
3262 WWN_SIZE))
3263 continue;
3264
3265 fcport->scan_state = QLA_FCPORT_SCAN_FOUND;
3266
3267 found++;
3268
3269
3270 memcpy(fcport->fabric_port_name,
3271 new_fcport->fabric_port_name, WWN_SIZE);
3272 fcport->fp_speed = new_fcport->fp_speed;
3273
3274
3275
3276
3277
3278 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
3279 atomic_read(&fcport->state) == FCS_ONLINE) {
3280 break;
3281 }
3282
3283
3284
3285
3286 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
3287 fcport->d_id.b24 = new_fcport->d_id.b24;
3288 fcport->loop_id = FC_NO_LOOP_ID;
3289 fcport->flags |= (FCF_FABRIC_DEVICE |
3290 FCF_LOGIN_NEEDED);
3291 break;
3292 }
3293
3294
3295
3296
3297
3298
3299 fcport->d_id.b24 = new_fcport->d_id.b24;
3300 fcport->flags |= FCF_LOGIN_NEEDED;
3301 if (fcport->loop_id != FC_NO_LOOP_ID &&
3302 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
3303 (fcport->flags & FCF_ASYNC_SENT) == 0 &&
3304 fcport->port_type != FCT_INITIATOR &&
3305 fcport->port_type != FCT_BROADCAST) {
3306 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3307 fcport->d_id.b.domain, fcport->d_id.b.area,
3308 fcport->d_id.b.al_pa);
3309 fcport->loop_id = FC_NO_LOOP_ID;
3310 }
3311
3312 break;
3313 }
3314
3315 if (found)
3316 continue;
3317
3318 list_add_tail(&new_fcport->list, new_fcports);
3319
3320
3321 nxt_d_id.b24 = new_fcport->d_id.b24;
3322 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
3323 if (new_fcport == NULL) {
3324 ql_log(ql_log_warn, vha, 0x2066,
3325 "Memory allocation failed for fcport.\n");
3326 return (QLA_MEMORY_ALLOC_FAILED);
3327 }
3328 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
3329 new_fcport->d_id.b24 = nxt_d_id.b24;
3330 }
3331
3332 kfree(new_fcport);
3333
3334 return (rval);
3335}
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351int
3352qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
3353{
3354 int rval;
3355 int found;
3356 fc_port_t *fcport;
3357 uint16_t first_loop_id;
3358 struct qla_hw_data *ha = vha->hw;
3359 struct scsi_qla_host *vp;
3360 struct scsi_qla_host *tvp;
3361 unsigned long flags = 0;
3362
3363 rval = QLA_SUCCESS;
3364
3365
3366 first_loop_id = dev->loop_id;
3367
3368 for (;;) {
3369
3370 if (dev->loop_id == vha->loop_id)
3371 dev->loop_id++;
3372
3373
3374 while (qla2x00_is_reserved_id(vha, dev->loop_id))
3375 dev->loop_id++;
3376
3377
3378 if (dev->loop_id > ha->max_loop_id) {
3379
3380 dev->loop_id = ha->min_external_loopid;
3381 }
3382
3383
3384 found = 0;
3385 fcport = NULL;
3386
3387 spin_lock_irqsave(&ha->vport_slock, flags);
3388 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
3389 list_for_each_entry(fcport, &vp->vp_fcports, list) {
3390 if (fcport->loop_id == dev->loop_id &&
3391 fcport != dev) {
3392
3393 found++;
3394 break;
3395 }
3396 }
3397 if (found)
3398 break;
3399 }
3400 spin_unlock_irqrestore(&ha->vport_slock, flags);
3401
3402
3403 if (!found) {
3404 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
3405 "Assigning new loopid=%x, portid=%x.\n",
3406 dev->loop_id, dev->d_id.b24);
3407 break;
3408 }
3409
3410
3411 dev->loop_id++;
3412
3413
3414 if (dev->loop_id == first_loop_id) {
3415 dev->loop_id = FC_NO_LOOP_ID;
3416 rval = QLA_FUNCTION_FAILED;
3417 break;
3418 }
3419 }
3420
3421 return (rval);
3422}
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440static int
3441qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3442 uint16_t *next_loopid)
3443{
3444 int rval;
3445 int retry;
3446 uint8_t opts;
3447 struct qla_hw_data *ha = vha->hw;
3448
3449 rval = QLA_SUCCESS;
3450 retry = 0;
3451
3452 if (IS_ALOGIO_CAPABLE(ha)) {
3453 if (fcport->flags & FCF_ASYNC_SENT)
3454 return rval;
3455 fcport->flags |= FCF_ASYNC_SENT;
3456 rval = qla2x00_post_async_login_work(vha, fcport, NULL);
3457 if (!rval)
3458 return rval;
3459 }
3460
3461 fcport->flags &= ~FCF_ASYNC_SENT;
3462 rval = qla2x00_fabric_login(vha, fcport, next_loopid);
3463 if (rval == QLA_SUCCESS) {
3464
3465 opts = 0;
3466 if (fcport->flags & FCF_FCP2_DEVICE)
3467 opts |= BIT_1;
3468 rval = qla2x00_get_port_database(vha, fcport, opts);
3469 if (rval != QLA_SUCCESS) {
3470 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3471 fcport->d_id.b.domain, fcport->d_id.b.area,
3472 fcport->d_id.b.al_pa);
3473 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3474 } else {
3475 qla2x00_update_fcport(vha, fcport);
3476 }
3477 } else {
3478
3479 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3480 }
3481
3482 return (rval);
3483}
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499int
3500qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
3501 uint16_t *next_loopid)
3502{
3503 int rval;
3504 int retry;
3505 uint16_t tmp_loopid;
3506 uint16_t mb[MAILBOX_REGISTER_COUNT];
3507 struct qla_hw_data *ha = vha->hw;
3508
3509 retry = 0;
3510 tmp_loopid = 0;
3511
3512 for (;;) {
3513 ql_dbg(ql_dbg_disc, vha, 0x2000,
3514 "Trying Fabric Login w/loop id 0x%04x for port "
3515 "%02x%02x%02x.\n",
3516 fcport->loop_id, fcport->d_id.b.domain,
3517 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3518
3519
3520 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
3521 fcport->d_id.b.domain, fcport->d_id.b.area,
3522 fcport->d_id.b.al_pa, mb, BIT_0);
3523 if (rval != QLA_SUCCESS) {
3524 return rval;
3525 }
3526 if (mb[0] == MBS_PORT_ID_USED) {
3527
3528
3529
3530
3531
3532
3533
3534 retry++;
3535 tmp_loopid = fcport->loop_id;
3536 fcport->loop_id = mb[1];
3537
3538 ql_dbg(ql_dbg_disc, vha, 0x2001,
3539 "Fabric Login: port in use - next loop "
3540 "id=0x%04x, port id= %02x%02x%02x.\n",
3541 fcport->loop_id, fcport->d_id.b.domain,
3542 fcport->d_id.b.area, fcport->d_id.b.al_pa);
3543
3544 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
3545
3546
3547
3548 if (retry) {
3549
3550 *next_loopid = tmp_loopid;
3551 } else {
3552
3553
3554
3555
3556 *next_loopid = (fcport->loop_id + 1);
3557 }
3558
3559 if (mb[1] & BIT_0) {
3560 fcport->port_type = FCT_INITIATOR;
3561 } else {
3562 fcport->port_type = FCT_TARGET;
3563 if (mb[1] & BIT_1) {
3564 fcport->flags |= FCF_FCP2_DEVICE;
3565 }
3566 }
3567
3568 if (mb[10] & BIT_0)
3569 fcport->supported_classes |= FC_COS_CLASS2;
3570 if (mb[10] & BIT_1)
3571 fcport->supported_classes |= FC_COS_CLASS3;
3572
3573 if (IS_FWI2_CAPABLE(ha)) {
3574 if (mb[10] & BIT_7)
3575 fcport->flags |=
3576 FCF_CONF_COMP_SUPPORTED;
3577 }
3578
3579 rval = QLA_SUCCESS;
3580 break;
3581 } else if (mb[0] == MBS_LOOP_ID_USED) {
3582
3583
3584
3585 fcport->loop_id++;
3586 rval = qla2x00_find_new_loop_id(vha, fcport);
3587 if (rval != QLA_SUCCESS) {
3588
3589 break;
3590 }
3591 } else if (mb[0] == MBS_COMMAND_ERROR) {
3592
3593
3594
3595
3596
3597 *next_loopid = fcport->loop_id;
3598 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3599 fcport->d_id.b.domain, fcport->d_id.b.area,
3600 fcport->d_id.b.al_pa);
3601 qla2x00_mark_device_lost(vha, fcport, 1, 0);
3602
3603 rval = 1;
3604 break;
3605 } else {
3606
3607
3608
3609 ql_dbg(ql_dbg_disc, vha, 0x2002,
3610 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
3611 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
3612 fcport->d_id.b.area, fcport->d_id.b.al_pa,
3613 fcport->loop_id, jiffies);
3614
3615 *next_loopid = fcport->loop_id;
3616 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
3617 fcport->d_id.b.domain, fcport->d_id.b.area,
3618 fcport->d_id.b.al_pa);
3619 fcport->loop_id = FC_NO_LOOP_ID;
3620 fcport->login_retry = 0;
3621
3622 rval = 3;
3623 break;
3624 }
3625 }
3626
3627 return (rval);
3628}
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643int
3644qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
3645{
3646 int rval;
3647 uint16_t mb[MAILBOX_REGISTER_COUNT];
3648
3649 memset(mb, 0, sizeof(mb));
3650 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
3651 if (rval == QLA_SUCCESS) {
3652
3653 if (mb[0] == MBS_COMMAND_ERROR)
3654 rval = 1;
3655 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
3656
3657 rval = 3;
3658 }
3659
3660 return (rval);
3661}
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673int
3674qla2x00_loop_resync(scsi_qla_host_t *vha)
3675{
3676 int rval = QLA_SUCCESS;
3677 uint32_t wait_time;
3678 struct req_que *req;
3679 struct rsp_que *rsp;
3680
3681 if (vha->hw->flags.cpu_affinity_enabled)
3682 req = vha->hw->req_q_map[0];
3683 else
3684 req = vha->req;
3685 rsp = req->rsp;
3686
3687 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3688 if (vha->flags.online) {
3689 if (!(rval = qla2x00_fw_ready(vha))) {
3690
3691 wait_time = 256;
3692 do {
3693
3694 qla2x00_marker(vha, req, rsp, 0, 0,
3695 MK_SYNC_ALL);
3696 vha->marker_needed = 0;
3697
3698
3699 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
3700
3701 qla2x00_configure_loop(vha);
3702 wait_time--;
3703 } while (!atomic_read(&vha->loop_down_timer) &&
3704 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3705 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
3706 &vha->dpc_flags)));
3707 }
3708 }
3709
3710 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
3711 return (QLA_FUNCTION_FAILED);
3712
3713 if (rval)
3714 ql_dbg(ql_dbg_disc, vha, 0x206c,
3715 "%s *** FAILED ***.\n", __func__);
3716
3717 return (rval);
3718}
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
3729{
3730 int32_t rval = 0;
3731
3732 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
3733
3734 atomic_set(&ha->loop_down_timer, 0);
3735 if (!(ha->device_flags & DFLG_NO_CABLE)) {
3736 atomic_set(&ha->loop_state, LOOP_UP);
3737 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
3738 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
3739 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
3740
3741 rval = qla2x00_loop_resync(ha);
3742 } else
3743 atomic_set(&ha->loop_state, LOOP_DEAD);
3744
3745 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
3746 }
3747
3748 return rval;
3749}
3750
3751void
3752qla2x00_update_fcports(scsi_qla_host_t *base_vha)
3753{
3754 fc_port_t *fcport;
3755 struct scsi_qla_host *vha;
3756 struct qla_hw_data *ha = base_vha->hw;
3757 unsigned long flags;
3758
3759 spin_lock_irqsave(&ha->vport_slock, flags);
3760
3761 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
3762 atomic_inc(&vha->vref_count);
3763 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3764 if (fcport->drport &&
3765 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
3766 spin_unlock_irqrestore(&ha->vport_slock, flags);
3767
3768 qla2x00_rport_del(fcport);
3769
3770 spin_lock_irqsave(&ha->vport_slock, flags);
3771 }
3772 }
3773 atomic_dec(&vha->vref_count);
3774 }
3775 spin_unlock_irqrestore(&ha->vport_slock, flags);
3776}
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786void
3787qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
3788{
3789 struct qla_hw_data *ha = vha->hw;
3790 struct scsi_qla_host *vp;
3791
3792 ql_dbg(ql_dbg_p3p, vha, 0xb002,
3793 "Performing ISP error recovery - ha=%p.\n", ha);
3794
3795 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
3796 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
3797 atomic_set(&vha->loop_state, LOOP_DOWN);
3798 qla2x00_mark_all_devices_lost(vha, 0);
3799 list_for_each_entry(vp, &ha->vp_list, list)
3800 qla2x00_mark_all_devices_lost(vha, 0);
3801 } else {
3802 if (!atomic_read(&vha->loop_down_timer))
3803 atomic_set(&vha->loop_down_timer,
3804 LOOP_DOWN_TIME);
3805 }
3806
3807 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
3808}
3809
3810void
3811qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
3812{
3813 struct qla_hw_data *ha = vha->hw;
3814 struct scsi_qla_host *vp;
3815 unsigned long flags;
3816 fc_port_t *fcport;
3817
3818
3819
3820
3821 if (!IS_QLA82XX(ha))
3822 vha->flags.online = 0;
3823 ha->flags.chip_reset_done = 0;
3824 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3825 vha->qla_stats.total_isp_aborts++;
3826
3827 ql_log(ql_log_info, vha, 0x00af,
3828 "Performing ISP error recovery - ha=%p.\n", ha);
3829
3830
3831
3832
3833
3834 if (!IS_QLA82XX(ha))
3835 ha->isp_ops->reset_chip(vha);
3836
3837 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
3838 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
3839 atomic_set(&vha->loop_state, LOOP_DOWN);
3840 qla2x00_mark_all_devices_lost(vha, 0);
3841
3842 spin_lock_irqsave(&ha->vport_slock, flags);
3843 list_for_each_entry(vp, &ha->vp_list, list) {
3844 atomic_inc(&vp->vref_count);
3845 spin_unlock_irqrestore(&ha->vport_slock, flags);
3846
3847 qla2x00_mark_all_devices_lost(vp, 0);
3848
3849 spin_lock_irqsave(&ha->vport_slock, flags);
3850 atomic_dec(&vp->vref_count);
3851 }
3852 spin_unlock_irqrestore(&ha->vport_slock, flags);
3853 } else {
3854 if (!atomic_read(&vha->loop_down_timer))
3855 atomic_set(&vha->loop_down_timer,
3856 LOOP_DOWN_TIME);
3857 }
3858
3859
3860 list_for_each_entry(fcport, &vha->vp_fcports, list)
3861 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
3862 spin_lock_irqsave(&ha->vport_slock, flags);
3863 list_for_each_entry(vp, &ha->vp_list, list) {
3864 atomic_inc(&vp->vref_count);
3865 spin_unlock_irqrestore(&ha->vport_slock, flags);
3866
3867 list_for_each_entry(fcport, &vp->vp_fcports, list)
3868 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
3869
3870 spin_lock_irqsave(&ha->vport_slock, flags);
3871 atomic_dec(&vp->vref_count);
3872 }
3873 spin_unlock_irqrestore(&ha->vport_slock, flags);
3874
3875 if (!ha->flags.eeh_busy) {
3876
3877 if (IS_QLA82XX(ha)) {
3878 qla82xx_chip_reset_cleanup(vha);
3879 ql_log(ql_log_info, vha, 0x00b4,
3880 "Done chip reset cleanup.\n");
3881
3882
3883
3884
3885 vha->flags.online = 0;
3886 }
3887
3888
3889 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
3890 }
3891}
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903int
3904qla2x00_abort_isp(scsi_qla_host_t *vha)
3905{
3906 int rval;
3907 uint8_t status = 0;
3908 struct qla_hw_data *ha = vha->hw;
3909 struct scsi_qla_host *vp;
3910 struct req_que *req = ha->req_q_map[0];
3911 unsigned long flags;
3912
3913 if (vha->flags.online) {
3914 qla2x00_abort_isp_cleanup(vha);
3915
3916 if (unlikely(pci_channel_offline(ha->pdev) &&
3917 ha->flags.pci_channel_io_perm_failure)) {
3918 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3919 status = 0;
3920 return status;
3921 }
3922
3923 ha->isp_ops->get_flash_version(vha, req->ring);
3924
3925 ha->isp_ops->nvram_config(vha);
3926
3927 if (!qla2x00_restart_isp(vha)) {
3928 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
3929
3930 if (!atomic_read(&vha->loop_down_timer)) {
3931
3932
3933
3934
3935 vha->marker_needed = 1;
3936 }
3937
3938 vha->flags.online = 1;
3939
3940 ha->isp_ops->enable_intrs(ha);
3941
3942 ha->isp_abort_cnt = 0;
3943 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3944
3945 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
3946 qla2x00_get_fw_version(vha);
3947 if (ha->fce) {
3948 ha->flags.fce_enabled = 1;
3949 memset(ha->fce, 0,
3950 fce_calc_size(ha->fce_bufs));
3951 rval = qla2x00_enable_fce_trace(vha,
3952 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
3953 &ha->fce_bufs);
3954 if (rval) {
3955 ql_log(ql_log_warn, vha, 0x8033,
3956 "Unable to reinitialize FCE "
3957 "(%d).\n", rval);
3958 ha->flags.fce_enabled = 0;
3959 }
3960 }
3961
3962 if (ha->eft) {
3963 memset(ha->eft, 0, EFT_SIZE);
3964 rval = qla2x00_enable_eft_trace(vha,
3965 ha->eft_dma, EFT_NUM_BUFFERS);
3966 if (rval) {
3967 ql_log(ql_log_warn, vha, 0x8034,
3968 "Unable to reinitialize EFT "
3969 "(%d).\n", rval);
3970 }
3971 }
3972 } else {
3973 vha->flags.online = 1;
3974 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3975 if (ha->isp_abort_cnt == 0) {
3976 ql_log(ql_log_fatal, vha, 0x8035,
3977 "ISP error recover failed - "
3978 "board disabled.\n");
3979
3980
3981
3982
3983 ha->isp_ops->reset_adapter(vha);
3984 vha->flags.online = 0;
3985 clear_bit(ISP_ABORT_RETRY,
3986 &vha->dpc_flags);
3987 status = 0;
3988 } else {
3989 ha->isp_abort_cnt--;
3990 ql_dbg(ql_dbg_taskm, vha, 0x8020,
3991 "ISP abort - retry remaining %d.\n",
3992 ha->isp_abort_cnt);
3993 status = 1;
3994 }
3995 } else {
3996 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3997 ql_dbg(ql_dbg_taskm, vha, 0x8021,
3998 "ISP error recovery - retrying (%d) "
3999 "more times.\n", ha->isp_abort_cnt);
4000 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
4001 status = 1;
4002 }
4003 }
4004
4005 }
4006
4007 if (!status) {
4008 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
4009
4010 spin_lock_irqsave(&ha->vport_slock, flags);
4011 list_for_each_entry(vp, &ha->vp_list, list) {
4012 if (vp->vp_idx) {
4013 atomic_inc(&vp->vref_count);
4014 spin_unlock_irqrestore(&ha->vport_slock, flags);
4015
4016 qla2x00_vp_abort_isp(vp);
4017
4018 spin_lock_irqsave(&ha->vport_slock, flags);
4019 atomic_dec(&vp->vref_count);
4020 }
4021 }
4022 spin_unlock_irqrestore(&ha->vport_slock, flags);
4023
4024 } else {
4025 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
4026 __func__);
4027 }
4028
4029 return(status);
4030}
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042static int
4043qla2x00_restart_isp(scsi_qla_host_t *vha)
4044{
4045 int status = 0;
4046 uint32_t wait_time;
4047 struct qla_hw_data *ha = vha->hw;
4048 struct req_que *req = ha->req_q_map[0];
4049 struct rsp_que *rsp = ha->rsp_q_map[0];
4050 unsigned long flags;
4051
4052
4053 if (qla2x00_isp_firmware(vha)) {
4054 vha->flags.online = 0;
4055 status = ha->isp_ops->chip_diag(vha);
4056 if (!status)
4057 status = qla2x00_setup_chip(vha);
4058 }
4059
4060 if (!status && !(status = qla2x00_init_rings(vha))) {
4061 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4062 ha->flags.chip_reset_done = 1;
4063
4064 qla25xx_init_queues(ha);
4065
4066 status = qla2x00_fw_ready(vha);
4067 if (!status) {
4068 ql_dbg(ql_dbg_taskm, vha, 0x8031,
4069 "Start configure loop status = %d.\n", status);
4070
4071
4072 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
4073
4074 vha->flags.online = 1;
4075
4076
4077
4078
4079
4080 spin_lock_irqsave(&ha->hardware_lock, flags);
4081 if (qla_tgt_mode_enabled(vha))
4082 qlt_24xx_process_atio_queue(vha);
4083 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4084
4085
4086 wait_time = 256;
4087 do {
4088 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4089 qla2x00_configure_loop(vha);
4090 wait_time--;
4091 } while (!atomic_read(&vha->loop_down_timer) &&
4092 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
4093 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
4094 &vha->dpc_flags)));
4095 }
4096
4097
4098 if ((vha->device_flags & DFLG_NO_CABLE))
4099 status = 0;
4100
4101 ql_dbg(ql_dbg_taskm, vha, 0x8032,
4102 "Configure loop done, status = 0x%x.\n", status);
4103 }
4104 return (status);
4105}
4106
4107static int
4108qla25xx_init_queues(struct qla_hw_data *ha)
4109{
4110 struct rsp_que *rsp = NULL;
4111 struct req_que *req = NULL;
4112 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4113 int ret = -1;
4114 int i;
4115
4116 for (i = 1; i < ha->max_rsp_queues; i++) {
4117 rsp = ha->rsp_q_map[i];
4118 if (rsp) {
4119 rsp->options &= ~BIT_0;
4120 ret = qla25xx_init_rsp_que(base_vha, rsp);
4121 if (ret != QLA_SUCCESS)
4122 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
4123 "%s Rsp que: %d init failed.\n",
4124 __func__, rsp->id);
4125 else
4126 ql_dbg(ql_dbg_init, base_vha, 0x0100,
4127 "%s Rsp que: %d inited.\n",
4128 __func__, rsp->id);
4129 }
4130 }
4131 for (i = 1; i < ha->max_req_queues; i++) {
4132 req = ha->req_q_map[i];
4133 if (req) {
4134
4135 req->options &= ~BIT_0;
4136 ret = qla25xx_init_req_que(base_vha, req);
4137 if (ret != QLA_SUCCESS)
4138 ql_dbg(ql_dbg_init, base_vha, 0x0101,
4139 "%s Req que: %d init failed.\n",
4140 __func__, req->id);
4141 else
4142 ql_dbg(ql_dbg_init, base_vha, 0x0102,
4143 "%s Req que: %d inited.\n",
4144 __func__, req->id);
4145 }
4146 }
4147 return ret;
4148}
4149
4150
4151
4152
4153
4154
4155
4156
4157void
4158qla2x00_reset_adapter(scsi_qla_host_t *vha)
4159{
4160 unsigned long flags = 0;
4161 struct qla_hw_data *ha = vha->hw;
4162 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4163
4164 vha->flags.online = 0;
4165 ha->isp_ops->disable_intrs(ha);
4166
4167 spin_lock_irqsave(&ha->hardware_lock, flags);
4168 WRT_REG_WORD(®->hccr, HCCR_RESET_RISC);
4169 RD_REG_WORD(®->hccr);
4170 WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC);
4171 RD_REG_WORD(®->hccr);
4172 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4173}
4174
4175void
4176qla24xx_reset_adapter(scsi_qla_host_t *vha)
4177{
4178 unsigned long flags = 0;
4179 struct qla_hw_data *ha = vha->hw;
4180 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
4181
4182 if (IS_QLA82XX(ha))
4183 return;
4184
4185 vha->flags.online = 0;
4186 ha->isp_ops->disable_intrs(ha);
4187
4188 spin_lock_irqsave(&ha->hardware_lock, flags);
4189 WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET);
4190 RD_REG_DWORD(®->hccr);
4191 WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE);
4192 RD_REG_DWORD(®->hccr);
4193 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4194
4195 if (IS_NOPOLLING_TYPE(ha))
4196 ha->isp_ops->enable_intrs(ha);
4197}
4198
4199
4200
4201
4202static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
4203 struct nvram_24xx *nv)
4204{
4205#ifdef CONFIG_SPARC
4206 struct qla_hw_data *ha = vha->hw;
4207 struct pci_dev *pdev = ha->pdev;
4208 struct device_node *dp = pci_device_to_OF_node(pdev);
4209 const u8 *val;
4210 int len;
4211
4212 val = of_get_property(dp, "port-wwn", &len);
4213 if (val && len >= WWN_SIZE)
4214 memcpy(nv->port_name, val, WWN_SIZE);
4215
4216 val = of_get_property(dp, "node-wwn", &len);
4217 if (val && len >= WWN_SIZE)
4218 memcpy(nv->node_name, val, WWN_SIZE);
4219#endif
4220}
4221
4222int
4223qla24xx_nvram_config(scsi_qla_host_t *vha)
4224{
4225 int rval;
4226 struct init_cb_24xx *icb;
4227 struct nvram_24xx *nv;
4228 uint32_t *dptr;
4229 uint8_t *dptr1, *dptr2;
4230 uint32_t chksum;
4231 uint16_t cnt;
4232 struct qla_hw_data *ha = vha->hw;
4233
4234 rval = QLA_SUCCESS;
4235 icb = (struct init_cb_24xx *)ha->init_cb;
4236 nv = ha->nvram;
4237
4238
4239 if (ha->flags.port0) {
4240 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
4241 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
4242 } else {
4243 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
4244 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
4245 }
4246 ha->nvram_size = sizeof(struct nvram_24xx);
4247 ha->vpd_size = FA_NVRAM_VPD_SIZE;
4248 if (IS_QLA82XX(ha))
4249 ha->vpd_size = FA_VPD_SIZE_82XX;
4250
4251
4252 ha->vpd = ha->nvram + VPD_OFFSET;
4253 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
4254 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
4255
4256
4257 dptr = (uint32_t *)nv;
4258 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
4259 ha->nvram_size);
4260 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
4261 chksum += le32_to_cpu(*dptr++);
4262
4263 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
4264 "Contents of NVRAM\n");
4265 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
4266 (uint8_t *)nv, ha->nvram_size);
4267
4268
4269 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
4270 || nv->id[3] != ' ' ||
4271 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
4272
4273 ql_log(ql_log_warn, vha, 0x006b,
4274 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
4275 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
4276 ql_log(ql_log_warn, vha, 0x006c,
4277 "Falling back to functioning (yet invalid -- WWPN) "
4278 "defaults.\n");
4279
4280
4281
4282
4283 memset(nv, 0, ha->nvram_size);
4284 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
4285 nv->version = __constant_cpu_to_le16(ICB_VERSION);
4286 nv->frame_payload_size = __constant_cpu_to_le16(2048);
4287 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4288 nv->exchange_count = __constant_cpu_to_le16(0);
4289 nv->hard_address = __constant_cpu_to_le16(124);
4290 nv->port_name[0] = 0x21;
4291 nv->port_name[1] = 0x00 + ha->port_no;
4292 nv->port_name[2] = 0x00;
4293 nv->port_name[3] = 0xe0;
4294 nv->port_name[4] = 0x8b;
4295 nv->port_name[5] = 0x1c;
4296 nv->port_name[6] = 0x55;
4297 nv->port_name[7] = 0x86;
4298 nv->node_name[0] = 0x20;
4299 nv->node_name[1] = 0x00;
4300 nv->node_name[2] = 0x00;
4301 nv->node_name[3] = 0xe0;
4302 nv->node_name[4] = 0x8b;
4303 nv->node_name[5] = 0x1c;
4304 nv->node_name[6] = 0x55;
4305 nv->node_name[7] = 0x86;
4306 qla24xx_nvram_wwn_from_ofw(vha, nv);
4307 nv->login_retry_count = __constant_cpu_to_le16(8);
4308 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
4309 nv->login_timeout = __constant_cpu_to_le16(0);
4310 nv->firmware_options_1 =
4311 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
4312 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
4313 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
4314 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
4315 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
4316 nv->efi_parameters = __constant_cpu_to_le32(0);
4317 nv->reset_delay = 5;
4318 nv->max_luns_per_target = __constant_cpu_to_le16(128);
4319 nv->port_down_retry_count = __constant_cpu_to_le16(30);
4320 nv->link_down_timeout = __constant_cpu_to_le16(30);
4321
4322 rval = 1;
4323 }
4324
4325 if (!qla_ini_mode_enabled(vha)) {
4326
4327 nv->firmware_options_1 &= __constant_cpu_to_le32(~BIT_13);
4328
4329 nv->host_p &= __constant_cpu_to_le32(~BIT_10);
4330 }
4331
4332 qlt_24xx_config_nvram_stage1(vha, nv);
4333
4334
4335 memset(icb, 0, ha->init_cb_size);
4336
4337
4338 dptr1 = (uint8_t *)icb;
4339 dptr2 = (uint8_t *)&nv->version;
4340 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
4341 while (cnt--)
4342 *dptr1++ = *dptr2++;
4343
4344 icb->login_retry_count = nv->login_retry_count;
4345 icb->link_down_on_nos = nv->link_down_on_nos;
4346
4347
4348 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
4349 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
4350 cnt = (uint8_t *)&icb->reserved_3 -
4351 (uint8_t *)&icb->interrupt_delay_timer;
4352 while (cnt--)
4353 *dptr1++ = *dptr2++;
4354
4355
4356
4357
4358 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
4359 "QLA2462");
4360
4361 qlt_24xx_config_nvram_stage2(vha, icb);
4362
4363 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
4364
4365 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4366 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4367 }
4368
4369
4370 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
4371
4372
4373
4374
4375 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4376 icb->node_name[0] &= 0xF0;
4377 }
4378
4379
4380 ha->flags.disable_risc_code_load = 0;
4381 ha->flags.enable_lip_reset = 0;
4382 ha->flags.enable_lip_full_login =
4383 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
4384 ha->flags.enable_target_reset =
4385 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
4386 ha->flags.enable_led_scheme = 0;
4387 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
4388
4389 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
4390 (BIT_6 | BIT_5 | BIT_4)) >> 4;
4391
4392 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
4393 sizeof(ha->fw_seriallink_options24));
4394
4395
4396 ha->serial0 = icb->port_name[5];
4397 ha->serial1 = icb->port_name[6];
4398 ha->serial2 = icb->port_name[7];
4399 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4400 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
4401
4402 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
4403
4404 ha->retry_count = le16_to_cpu(nv->login_retry_count);
4405
4406
4407 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
4408 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
4409 if (le16_to_cpu(nv->login_timeout) < 4)
4410 nv->login_timeout = __constant_cpu_to_le16(4);
4411 ha->login_timeout = le16_to_cpu(nv->login_timeout);
4412 icb->login_timeout = nv->login_timeout;
4413
4414
4415 ha->r_a_tov = 100;
4416
4417 ha->loop_reset_delay = nv->reset_delay;
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429 if (le16_to_cpu(nv->link_down_timeout) == 0) {
4430 ha->loop_down_abort_time =
4431 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4432 } else {
4433 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
4434 ha->loop_down_abort_time =
4435 (LOOP_DOWN_TIME - ha->link_down_timeout);
4436 }
4437
4438
4439 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
4440 if (qlport_down_retry)
4441 ha->port_down_retry_count = qlport_down_retry;
4442
4443
4444 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
4445 if (ha->port_down_retry_count ==
4446 le16_to_cpu(nv->port_down_retry_count) &&
4447 ha->port_down_retry_count > 3)
4448 ha->login_retry_count = ha->port_down_retry_count;
4449 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4450 ha->login_retry_count = ha->port_down_retry_count;
4451 if (ql2xloginretrycount)
4452 ha->login_retry_count = ql2xloginretrycount;
4453
4454
4455 if (!vha->flags.init_done) {
4456 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
4457 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4458 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
4459 le16_to_cpu(icb->interrupt_delay_timer): 2;
4460 }
4461 icb->firmware_options_2 &= __constant_cpu_to_le32(
4462 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
4463 vha->flags.process_response_queue = 0;
4464 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4465 ha->zio_mode = QLA_ZIO_MODE_6;
4466
4467 ql_log(ql_log_info, vha, 0x006f,
4468 "ZIO mode %d enabled; timer delay (%d us).\n",
4469 ha->zio_mode, ha->zio_timer * 100);
4470
4471 icb->firmware_options_2 |= cpu_to_le32(
4472 (uint32_t)ha->zio_mode);
4473 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
4474 vha->flags.process_response_queue = 1;
4475 }
4476
4477 if (rval) {
4478 ql_log(ql_log_warn, vha, 0x0070,
4479 "NVRAM configuration failed.\n");
4480 }
4481 return (rval);
4482}
4483
4484static int
4485qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
4486 uint32_t faddr)
4487{
4488 int rval = QLA_SUCCESS;
4489 int segments, fragment;
4490 uint32_t *dcode, dlen;
4491 uint32_t risc_addr;
4492 uint32_t risc_size;
4493 uint32_t i;
4494 struct qla_hw_data *ha = vha->hw;
4495 struct req_que *req = ha->req_q_map[0];
4496
4497 ql_dbg(ql_dbg_init, vha, 0x008b,
4498 "FW: Loading firmware from flash (%x).\n", faddr);
4499
4500 rval = QLA_SUCCESS;
4501
4502 segments = FA_RISC_CODE_SEGMENTS;
4503 dcode = (uint32_t *)req->ring;
4504 *srisc_addr = 0;
4505
4506
4507 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
4508 for (i = 0; i < 4; i++)
4509 dcode[i] = be32_to_cpu(dcode[i]);
4510 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4511 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
4512 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
4513 dcode[3] == 0)) {
4514 ql_log(ql_log_fatal, vha, 0x008c,
4515 "Unable to verify the integrity of flash firmware "
4516 "image.\n");
4517 ql_log(ql_log_fatal, vha, 0x008d,
4518 "Firmware data: %08x %08x %08x %08x.\n",
4519 dcode[0], dcode[1], dcode[2], dcode[3]);
4520
4521 return QLA_FUNCTION_FAILED;
4522 }
4523
4524 while (segments && rval == QLA_SUCCESS) {
4525
4526 qla24xx_read_flash_data(vha, dcode, faddr, 4);
4527
4528 risc_addr = be32_to_cpu(dcode[2]);
4529 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
4530 risc_size = be32_to_cpu(dcode[3]);
4531
4532 fragment = 0;
4533 while (risc_size > 0 && rval == QLA_SUCCESS) {
4534 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
4535 if (dlen > risc_size)
4536 dlen = risc_size;
4537
4538 ql_dbg(ql_dbg_init, vha, 0x008e,
4539 "Loading risc segment@ risc addr %x "
4540 "number of dwords 0x%x offset 0x%x.\n",
4541 risc_addr, dlen, faddr);
4542
4543 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
4544 for (i = 0; i < dlen; i++)
4545 dcode[i] = swab32(dcode[i]);
4546
4547 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
4548 dlen);
4549 if (rval) {
4550 ql_log(ql_log_fatal, vha, 0x008f,
4551 "Failed to load segment %d of firmware.\n",
4552 fragment);
4553 break;
4554 }
4555
4556 faddr += dlen;
4557 risc_addr += dlen;
4558 risc_size -= dlen;
4559 fragment++;
4560 }
4561
4562
4563 segments--;
4564 }
4565
4566 return rval;
4567}
4568
4569#define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
4570
4571int
4572qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
4573{
4574 int rval;
4575 int i, fragment;
4576 uint16_t *wcode, *fwcode;
4577 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
4578 struct fw_blob *blob;
4579 struct qla_hw_data *ha = vha->hw;
4580 struct req_que *req = ha->req_q_map[0];
4581
4582
4583 blob = qla2x00_request_firmware(vha);
4584 if (!blob) {
4585 ql_log(ql_log_info, vha, 0x0083,
4586 "Fimware image unavailable.\n");
4587 ql_log(ql_log_info, vha, 0x0084,
4588 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
4589 return QLA_FUNCTION_FAILED;
4590 }
4591
4592 rval = QLA_SUCCESS;
4593
4594 wcode = (uint16_t *)req->ring;
4595 *srisc_addr = 0;
4596 fwcode = (uint16_t *)blob->fw->data;
4597 fwclen = 0;
4598
4599
4600 if (blob->fw->size < 8 * sizeof(uint16_t)) {
4601 ql_log(ql_log_fatal, vha, 0x0085,
4602 "Unable to verify integrity of firmware image (%Zd).\n",
4603 blob->fw->size);
4604 goto fail_fw_integrity;
4605 }
4606 for (i = 0; i < 4; i++)
4607 wcode[i] = be16_to_cpu(fwcode[i + 4]);
4608 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
4609 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
4610 wcode[2] == 0 && wcode[3] == 0)) {
4611 ql_log(ql_log_fatal, vha, 0x0086,
4612 "Unable to verify integrity of firmware image.\n");
4613 ql_log(ql_log_fatal, vha, 0x0087,
4614 "Firmware data: %04x %04x %04x %04x.\n",
4615 wcode[0], wcode[1], wcode[2], wcode[3]);
4616 goto fail_fw_integrity;
4617 }
4618
4619 seg = blob->segs;
4620 while (*seg && rval == QLA_SUCCESS) {
4621 risc_addr = *seg;
4622 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
4623 risc_size = be16_to_cpu(fwcode[3]);
4624
4625
4626 fwclen += risc_size * sizeof(uint16_t);
4627 if (blob->fw->size < fwclen) {
4628 ql_log(ql_log_fatal, vha, 0x0088,
4629 "Unable to verify integrity of firmware image "
4630 "(%Zd).\n", blob->fw->size);
4631 goto fail_fw_integrity;
4632 }
4633
4634 fragment = 0;
4635 while (risc_size > 0 && rval == QLA_SUCCESS) {
4636 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
4637 if (wlen > risc_size)
4638 wlen = risc_size;
4639 ql_dbg(ql_dbg_init, vha, 0x0089,
4640 "Loading risc segment@ risc addr %x number of "
4641 "words 0x%x.\n", risc_addr, wlen);
4642
4643 for (i = 0; i < wlen; i++)
4644 wcode[i] = swab16(fwcode[i]);
4645
4646 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
4647 wlen);
4648 if (rval) {
4649 ql_log(ql_log_fatal, vha, 0x008a,
4650 "Failed to load segment %d of firmware.\n",
4651 fragment);
4652 break;
4653 }
4654
4655 fwcode += wlen;
4656 risc_addr += wlen;
4657 risc_size -= wlen;
4658 fragment++;
4659 }
4660
4661
4662 seg++;
4663 }
4664 return rval;
4665
4666fail_fw_integrity:
4667 return QLA_FUNCTION_FAILED;
4668}
4669
4670static int
4671qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
4672{
4673 int rval;
4674 int segments, fragment;
4675 uint32_t *dcode, dlen;
4676 uint32_t risc_addr;
4677 uint32_t risc_size;
4678 uint32_t i;
4679 struct fw_blob *blob;
4680 uint32_t *fwcode, fwclen;
4681 struct qla_hw_data *ha = vha->hw;
4682 struct req_que *req = ha->req_q_map[0];
4683
4684
4685 blob = qla2x00_request_firmware(vha);
4686 if (!blob) {
4687 ql_log(ql_log_warn, vha, 0x0090,
4688 "Fimware image unavailable.\n");
4689 ql_log(ql_log_warn, vha, 0x0091,
4690 "Firmware images can be retrieved from: "
4691 QLA_FW_URL ".\n");
4692
4693 return QLA_FUNCTION_FAILED;
4694 }
4695
4696 ql_dbg(ql_dbg_init, vha, 0x0092,
4697 "FW: Loading via request-firmware.\n");
4698
4699 rval = QLA_SUCCESS;
4700
4701 segments = FA_RISC_CODE_SEGMENTS;
4702 dcode = (uint32_t *)req->ring;
4703 *srisc_addr = 0;
4704 fwcode = (uint32_t *)blob->fw->data;
4705 fwclen = 0;
4706
4707
4708 if (blob->fw->size < 8 * sizeof(uint32_t)) {
4709 ql_log(ql_log_fatal, vha, 0x0093,
4710 "Unable to verify integrity of firmware image (%Zd).\n",
4711 blob->fw->size);
4712 goto fail_fw_integrity;
4713 }
4714 for (i = 0; i < 4; i++)
4715 dcode[i] = be32_to_cpu(fwcode[i + 4]);
4716 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
4717 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
4718 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
4719 dcode[3] == 0)) {
4720 ql_log(ql_log_fatal, vha, 0x0094,
4721 "Unable to verify integrity of firmware image (%Zd).\n",
4722 blob->fw->size);
4723 ql_log(ql_log_fatal, vha, 0x0095,
4724 "Firmware data: %08x %08x %08x %08x.\n",
4725 dcode[0], dcode[1], dcode[2], dcode[3]);
4726 goto fail_fw_integrity;
4727 }
4728
4729 while (segments && rval == QLA_SUCCESS) {
4730 risc_addr = be32_to_cpu(fwcode[2]);
4731 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
4732 risc_size = be32_to_cpu(fwcode[3]);
4733
4734
4735 fwclen += risc_size * sizeof(uint32_t);
4736 if (blob->fw->size < fwclen) {
4737 ql_log(ql_log_fatal, vha, 0x0096,
4738 "Unable to verify integrity of firmware image "
4739 "(%Zd).\n", blob->fw->size);
4740
4741 goto fail_fw_integrity;
4742 }
4743
4744 fragment = 0;
4745 while (risc_size > 0 && rval == QLA_SUCCESS) {
4746 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
4747 if (dlen > risc_size)
4748 dlen = risc_size;
4749
4750 ql_dbg(ql_dbg_init, vha, 0x0097,
4751 "Loading risc segment@ risc addr %x "
4752 "number of dwords 0x%x.\n", risc_addr, dlen);
4753
4754 for (i = 0; i < dlen; i++)
4755 dcode[i] = swab32(fwcode[i]);
4756
4757 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
4758 dlen);
4759 if (rval) {
4760 ql_log(ql_log_fatal, vha, 0x0098,
4761 "Failed to load segment %d of firmware.\n",
4762 fragment);
4763 break;
4764 }
4765
4766 fwcode += dlen;
4767 risc_addr += dlen;
4768 risc_size -= dlen;
4769 fragment++;
4770 }
4771
4772
4773 segments--;
4774 }
4775 return rval;
4776
4777fail_fw_integrity:
4778 return QLA_FUNCTION_FAILED;
4779}
4780
4781int
4782qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
4783{
4784 int rval;
4785
4786 if (ql2xfwloadbin == 1)
4787 return qla81xx_load_risc(vha, srisc_addr);
4788
4789
4790
4791
4792
4793
4794 rval = qla24xx_load_risc_blob(vha, srisc_addr);
4795 if (rval == QLA_SUCCESS)
4796 return rval;
4797
4798 return qla24xx_load_risc_flash(vha, srisc_addr,
4799 vha->hw->flt_region_fw);
4800}
4801
4802int
4803qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
4804{
4805 int rval;
4806 struct qla_hw_data *ha = vha->hw;
4807
4808 if (ql2xfwloadbin == 2)
4809 goto try_blob_fw;
4810
4811
4812
4813
4814
4815
4816
4817 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
4818 if (rval == QLA_SUCCESS)
4819 return rval;
4820
4821try_blob_fw:
4822 rval = qla24xx_load_risc_blob(vha, srisc_addr);
4823 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
4824 return rval;
4825
4826 ql_log(ql_log_info, vha, 0x0099,
4827 "Attempting to fallback to golden firmware.\n");
4828 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
4829 if (rval != QLA_SUCCESS)
4830 return rval;
4831
4832 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
4833 ha->flags.running_gold_fw = 1;
4834 return rval;
4835}
4836
4837void
4838qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
4839{
4840 int ret, retries;
4841 struct qla_hw_data *ha = vha->hw;
4842
4843 if (ha->flags.pci_channel_io_perm_failure)
4844 return;
4845 if (!IS_FWI2_CAPABLE(ha))
4846 return;
4847 if (!ha->fw_major_version)
4848 return;
4849
4850 ret = qla2x00_stop_firmware(vha);
4851 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
4852 ret != QLA_INVALID_COMMAND && retries ; retries--) {
4853 ha->isp_ops->reset_chip(vha);
4854 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
4855 continue;
4856 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
4857 continue;
4858 ql_log(ql_log_info, vha, 0x8015,
4859 "Attempting retry of stop-firmware command.\n");
4860 ret = qla2x00_stop_firmware(vha);
4861 }
4862}
4863
4864int
4865qla24xx_configure_vhba(scsi_qla_host_t *vha)
4866{
4867 int rval = QLA_SUCCESS;
4868 int rval2;
4869 uint16_t mb[MAILBOX_REGISTER_COUNT];
4870 struct qla_hw_data *ha = vha->hw;
4871 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
4872 struct req_que *req;
4873 struct rsp_que *rsp;
4874
4875 if (!vha->vp_idx)
4876 return -EINVAL;
4877
4878 rval = qla2x00_fw_ready(base_vha);
4879 if (ha->flags.cpu_affinity_enabled)
4880 req = ha->req_q_map[0];
4881 else
4882 req = vha->req;
4883 rsp = req->rsp;
4884
4885 if (rval == QLA_SUCCESS) {
4886 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
4887 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
4888 }
4889
4890 vha->flags.management_server_logged_in = 0;
4891
4892
4893 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
4894 BIT_1);
4895 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
4896 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
4897 ql_dbg(ql_dbg_init, vha, 0x0120,
4898 "Failed SNS login: loop_id=%x, rval2=%d\n",
4899 NPH_SNS, rval2);
4900 else
4901 ql_dbg(ql_dbg_init, vha, 0x0103,
4902 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
4903 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
4904 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
4905 return (QLA_FUNCTION_FAILED);
4906 }
4907
4908 atomic_set(&vha->loop_down_timer, 0);
4909 atomic_set(&vha->loop_state, LOOP_UP);
4910 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4911 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4912 rval = qla2x00_loop_resync(base_vha);
4913
4914 return rval;
4915}
4916
4917
4918
4919static LIST_HEAD(qla_cs84xx_list);
4920static DEFINE_MUTEX(qla_cs84xx_mutex);
4921
4922static struct qla_chip_state_84xx *
4923qla84xx_get_chip(struct scsi_qla_host *vha)
4924{
4925 struct qla_chip_state_84xx *cs84xx;
4926 struct qla_hw_data *ha = vha->hw;
4927
4928 mutex_lock(&qla_cs84xx_mutex);
4929
4930
4931 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
4932 if (cs84xx->bus == ha->pdev->bus) {
4933 kref_get(&cs84xx->kref);
4934 goto done;
4935 }
4936 }
4937
4938 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
4939 if (!cs84xx)
4940 goto done;
4941
4942 kref_init(&cs84xx->kref);
4943 spin_lock_init(&cs84xx->access_lock);
4944 mutex_init(&cs84xx->fw_update_mutex);
4945 cs84xx->bus = ha->pdev->bus;
4946
4947 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
4948done:
4949 mutex_unlock(&qla_cs84xx_mutex);
4950 return cs84xx;
4951}
4952
4953static void
4954__qla84xx_chip_release(struct kref *kref)
4955{
4956 struct qla_chip_state_84xx *cs84xx =
4957 container_of(kref, struct qla_chip_state_84xx, kref);
4958
4959 mutex_lock(&qla_cs84xx_mutex);
4960 list_del(&cs84xx->list);
4961 mutex_unlock(&qla_cs84xx_mutex);
4962 kfree(cs84xx);
4963}
4964
4965void
4966qla84xx_put_chip(struct scsi_qla_host *vha)
4967{
4968 struct qla_hw_data *ha = vha->hw;
4969 if (ha->cs84xx)
4970 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
4971}
4972
4973static int
4974qla84xx_init_chip(scsi_qla_host_t *vha)
4975{
4976 int rval;
4977 uint16_t status[2];
4978 struct qla_hw_data *ha = vha->hw;
4979
4980 mutex_lock(&ha->cs84xx->fw_update_mutex);
4981
4982 rval = qla84xx_verify_chip(vha, status);
4983
4984 mutex_unlock(&ha->cs84xx->fw_update_mutex);
4985
4986 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
4987 QLA_SUCCESS;
4988}
4989
4990
4991
4992int
4993qla81xx_nvram_config(scsi_qla_host_t *vha)
4994{
4995 int rval;
4996 struct init_cb_81xx *icb;
4997 struct nvram_81xx *nv;
4998 uint32_t *dptr;
4999 uint8_t *dptr1, *dptr2;
5000 uint32_t chksum;
5001 uint16_t cnt;
5002 struct qla_hw_data *ha = vha->hw;
5003
5004 rval = QLA_SUCCESS;
5005 icb = (struct init_cb_81xx *)ha->init_cb;
5006 nv = ha->nvram;
5007
5008
5009 ha->nvram_size = sizeof(struct nvram_81xx);
5010 ha->vpd_size = FA_NVRAM_VPD_SIZE;
5011
5012
5013 ha->vpd = ha->nvram + VPD_OFFSET;
5014 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
5015 ha->vpd_size);
5016
5017
5018 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
5019 ha->nvram_size);
5020 dptr = (uint32_t *)nv;
5021 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
5022 chksum += le32_to_cpu(*dptr++);
5023
5024 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
5025 "Contents of NVRAM:\n");
5026 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
5027 (uint8_t *)nv, ha->nvram_size);
5028
5029
5030 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
5031 || nv->id[3] != ' ' ||
5032 nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
5033
5034 ql_log(ql_log_info, vha, 0x0073,
5035 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
5036 "version=0x%x.\n", chksum, nv->id[0],
5037 le16_to_cpu(nv->nvram_version));
5038 ql_log(ql_log_info, vha, 0x0074,
5039 "Falling back to functioning (yet invalid -- WWPN) "
5040 "defaults.\n");
5041
5042
5043
5044
5045 memset(nv, 0, ha->nvram_size);
5046 nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
5047 nv->version = __constant_cpu_to_le16(ICB_VERSION);
5048 nv->frame_payload_size = __constant_cpu_to_le16(2048);
5049 nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5050 nv->exchange_count = __constant_cpu_to_le16(0);
5051 nv->port_name[0] = 0x21;
5052 nv->port_name[1] = 0x00 + ha->port_no;
5053 nv->port_name[2] = 0x00;
5054 nv->port_name[3] = 0xe0;
5055 nv->port_name[4] = 0x8b;
5056 nv->port_name[5] = 0x1c;
5057 nv->port_name[6] = 0x55;
5058 nv->port_name[7] = 0x86;
5059 nv->node_name[0] = 0x20;
5060 nv->node_name[1] = 0x00;
5061 nv->node_name[2] = 0x00;
5062 nv->node_name[3] = 0xe0;
5063 nv->node_name[4] = 0x8b;
5064 nv->node_name[5] = 0x1c;
5065 nv->node_name[6] = 0x55;
5066 nv->node_name[7] = 0x86;
5067 nv->login_retry_count = __constant_cpu_to_le16(8);
5068 nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
5069 nv->login_timeout = __constant_cpu_to_le16(0);
5070 nv->firmware_options_1 =
5071 __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
5072 nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
5073 nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
5074 nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
5075 nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
5076 nv->efi_parameters = __constant_cpu_to_le32(0);
5077 nv->reset_delay = 5;
5078 nv->max_luns_per_target = __constant_cpu_to_le16(128);
5079 nv->port_down_retry_count = __constant_cpu_to_le16(30);
5080 nv->link_down_timeout = __constant_cpu_to_le16(180);
5081 nv->enode_mac[0] = 0x00;
5082 nv->enode_mac[1] = 0xC0;
5083 nv->enode_mac[2] = 0xDD;
5084 nv->enode_mac[3] = 0x04;
5085 nv->enode_mac[4] = 0x05;
5086 nv->enode_mac[5] = 0x06 + ha->port_no;
5087
5088 rval = 1;
5089 }
5090
5091
5092 memset(icb, 0, ha->init_cb_size);
5093
5094
5095 dptr1 = (uint8_t *)icb;
5096 dptr2 = (uint8_t *)&nv->version;
5097 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
5098 while (cnt--)
5099 *dptr1++ = *dptr2++;
5100
5101 icb->login_retry_count = nv->login_retry_count;
5102
5103
5104 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
5105 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
5106 cnt = (uint8_t *)&icb->reserved_5 -
5107 (uint8_t *)&icb->interrupt_delay_timer;
5108 while (cnt--)
5109 *dptr1++ = *dptr2++;
5110
5111 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
5112
5113 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
5114 icb->enode_mac[0] = 0x00;
5115 icb->enode_mac[1] = 0xC0;
5116 icb->enode_mac[2] = 0xDD;
5117 icb->enode_mac[3] = 0x04;
5118 icb->enode_mac[4] = 0x05;
5119 icb->enode_mac[5] = 0x06 + ha->port_no;
5120 }
5121
5122
5123 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
5124
5125
5126
5127
5128 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
5129 "QLE8XXX");
5130
5131
5132 if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
5133 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
5134 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
5135 }
5136
5137
5138 if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
5139
5140
5141
5142
5143 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
5144 icb->node_name[0] &= 0xF0;
5145 }
5146
5147
5148 ha->flags.disable_risc_code_load = 0;
5149 ha->flags.enable_lip_reset = 0;
5150 ha->flags.enable_lip_full_login =
5151 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
5152 ha->flags.enable_target_reset =
5153 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
5154 ha->flags.enable_led_scheme = 0;
5155 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
5156
5157 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
5158 (BIT_6 | BIT_5 | BIT_4)) >> 4;
5159
5160
5161 ha->serial0 = icb->port_name[5];
5162 ha->serial1 = icb->port_name[6];
5163 ha->serial2 = icb->port_name[7];
5164 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
5165 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
5166
5167 icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
5168
5169 ha->retry_count = le16_to_cpu(nv->login_retry_count);
5170
5171
5172 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
5173 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
5174 if (le16_to_cpu(nv->login_timeout) < 4)
5175 nv->login_timeout = __constant_cpu_to_le16(4);
5176 ha->login_timeout = le16_to_cpu(nv->login_timeout);
5177 icb->login_timeout = nv->login_timeout;
5178
5179
5180 ha->r_a_tov = 100;
5181
5182 ha->loop_reset_delay = nv->reset_delay;
5183
5184
5185
5186
5187
5188
5189
5190
5191
5192
5193
5194 if (le16_to_cpu(nv->link_down_timeout) == 0) {
5195 ha->loop_down_abort_time =
5196 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
5197 } else {
5198 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
5199 ha->loop_down_abort_time =
5200 (LOOP_DOWN_TIME - ha->link_down_timeout);
5201 }
5202
5203
5204 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
5205 if (qlport_down_retry)
5206 ha->port_down_retry_count = qlport_down_retry;
5207
5208
5209 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
5210 if (ha->port_down_retry_count ==
5211 le16_to_cpu(nv->port_down_retry_count) &&
5212 ha->port_down_retry_count > 3)
5213 ha->login_retry_count = ha->port_down_retry_count;
5214 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
5215 ha->login_retry_count = ha->port_down_retry_count;
5216 if (ql2xloginretrycount)
5217 ha->login_retry_count = ql2xloginretrycount;
5218
5219
5220 if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
5221 icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
5222
5223
5224 if (!vha->flags.init_done) {
5225 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
5226 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
5227 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
5228 le16_to_cpu(icb->interrupt_delay_timer): 2;
5229 }
5230 icb->firmware_options_2 &= __constant_cpu_to_le32(
5231 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
5232 vha->flags.process_response_queue = 0;
5233 if (ha->zio_mode != QLA_ZIO_DISABLED) {
5234 ha->zio_mode = QLA_ZIO_MODE_6;
5235
5236 ql_log(ql_log_info, vha, 0x0075,
5237 "ZIO mode %d enabled; timer delay (%d us).\n",
5238 ha->zio_mode,
5239 ha->zio_timer * 100);
5240
5241 icb->firmware_options_2 |= cpu_to_le32(
5242 (uint32_t)ha->zio_mode);
5243 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
5244 vha->flags.process_response_queue = 1;
5245 }
5246
5247 if (rval) {
5248 ql_log(ql_log_warn, vha, 0x0076,
5249 "NVRAM configuration failed.\n");
5250 }
5251 return (rval);
5252}
5253
5254int
5255qla82xx_restart_isp(scsi_qla_host_t *vha)
5256{
5257 int status, rval;
5258 uint32_t wait_time;
5259 struct qla_hw_data *ha = vha->hw;
5260 struct req_que *req = ha->req_q_map[0];
5261 struct rsp_que *rsp = ha->rsp_q_map[0];
5262 struct scsi_qla_host *vp;
5263 unsigned long flags;
5264
5265 status = qla2x00_init_rings(vha);
5266 if (!status) {
5267 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5268 ha->flags.chip_reset_done = 1;
5269
5270 status = qla2x00_fw_ready(vha);
5271 if (!status) {
5272 ql_log(ql_log_info, vha, 0x803c,
5273 "Start configure loop, status =%d.\n", status);
5274
5275
5276 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
5277
5278 vha->flags.online = 1;
5279
5280 wait_time = 256;
5281 do {
5282 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5283 qla2x00_configure_loop(vha);
5284 wait_time--;
5285 } while (!atomic_read(&vha->loop_down_timer) &&
5286 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
5287 wait_time &&
5288 (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
5289 }
5290
5291
5292 if ((vha->device_flags & DFLG_NO_CABLE))
5293 status = 0;
5294
5295 ql_log(ql_log_info, vha, 0x8000,
5296 "Configure loop done, status = 0x%x.\n", status);
5297 }
5298
5299 if (!status) {
5300 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
5301
5302 if (!atomic_read(&vha->loop_down_timer)) {
5303
5304
5305
5306
5307 vha->marker_needed = 1;
5308 }
5309
5310 vha->flags.online = 1;
5311
5312 ha->isp_ops->enable_intrs(ha);
5313
5314 ha->isp_abort_cnt = 0;
5315 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5316
5317
5318 status = qla82xx_check_md_needed(vha);
5319
5320 if (ha->fce) {
5321 ha->flags.fce_enabled = 1;
5322 memset(ha->fce, 0,
5323 fce_calc_size(ha->fce_bufs));
5324 rval = qla2x00_enable_fce_trace(vha,
5325 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5326 &ha->fce_bufs);
5327 if (rval) {
5328 ql_log(ql_log_warn, vha, 0x8001,
5329 "Unable to reinitialize FCE (%d).\n",
5330 rval);
5331 ha->flags.fce_enabled = 0;
5332 }
5333 }
5334
5335 if (ha->eft) {
5336 memset(ha->eft, 0, EFT_SIZE);
5337 rval = qla2x00_enable_eft_trace(vha,
5338 ha->eft_dma, EFT_NUM_BUFFERS);
5339 if (rval) {
5340 ql_log(ql_log_warn, vha, 0x8010,
5341 "Unable to reinitialize EFT (%d).\n",
5342 rval);
5343 }
5344 }
5345 }
5346
5347 if (!status) {
5348 ql_dbg(ql_dbg_taskm, vha, 0x8011,
5349 "qla82xx_restart_isp succeeded.\n");
5350
5351 spin_lock_irqsave(&ha->vport_slock, flags);
5352 list_for_each_entry(vp, &ha->vp_list, list) {
5353 if (vp->vp_idx) {
5354 atomic_inc(&vp->vref_count);
5355 spin_unlock_irqrestore(&ha->vport_slock, flags);
5356
5357 qla2x00_vp_abort_isp(vp);
5358
5359 spin_lock_irqsave(&ha->vport_slock, flags);
5360 atomic_dec(&vp->vref_count);
5361 }
5362 }
5363 spin_unlock_irqrestore(&ha->vport_slock, flags);
5364
5365 } else {
5366 ql_log(ql_log_warn, vha, 0x8016,
5367 "qla82xx_restart_isp **** FAILED ****.\n");
5368 }
5369
5370 return status;
5371}
5372
5373void
5374qla81xx_update_fw_options(scsi_qla_host_t *vha)
5375{
5376 struct qla_hw_data *ha = vha->hw;
5377
5378 if (!ql2xetsenable)
5379 return;
5380
5381
5382 memset(ha->fw_options, 0, sizeof(ha->fw_options));
5383 ha->fw_options[2] |= BIT_9;
5384 qla2x00_set_fw_options(vha, ha->fw_options);
5385}
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403
5404
5405static int
5406qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5407{
5408 int i, entries;
5409 uint8_t pid_match, wwn_match;
5410 int priority;
5411 uint32_t pid1, pid2;
5412 uint64_t wwn1, wwn2;
5413 struct qla_fcp_prio_entry *pri_entry;
5414 struct qla_hw_data *ha = vha->hw;
5415
5416 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
5417 return -1;
5418
5419 priority = -1;
5420 entries = ha->fcp_prio_cfg->num_entries;
5421 pri_entry = &ha->fcp_prio_cfg->entry[0];
5422
5423 for (i = 0; i < entries; i++) {
5424 pid_match = wwn_match = 0;
5425
5426 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
5427 pri_entry++;
5428 continue;
5429 }
5430
5431
5432 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
5433 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
5434 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
5435 if (pid1 == INVALID_PORT_ID)
5436 pid_match++;
5437 else if (pid1 == pid2)
5438 pid_match++;
5439 }
5440
5441
5442 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
5443 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
5444 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
5445 if (pid1 == INVALID_PORT_ID)
5446 pid_match++;
5447 else if (pid1 == pid2)
5448 pid_match++;
5449 }
5450
5451
5452 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
5453 wwn1 = wwn_to_u64(vha->port_name);
5454 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
5455 if (wwn2 == (uint64_t)-1)
5456 wwn_match++;
5457 else if (wwn1 == wwn2)
5458 wwn_match++;
5459 }
5460
5461
5462 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
5463 wwn1 = wwn_to_u64(fcport->port_name);
5464 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
5465 if (wwn2 == (uint64_t)-1)
5466 wwn_match++;
5467 else if (wwn1 == wwn2)
5468 wwn_match++;
5469 }
5470
5471 if (pid_match == 2 || wwn_match == 2) {
5472
5473 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
5474 priority = pri_entry->tag;
5475 break;
5476 }
5477
5478 pri_entry++;
5479 }
5480
5481 return priority;
5482}
5483
5484
5485
5486
5487
5488
5489
5490
5491
5492
5493
5494
5495
5496
5497
5498int
5499qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
5500{
5501 int ret;
5502 int priority;
5503 uint16_t mb[5];
5504
5505 if (fcport->port_type != FCT_TARGET ||
5506 fcport->loop_id == FC_NO_LOOP_ID)
5507 return QLA_FUNCTION_FAILED;
5508
5509 priority = qla24xx_get_fcp_prio(vha, fcport);
5510 if (priority < 0)
5511 return QLA_FUNCTION_FAILED;
5512
5513 if (IS_QLA82XX(vha->hw)) {
5514 fcport->fcp_prio = priority & 0xf;
5515 return QLA_SUCCESS;
5516 }
5517
5518 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
5519 if (ret == QLA_SUCCESS) {
5520 if (fcport->fcp_prio != priority)
5521 ql_dbg(ql_dbg_user, vha, 0x709e,
5522 "Updated FCP_CMND priority - value=%d loop_id=%d "
5523 "port_id=%02x%02x%02x.\n", priority,
5524 fcport->loop_id, fcport->d_id.b.domain,
5525 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5526 fcport->fcp_prio = priority & 0xf;
5527 } else
5528 ql_dbg(ql_dbg_user, vha, 0x704f,
5529 "Unable to update FCP_CMND priority - ret=0x%x for "
5530 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
5531 fcport->d_id.b.domain, fcport->d_id.b.area,
5532 fcport->d_id.b.al_pa);
5533 return ret;
5534}
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547
5548
5549int
5550qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
5551{
5552 int ret;
5553 fc_port_t *fcport;
5554
5555 ret = QLA_FUNCTION_FAILED;
5556
5557 list_for_each_entry(fcport, &vha->vp_fcports, list)
5558 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
5559
5560 return ret;
5561}
5562
