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11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/irq.h>
19#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/spi/spi.h>
24#include <linux/workqueue.h>
25
26#include <asm/dma.h>
27#include <asm/portmux.h>
28#include <asm/bfin5xx_spi.h>
29#include <asm/cacheflush.h>
30
31#define DRV_NAME "bfin-spi"
32#define DRV_AUTHOR "Bryan Wu, Luke Yang"
33#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34#define DRV_VERSION "1.0"
35
36MODULE_AUTHOR(DRV_AUTHOR);
37MODULE_DESCRIPTION(DRV_DESC);
38MODULE_LICENSE("GPL");
39
40#define START_STATE ((void *)0)
41#define RUNNING_STATE ((void *)1)
42#define DONE_STATE ((void *)2)
43#define ERROR_STATE ((void *)-1)
44
45struct bfin_spi_master_data;
46
47struct bfin_spi_transfer_ops {
48 void (*write) (struct bfin_spi_master_data *);
49 void (*read) (struct bfin_spi_master_data *);
50 void (*duplex) (struct bfin_spi_master_data *);
51};
52
53struct bfin_spi_master_data {
54
55 struct platform_device *pdev;
56
57
58 struct spi_master *master;
59
60
61 struct bfin_spi_regs __iomem *regs;
62
63
64 u16 *pin_req;
65
66
67 struct bfin5xx_spi_master *master_info;
68
69
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
72 spinlock_t lock;
73 struct list_head queue;
74 int busy;
75 bool running;
76
77
78 struct tasklet_struct pump_transfers;
79
80
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct bfin_spi_slave_data *cur_chip;
84 size_t len_in_bytes;
85 size_t len;
86 void *tx;
87 void *tx_end;
88 void *rx;
89 void *rx_end;
90
91
92 int dma_channel;
93 int dma_mapped;
94 int dma_requested;
95 dma_addr_t rx_dma;
96 dma_addr_t tx_dma;
97
98 int irq_requested;
99 int spi_irq;
100
101 size_t rx_map_len;
102 size_t tx_map_len;
103 u8 n_bytes;
104 u16 ctrl_reg;
105 u16 flag_reg;
106
107 int cs_change;
108 const struct bfin_spi_transfer_ops *ops;
109};
110
111struct bfin_spi_slave_data {
112 u16 ctl_reg;
113 u16 baud;
114 u16 flag;
115
116 u8 chip_select_num;
117 u8 enable_dma;
118 u16 cs_chg_udelay;
119 u32 cs_gpio;
120 u16 idle_tx_val;
121 u8 pio_interrupt;
122 const struct bfin_spi_transfer_ops *ops;
123};
124
125static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
126{
127 bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
128}
129
130static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
131{
132 bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
133}
134
135
136static u16 hz_to_spi_baud(u32 speed_hz)
137{
138 u_long sclk = get_sclk();
139 u16 spi_baud = (sclk / (2 * speed_hz));
140
141 if ((sclk % (2 * speed_hz)) > 0)
142 spi_baud++;
143
144 if (spi_baud < MIN_SPI_BAUD_VAL)
145 spi_baud = MIN_SPI_BAUD_VAL;
146
147 return spi_baud;
148}
149
150static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
151{
152 unsigned long limit = loops_per_jiffy << 1;
153
154
155 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
156 cpu_relax();
157
158 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
159
160 return limit;
161}
162
163
164static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
165{
166 if (likely(chip->chip_select_num < MAX_CTRL_CS))
167 bfin_write_and(&drv_data->regs->flg, ~chip->flag);
168 else
169 gpio_set_value(chip->cs_gpio, 0);
170}
171
172static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
173 struct bfin_spi_slave_data *chip)
174{
175 if (likely(chip->chip_select_num < MAX_CTRL_CS))
176 bfin_write_or(&drv_data->regs->flg, chip->flag);
177 else
178 gpio_set_value(chip->cs_gpio, 1);
179
180
181 if (chip->cs_chg_udelay)
182 udelay(chip->cs_chg_udelay);
183}
184
185
186static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
187 struct bfin_spi_slave_data *chip)
188{
189 if (chip->chip_select_num < MAX_CTRL_CS)
190 bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
191}
192
193static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
194 struct bfin_spi_slave_data *chip)
195{
196 if (chip->chip_select_num < MAX_CTRL_CS)
197 bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
198}
199
200
201static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
202{
203 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
204
205
206 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
207 bfin_spi_disable(drv_data);
208 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
209
210 SSYNC();
211
212
213 bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
214 bfin_write(&drv_data->regs->baud, chip->baud);
215
216 bfin_spi_enable(drv_data);
217 bfin_spi_cs_active(drv_data, chip);
218}
219
220
221static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
222{
223 (void) bfin_read(&drv_data->regs->rdbr);
224}
225
226static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
227{
228
229 bfin_spi_dummy_read(drv_data);
230
231 while (drv_data->tx < drv_data->tx_end) {
232 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
233
234
235 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
236 cpu_relax();
237
238 bfin_spi_dummy_read(drv_data);
239 }
240}
241
242static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
243{
244 u16 tx_val = drv_data->cur_chip->idle_tx_val;
245
246
247 bfin_spi_dummy_read(drv_data);
248
249 while (drv_data->rx < drv_data->rx_end) {
250 bfin_write(&drv_data->regs->tdbr, tx_val);
251 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
252 cpu_relax();
253 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
254 }
255}
256
257static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
258{
259
260 bfin_spi_dummy_read(drv_data);
261
262 while (drv_data->rx < drv_data->rx_end) {
263 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
264 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
265 cpu_relax();
266 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
267 }
268}
269
270static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
271 .write = bfin_spi_u8_writer,
272 .read = bfin_spi_u8_reader,
273 .duplex = bfin_spi_u8_duplex,
274};
275
276static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
277{
278
279 bfin_spi_dummy_read(drv_data);
280
281 while (drv_data->tx < drv_data->tx_end) {
282 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
283 drv_data->tx += 2;
284
285
286 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
287 cpu_relax();
288
289 bfin_spi_dummy_read(drv_data);
290 }
291}
292
293static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
294{
295 u16 tx_val = drv_data->cur_chip->idle_tx_val;
296
297
298 bfin_spi_dummy_read(drv_data);
299
300 while (drv_data->rx < drv_data->rx_end) {
301 bfin_write(&drv_data->regs->tdbr, tx_val);
302 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
303 cpu_relax();
304 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
305 drv_data->rx += 2;
306 }
307}
308
309static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
310{
311
312 bfin_spi_dummy_read(drv_data);
313
314 while (drv_data->rx < drv_data->rx_end) {
315 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
316 drv_data->tx += 2;
317 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
318 cpu_relax();
319 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
320 drv_data->rx += 2;
321 }
322}
323
324static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
325 .write = bfin_spi_u16_writer,
326 .read = bfin_spi_u16_reader,
327 .duplex = bfin_spi_u16_duplex,
328};
329
330
331static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
332{
333 struct spi_message *msg = drv_data->cur_msg;
334 struct spi_transfer *trans = drv_data->cur_transfer;
335
336
337 if (trans->transfer_list.next != &msg->transfers) {
338 drv_data->cur_transfer =
339 list_entry(trans->transfer_list.next,
340 struct spi_transfer, transfer_list);
341 return RUNNING_STATE;
342 } else
343 return DONE_STATE;
344}
345
346
347
348
349
350static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
351{
352 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
353 struct spi_transfer *last_transfer;
354 unsigned long flags;
355 struct spi_message *msg;
356
357 spin_lock_irqsave(&drv_data->lock, flags);
358 msg = drv_data->cur_msg;
359 drv_data->cur_msg = NULL;
360 drv_data->cur_transfer = NULL;
361 drv_data->cur_chip = NULL;
362 queue_work(drv_data->workqueue, &drv_data->pump_messages);
363 spin_unlock_irqrestore(&drv_data->lock, flags);
364
365 last_transfer = list_entry(msg->transfers.prev,
366 struct spi_transfer, transfer_list);
367
368 msg->state = NULL;
369
370 if (!drv_data->cs_change)
371 bfin_spi_cs_deactive(drv_data, chip);
372
373
374 if (drv_data->tx_dma != 0xFFFF)
375 bfin_spi_disable(drv_data);
376
377 if (msg->complete)
378 msg->complete(msg->context);
379}
380
381
382static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
383{
384 struct bfin_spi_master_data *drv_data = dev_id;
385 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
386 struct spi_message *msg = drv_data->cur_msg;
387 int n_bytes = drv_data->n_bytes;
388 int loop = 0;
389
390
391 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
392 cpu_relax();
393
394 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
395 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
396
397 if (drv_data->rx) {
398 dev_dbg(&drv_data->pdev->dev, "last read\n");
399 if (!(n_bytes % 2)) {
400 u16 *buf = (u16 *)drv_data->rx;
401 for (loop = 0; loop < n_bytes / 2; loop++)
402 *buf++ = bfin_read(&drv_data->regs->rdbr);
403 } else {
404 u8 *buf = (u8 *)drv_data->rx;
405 for (loop = 0; loop < n_bytes; loop++)
406 *buf++ = bfin_read(&drv_data->regs->rdbr);
407 }
408 drv_data->rx += n_bytes;
409 }
410
411 msg->actual_length += drv_data->len_in_bytes;
412 if (drv_data->cs_change)
413 bfin_spi_cs_deactive(drv_data, chip);
414
415 msg->state = bfin_spi_next_transfer(drv_data);
416
417 disable_irq_nosync(drv_data->spi_irq);
418
419
420 tasklet_schedule(&drv_data->pump_transfers);
421 return IRQ_HANDLED;
422 }
423
424 if (drv_data->rx && drv_data->tx) {
425
426 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
427 if (!(n_bytes % 2)) {
428 u16 *buf = (u16 *)drv_data->rx;
429 u16 *buf2 = (u16 *)drv_data->tx;
430 for (loop = 0; loop < n_bytes / 2; loop++) {
431 *buf++ = bfin_read(&drv_data->regs->rdbr);
432 bfin_write(&drv_data->regs->tdbr, *buf2++);
433 }
434 } else {
435 u8 *buf = (u8 *)drv_data->rx;
436 u8 *buf2 = (u8 *)drv_data->tx;
437 for (loop = 0; loop < n_bytes; loop++) {
438 *buf++ = bfin_read(&drv_data->regs->rdbr);
439 bfin_write(&drv_data->regs->tdbr, *buf2++);
440 }
441 }
442 } else if (drv_data->rx) {
443
444 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
445 if (!(n_bytes % 2)) {
446 u16 *buf = (u16 *)drv_data->rx;
447 for (loop = 0; loop < n_bytes / 2; loop++) {
448 *buf++ = bfin_read(&drv_data->regs->rdbr);
449 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
450 }
451 } else {
452 u8 *buf = (u8 *)drv_data->rx;
453 for (loop = 0; loop < n_bytes; loop++) {
454 *buf++ = bfin_read(&drv_data->regs->rdbr);
455 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
456 }
457 }
458 } else if (drv_data->tx) {
459
460 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
461 if (!(n_bytes % 2)) {
462 u16 *buf = (u16 *)drv_data->tx;
463 for (loop = 0; loop < n_bytes / 2; loop++) {
464 bfin_read(&drv_data->regs->rdbr);
465 bfin_write(&drv_data->regs->tdbr, *buf++);
466 }
467 } else {
468 u8 *buf = (u8 *)drv_data->tx;
469 for (loop = 0; loop < n_bytes; loop++) {
470 bfin_read(&drv_data->regs->rdbr);
471 bfin_write(&drv_data->regs->tdbr, *buf++);
472 }
473 }
474 }
475
476 if (drv_data->tx)
477 drv_data->tx += n_bytes;
478 if (drv_data->rx)
479 drv_data->rx += n_bytes;
480
481 return IRQ_HANDLED;
482}
483
484static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
485{
486 struct bfin_spi_master_data *drv_data = dev_id;
487 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
488 struct spi_message *msg = drv_data->cur_msg;
489 unsigned long timeout;
490 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
491 u16 spistat = bfin_read(&drv_data->regs->stat);
492
493 dev_dbg(&drv_data->pdev->dev,
494 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
495 dmastat, spistat);
496
497 if (drv_data->rx != NULL) {
498 u16 cr = bfin_read(&drv_data->regs->ctl);
499
500 bfin_spi_dummy_read(drv_data);
501 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE);
502 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD);
503 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
504 }
505
506 clear_dma_irqstat(drv_data->dma_channel);
507
508
509
510
511
512
513
514 if (drv_data->tx != NULL) {
515 while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
516 (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
517 cpu_relax();
518 }
519
520 dev_dbg(&drv_data->pdev->dev,
521 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
522 dmastat, bfin_read(&drv_data->regs->stat));
523
524 timeout = jiffies + HZ;
525 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
526 if (!time_before(jiffies, timeout)) {
527 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
528 break;
529 } else
530 cpu_relax();
531
532 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
533 msg->state = ERROR_STATE;
534 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
535 } else {
536 msg->actual_length += drv_data->len_in_bytes;
537
538 if (drv_data->cs_change)
539 bfin_spi_cs_deactive(drv_data, chip);
540
541
542 msg->state = bfin_spi_next_transfer(drv_data);
543 }
544
545
546 tasklet_schedule(&drv_data->pump_transfers);
547
548
549 dev_dbg(&drv_data->pdev->dev,
550 "disable dma channel irq%d\n",
551 drv_data->dma_channel);
552 dma_disable_irq_nosync(drv_data->dma_channel);
553
554 return IRQ_HANDLED;
555}
556
557static void bfin_spi_pump_transfers(unsigned long data)
558{
559 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
560 struct spi_message *message = NULL;
561 struct spi_transfer *transfer = NULL;
562 struct spi_transfer *previous = NULL;
563 struct bfin_spi_slave_data *chip = NULL;
564 unsigned int bits_per_word;
565 u16 cr, cr_width, dma_width, dma_config;
566 u32 tranf_success = 1;
567 u8 full_duplex = 0;
568
569
570 message = drv_data->cur_msg;
571 transfer = drv_data->cur_transfer;
572 chip = drv_data->cur_chip;
573
574
575
576
577
578
579 if (message->state == ERROR_STATE) {
580 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
581 message->status = -EIO;
582 bfin_spi_giveback(drv_data);
583 return;
584 }
585
586
587 if (message->state == DONE_STATE) {
588 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
589 message->status = 0;
590 bfin_spi_flush(drv_data);
591 bfin_spi_giveback(drv_data);
592 return;
593 }
594
595
596 if (message->state == RUNNING_STATE) {
597 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
598 previous = list_entry(transfer->transfer_list.prev,
599 struct spi_transfer, transfer_list);
600 if (previous->delay_usecs)
601 udelay(previous->delay_usecs);
602 }
603
604
605 if (bfin_spi_flush(drv_data) == 0) {
606 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
607 message->status = -EIO;
608 bfin_spi_giveback(drv_data);
609 return;
610 }
611
612 if (transfer->len == 0) {
613
614 message->state = bfin_spi_next_transfer(drv_data);
615
616 tasklet_schedule(&drv_data->pump_transfers);
617 return;
618 }
619
620 if (transfer->tx_buf != NULL) {
621 drv_data->tx = (void *)transfer->tx_buf;
622 drv_data->tx_end = drv_data->tx + transfer->len;
623 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
624 transfer->tx_buf, drv_data->tx_end);
625 } else {
626 drv_data->tx = NULL;
627 }
628
629 if (transfer->rx_buf != NULL) {
630 full_duplex = transfer->tx_buf != NULL;
631 drv_data->rx = transfer->rx_buf;
632 drv_data->rx_end = drv_data->rx + transfer->len;
633 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
634 transfer->rx_buf, drv_data->rx_end);
635 } else {
636 drv_data->rx = NULL;
637 }
638
639 drv_data->rx_dma = transfer->rx_dma;
640 drv_data->tx_dma = transfer->tx_dma;
641 drv_data->len_in_bytes = transfer->len;
642 drv_data->cs_change = transfer->cs_change;
643
644
645 bits_per_word = transfer->bits_per_word ? :
646 message->spi->bits_per_word ? : 8;
647 if (bits_per_word % 16 == 0) {
648 drv_data->n_bytes = bits_per_word/8;
649 drv_data->len = (transfer->len) >> 1;
650 cr_width = BIT_CTL_WORDSIZE;
651 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
652 } else if (bits_per_word % 8 == 0) {
653 drv_data->n_bytes = bits_per_word/8;
654 drv_data->len = transfer->len;
655 cr_width = 0;
656 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
657 } else {
658 dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n");
659 message->status = -EINVAL;
660 bfin_spi_giveback(drv_data);
661 return;
662 }
663 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
664 cr |= cr_width;
665 bfin_write(&drv_data->regs->ctl, cr);
666
667 dev_dbg(&drv_data->pdev->dev,
668 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
669 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
670
671 message->state = RUNNING_STATE;
672 dma_config = 0;
673
674
675 if (transfer->speed_hz)
676 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
677 else
678 bfin_write(&drv_data->regs->baud, chip->baud);
679
680 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
681 bfin_spi_cs_active(drv_data, chip);
682
683 dev_dbg(&drv_data->pdev->dev,
684 "now pumping a transfer: width is %d, len is %d\n",
685 cr_width, transfer->len);
686
687
688
689
690
691
692
693 if (!full_duplex && drv_data->cur_chip->enable_dma
694 && drv_data->len > 6) {
695
696 unsigned long dma_start_addr, flags;
697
698 disable_dma(drv_data->dma_channel);
699 clear_dma_irqstat(drv_data->dma_channel);
700
701
702 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
703 set_dma_x_count(drv_data->dma_channel, drv_data->len);
704 if (cr_width == BIT_CTL_WORDSIZE) {
705 set_dma_x_modify(drv_data->dma_channel, 2);
706 dma_width = WDSIZE_16;
707 } else {
708 set_dma_x_modify(drv_data->dma_channel, 1);
709 dma_width = WDSIZE_8;
710 }
711
712
713 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
714 cpu_relax();
715
716
717 if (drv_data->tx_dma == 0xFFFF) {
718 dev_dbg(&drv_data->pdev->dev,
719 "doing autobuffer DMA out.\n");
720
721
722 dma_config =
723 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
724 set_dma_config(drv_data->dma_channel, dma_config);
725 set_dma_start_addr(drv_data->dma_channel,
726 (unsigned long)drv_data->tx);
727 enable_dma(drv_data->dma_channel);
728
729
730 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
731
732
733
734
735 message->status = 0;
736 bfin_spi_giveback(drv_data);
737 return;
738 }
739
740
741 dma_config = (RESTART | dma_width | DI_EN);
742 if (drv_data->rx != NULL) {
743
744 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
745 drv_data->rx, drv_data->len_in_bytes);
746
747
748 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
749 invalidate_dcache_range((unsigned long) drv_data->rx,
750 (unsigned long) (drv_data->rx +
751 drv_data->len_in_bytes));
752
753 dma_config |= WNR;
754 dma_start_addr = (unsigned long)drv_data->rx;
755 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
756
757 } else if (drv_data->tx != NULL) {
758 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
759
760
761 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
762 flush_dcache_range((unsigned long) drv_data->tx,
763 (unsigned long) (drv_data->tx +
764 drv_data->len_in_bytes));
765
766 dma_start_addr = (unsigned long)drv_data->tx;
767 cr |= BIT_CTL_TIMOD_DMA_TX;
768
769 } else
770 BUG();
771
772
773
774
775
776
777
778
779
780
781 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
782 set_dma_config(drv_data->dma_channel, dma_config);
783 local_irq_save(flags);
784 SSYNC();
785 bfin_write(&drv_data->regs->ctl, cr);
786 enable_dma(drv_data->dma_channel);
787 dma_enable_irq(drv_data->dma_channel);
788 local_irq_restore(flags);
789
790 return;
791 }
792
793
794
795
796
797
798
799 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
800
801 if (chip->pio_interrupt) {
802
803
804
805 bfin_spi_dummy_read(drv_data);
806
807
808 if (drv_data->tx == NULL)
809 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
810 else {
811 int loop;
812 if (bits_per_word % 16 == 0) {
813 u16 *buf = (u16 *)drv_data->tx;
814 for (loop = 0; loop < bits_per_word / 16;
815 loop++) {
816 bfin_write(&drv_data->regs->tdbr, *buf++);
817 }
818 } else if (bits_per_word % 8 == 0) {
819 u8 *buf = (u8 *)drv_data->tx;
820 for (loop = 0; loop < bits_per_word / 8; loop++)
821 bfin_write(&drv_data->regs->tdbr, *buf++);
822 }
823
824 drv_data->tx += drv_data->n_bytes;
825 }
826
827
828 enable_irq(drv_data->spi_irq);
829 return;
830 }
831
832
833 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
834
835 if (full_duplex) {
836
837 BUG_ON((drv_data->tx_end - drv_data->tx) !=
838 (drv_data->rx_end - drv_data->rx));
839 dev_dbg(&drv_data->pdev->dev,
840 "IO duplex: cr is 0x%x\n", cr);
841
842 drv_data->ops->duplex(drv_data);
843
844 if (drv_data->tx != drv_data->tx_end)
845 tranf_success = 0;
846 } else if (drv_data->tx != NULL) {
847
848 dev_dbg(&drv_data->pdev->dev,
849 "IO write: cr is 0x%x\n", cr);
850
851 drv_data->ops->write(drv_data);
852
853 if (drv_data->tx != drv_data->tx_end)
854 tranf_success = 0;
855 } else if (drv_data->rx != NULL) {
856
857 dev_dbg(&drv_data->pdev->dev,
858 "IO read: cr is 0x%x\n", cr);
859
860 drv_data->ops->read(drv_data);
861 if (drv_data->rx != drv_data->rx_end)
862 tranf_success = 0;
863 }
864
865 if (!tranf_success) {
866 dev_dbg(&drv_data->pdev->dev,
867 "IO write error!\n");
868 message->state = ERROR_STATE;
869 } else {
870
871 message->actual_length += drv_data->len_in_bytes;
872
873 message->state = bfin_spi_next_transfer(drv_data);
874 if (drv_data->cs_change && message->state != DONE_STATE) {
875 bfin_spi_flush(drv_data);
876 bfin_spi_cs_deactive(drv_data, chip);
877 }
878 }
879
880
881 tasklet_schedule(&drv_data->pump_transfers);
882}
883
884
885static void bfin_spi_pump_messages(struct work_struct *work)
886{
887 struct bfin_spi_master_data *drv_data;
888 unsigned long flags;
889
890 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
891
892
893 spin_lock_irqsave(&drv_data->lock, flags);
894 if (list_empty(&drv_data->queue) || !drv_data->running) {
895
896 drv_data->busy = 0;
897 spin_unlock_irqrestore(&drv_data->lock, flags);
898 return;
899 }
900
901
902 if (drv_data->cur_msg) {
903 spin_unlock_irqrestore(&drv_data->lock, flags);
904 return;
905 }
906
907
908 drv_data->cur_msg = list_entry(drv_data->queue.next,
909 struct spi_message, queue);
910
911
912 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
913 bfin_spi_restore_state(drv_data);
914
915 list_del_init(&drv_data->cur_msg->queue);
916
917
918 drv_data->cur_msg->state = START_STATE;
919 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
920 struct spi_transfer, transfer_list);
921
922 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
923 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
924 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
925 drv_data->cur_chip->ctl_reg);
926
927 dev_dbg(&drv_data->pdev->dev,
928 "the first transfer len is %d\n",
929 drv_data->cur_transfer->len);
930
931
932 tasklet_schedule(&drv_data->pump_transfers);
933
934 drv_data->busy = 1;
935 spin_unlock_irqrestore(&drv_data->lock, flags);
936}
937
938
939
940
941
942static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
943{
944 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
945 unsigned long flags;
946
947 spin_lock_irqsave(&drv_data->lock, flags);
948
949 if (!drv_data->running) {
950 spin_unlock_irqrestore(&drv_data->lock, flags);
951 return -ESHUTDOWN;
952 }
953
954 msg->actual_length = 0;
955 msg->status = -EINPROGRESS;
956 msg->state = START_STATE;
957
958 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
959 list_add_tail(&msg->queue, &drv_data->queue);
960
961 if (drv_data->running && !drv_data->busy)
962 queue_work(drv_data->workqueue, &drv_data->pump_messages);
963
964 spin_unlock_irqrestore(&drv_data->lock, flags);
965
966 return 0;
967}
968
969#define MAX_SPI_SSEL 7
970
971static const u16 ssel[][MAX_SPI_SSEL] = {
972 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
973 P_SPI0_SSEL4, P_SPI0_SSEL5,
974 P_SPI0_SSEL6, P_SPI0_SSEL7},
975
976 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
977 P_SPI1_SSEL4, P_SPI1_SSEL5,
978 P_SPI1_SSEL6, P_SPI1_SSEL7},
979
980 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
981 P_SPI2_SSEL4, P_SPI2_SSEL5,
982 P_SPI2_SSEL6, P_SPI2_SSEL7},
983};
984
985
986static int bfin_spi_setup(struct spi_device *spi)
987{
988 struct bfin5xx_spi_chip *chip_info;
989 struct bfin_spi_slave_data *chip = NULL;
990 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
991 u16 bfin_ctl_reg;
992 int ret = -EINVAL;
993
994
995 chip_info = NULL;
996 chip = spi_get_ctldata(spi);
997 if (chip == NULL) {
998 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
999 if (!chip) {
1000 dev_err(&spi->dev, "cannot allocate chip data\n");
1001 ret = -ENOMEM;
1002 goto error;
1003 }
1004
1005 chip->enable_dma = 0;
1006 chip_info = spi->controller_data;
1007 }
1008
1009
1010 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1011 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1012
1013
1014 if (chip_info) {
1015
1016
1017
1018
1019
1020
1021 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1022 dev_err(&spi->dev, "do not set bits in ctl_reg "
1023 "that the SPI framework manages\n");
1024 goto error;
1025 }
1026 chip->enable_dma = chip_info->enable_dma != 0
1027 && drv_data->master_info->enable_dma;
1028 chip->ctl_reg = chip_info->ctl_reg;
1029 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1030 chip->idle_tx_val = chip_info->idle_tx_val;
1031 chip->pio_interrupt = chip_info->pio_interrupt;
1032 } else {
1033
1034 chip->ctl_reg &= bfin_ctl_reg;
1035 }
1036
1037 if (spi->bits_per_word % 8) {
1038 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1039 spi->bits_per_word);
1040 goto error;
1041 }
1042
1043
1044 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1045 dev_err(&spi->dev, "unsupported spi modes detected\n");
1046 goto error;
1047 }
1048 if (spi->mode & SPI_CPOL)
1049 chip->ctl_reg |= BIT_CTL_CPOL;
1050 if (spi->mode & SPI_CPHA)
1051 chip->ctl_reg |= BIT_CTL_CPHA;
1052 if (spi->mode & SPI_LSB_FIRST)
1053 chip->ctl_reg |= BIT_CTL_LSBF;
1054
1055 chip->ctl_reg |= BIT_CTL_MASTER;
1056
1057
1058
1059
1060
1061 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1062 chip->chip_select_num = spi->chip_select;
1063 if (chip->chip_select_num < MAX_CTRL_CS) {
1064 if (!(spi->mode & SPI_CPHA))
1065 dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1066 " Slave Select not under software control!\n"
1067 " See Documentation/blackfin/bfin-spi-notes.txt");
1068
1069 chip->flag = (1 << spi->chip_select) << 8;
1070 } else
1071 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1072
1073 if (chip->enable_dma && chip->pio_interrupt) {
1074 dev_err(&spi->dev, "enable_dma is set, "
1075 "do not set pio_interrupt\n");
1076 goto error;
1077 }
1078
1079
1080
1081
1082 if (chip->enable_dma && !drv_data->dma_requested) {
1083
1084 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1085 if (ret) {
1086 dev_err(&spi->dev,
1087 "Unable to request BlackFin SPI DMA channel\n");
1088 goto error;
1089 }
1090 drv_data->dma_requested = 1;
1091
1092 ret = set_dma_callback(drv_data->dma_channel,
1093 bfin_spi_dma_irq_handler, drv_data);
1094 if (ret) {
1095 dev_err(&spi->dev, "Unable to set dma callback\n");
1096 goto error;
1097 }
1098 dma_disable_irq(drv_data->dma_channel);
1099 }
1100
1101 if (chip->pio_interrupt && !drv_data->irq_requested) {
1102 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1103 0, "BFIN_SPI", drv_data);
1104 if (ret) {
1105 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1106 goto error;
1107 }
1108 drv_data->irq_requested = 1;
1109
1110 disable_irq(drv_data->spi_irq);
1111 }
1112
1113 if (chip->chip_select_num >= MAX_CTRL_CS) {
1114
1115 if (spi_get_ctldata(spi) == NULL) {
1116 ret = gpio_request(chip->cs_gpio, spi->modalias);
1117 if (ret) {
1118 dev_err(&spi->dev, "gpio_request() error\n");
1119 goto pin_error;
1120 }
1121 gpio_direction_output(chip->cs_gpio, 1);
1122 }
1123 }
1124
1125 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1126 spi->modalias, spi->bits_per_word, chip->enable_dma);
1127 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1128 chip->ctl_reg, chip->flag);
1129
1130 spi_set_ctldata(spi, chip);
1131
1132 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1133 if (chip->chip_select_num < MAX_CTRL_CS) {
1134 ret = peripheral_request(ssel[spi->master->bus_num]
1135 [chip->chip_select_num-1], spi->modalias);
1136 if (ret) {
1137 dev_err(&spi->dev, "peripheral_request() error\n");
1138 goto pin_error;
1139 }
1140 }
1141
1142 bfin_spi_cs_enable(drv_data, chip);
1143 bfin_spi_cs_deactive(drv_data, chip);
1144
1145 return 0;
1146
1147 pin_error:
1148 if (chip->chip_select_num >= MAX_CTRL_CS)
1149 gpio_free(chip->cs_gpio);
1150 else
1151 peripheral_free(ssel[spi->master->bus_num]
1152 [chip->chip_select_num - 1]);
1153 error:
1154 if (chip) {
1155 if (drv_data->dma_requested)
1156 free_dma(drv_data->dma_channel);
1157 drv_data->dma_requested = 0;
1158
1159 kfree(chip);
1160
1161 spi_set_ctldata(spi, NULL);
1162 }
1163
1164 return ret;
1165}
1166
1167
1168
1169
1170
1171static void bfin_spi_cleanup(struct spi_device *spi)
1172{
1173 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1174 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1175
1176 if (!chip)
1177 return;
1178
1179 if (chip->chip_select_num < MAX_CTRL_CS) {
1180 peripheral_free(ssel[spi->master->bus_num]
1181 [chip->chip_select_num-1]);
1182 bfin_spi_cs_disable(drv_data, chip);
1183 } else
1184 gpio_free(chip->cs_gpio);
1185
1186 kfree(chip);
1187
1188 spi_set_ctldata(spi, NULL);
1189}
1190
1191static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1192{
1193 INIT_LIST_HEAD(&drv_data->queue);
1194 spin_lock_init(&drv_data->lock);
1195
1196 drv_data->running = false;
1197 drv_data->busy = 0;
1198
1199
1200 tasklet_init(&drv_data->pump_transfers,
1201 bfin_spi_pump_transfers, (unsigned long)drv_data);
1202
1203
1204 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1205 drv_data->workqueue = create_singlethread_workqueue(
1206 dev_name(drv_data->master->dev.parent));
1207 if (drv_data->workqueue == NULL)
1208 return -EBUSY;
1209
1210 return 0;
1211}
1212
1213static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1214{
1215 unsigned long flags;
1216
1217 spin_lock_irqsave(&drv_data->lock, flags);
1218
1219 if (drv_data->running || drv_data->busy) {
1220 spin_unlock_irqrestore(&drv_data->lock, flags);
1221 return -EBUSY;
1222 }
1223
1224 drv_data->running = true;
1225 drv_data->cur_msg = NULL;
1226 drv_data->cur_transfer = NULL;
1227 drv_data->cur_chip = NULL;
1228 spin_unlock_irqrestore(&drv_data->lock, flags);
1229
1230 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1231
1232 return 0;
1233}
1234
1235static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1236{
1237 unsigned long flags;
1238 unsigned limit = 500;
1239 int status = 0;
1240
1241 spin_lock_irqsave(&drv_data->lock, flags);
1242
1243
1244
1245
1246
1247
1248
1249 drv_data->running = false;
1250 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1251 spin_unlock_irqrestore(&drv_data->lock, flags);
1252 msleep(10);
1253 spin_lock_irqsave(&drv_data->lock, flags);
1254 }
1255
1256 if (!list_empty(&drv_data->queue) || drv_data->busy)
1257 status = -EBUSY;
1258
1259 spin_unlock_irqrestore(&drv_data->lock, flags);
1260
1261 return status;
1262}
1263
1264static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1265{
1266 int status;
1267
1268 status = bfin_spi_stop_queue(drv_data);
1269 if (status != 0)
1270 return status;
1271
1272 destroy_workqueue(drv_data->workqueue);
1273
1274 return 0;
1275}
1276
1277static int __init bfin_spi_probe(struct platform_device *pdev)
1278{
1279 struct device *dev = &pdev->dev;
1280 struct bfin5xx_spi_master *platform_info;
1281 struct spi_master *master;
1282 struct bfin_spi_master_data *drv_data;
1283 struct resource *res;
1284 int status = 0;
1285
1286 platform_info = dev->platform_data;
1287
1288
1289 master = spi_alloc_master(dev, sizeof(*drv_data));
1290 if (!master) {
1291 dev_err(&pdev->dev, "can not alloc spi_master\n");
1292 return -ENOMEM;
1293 }
1294
1295 drv_data = spi_master_get_devdata(master);
1296 drv_data->master = master;
1297 drv_data->master_info = platform_info;
1298 drv_data->pdev = pdev;
1299 drv_data->pin_req = platform_info->pin_req;
1300
1301
1302 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1303
1304 master->bus_num = pdev->id;
1305 master->num_chipselect = platform_info->num_chipselect;
1306 master->cleanup = bfin_spi_cleanup;
1307 master->setup = bfin_spi_setup;
1308 master->transfer = bfin_spi_transfer;
1309
1310
1311 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1312 if (res == NULL) {
1313 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1314 status = -ENOENT;
1315 goto out_error_get_res;
1316 }
1317
1318 drv_data->regs = ioremap(res->start, resource_size(res));
1319 if (drv_data->regs == NULL) {
1320 dev_err(dev, "Cannot map IO\n");
1321 status = -ENXIO;
1322 goto out_error_ioremap;
1323 }
1324
1325 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1326 if (res == NULL) {
1327 dev_err(dev, "No DMA channel specified\n");
1328 status = -ENOENT;
1329 goto out_error_free_io;
1330 }
1331 drv_data->dma_channel = res->start;
1332
1333 drv_data->spi_irq = platform_get_irq(pdev, 0);
1334 if (drv_data->spi_irq < 0) {
1335 dev_err(dev, "No spi pio irq specified\n");
1336 status = -ENOENT;
1337 goto out_error_free_io;
1338 }
1339
1340
1341 status = bfin_spi_init_queue(drv_data);
1342 if (status != 0) {
1343 dev_err(dev, "problem initializing queue\n");
1344 goto out_error_queue_alloc;
1345 }
1346
1347 status = bfin_spi_start_queue(drv_data);
1348 if (status != 0) {
1349 dev_err(dev, "problem starting queue\n");
1350 goto out_error_queue_alloc;
1351 }
1352
1353 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1354 if (status != 0) {
1355 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1356 goto out_error_queue_alloc;
1357 }
1358
1359
1360
1361
1362 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1363 bfin_write(&drv_data->regs->flg, 0xFF00);
1364
1365
1366 platform_set_drvdata(pdev, drv_data);
1367 status = spi_register_master(master);
1368 if (status != 0) {
1369 dev_err(dev, "problem registering spi master\n");
1370 goto out_error_queue_alloc;
1371 }
1372
1373 dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1374 DRV_DESC, DRV_VERSION, drv_data->regs,
1375 drv_data->dma_channel);
1376 return status;
1377
1378out_error_queue_alloc:
1379 bfin_spi_destroy_queue(drv_data);
1380out_error_free_io:
1381 iounmap(drv_data->regs);
1382out_error_ioremap:
1383out_error_get_res:
1384 spi_master_put(master);
1385
1386 return status;
1387}
1388
1389
1390static int __devexit bfin_spi_remove(struct platform_device *pdev)
1391{
1392 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1393 int status = 0;
1394
1395 if (!drv_data)
1396 return 0;
1397
1398
1399 status = bfin_spi_destroy_queue(drv_data);
1400 if (status != 0)
1401 return status;
1402
1403
1404 bfin_spi_disable(drv_data);
1405
1406
1407 if (drv_data->master_info->enable_dma) {
1408 if (dma_channel_active(drv_data->dma_channel))
1409 free_dma(drv_data->dma_channel);
1410 }
1411
1412 if (drv_data->irq_requested) {
1413 free_irq(drv_data->spi_irq, drv_data);
1414 drv_data->irq_requested = 0;
1415 }
1416
1417
1418 spi_unregister_master(drv_data->master);
1419
1420 peripheral_free_list(drv_data->pin_req);
1421
1422
1423 platform_set_drvdata(pdev, NULL);
1424
1425 return 0;
1426}
1427
1428#ifdef CONFIG_PM
1429static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1430{
1431 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1432 int status = 0;
1433
1434 status = bfin_spi_stop_queue(drv_data);
1435 if (status != 0)
1436 return status;
1437
1438 drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1439 drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
1440
1441
1442
1443
1444 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1445 bfin_write(&drv_data->regs->flg, 0xFF00);
1446
1447 return 0;
1448}
1449
1450static int bfin_spi_resume(struct platform_device *pdev)
1451{
1452 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1453 int status = 0;
1454
1455 bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1456 bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
1457
1458
1459 status = bfin_spi_start_queue(drv_data);
1460 if (status != 0) {
1461 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1462 return status;
1463 }
1464
1465 return 0;
1466}
1467#else
1468#define bfin_spi_suspend NULL
1469#define bfin_spi_resume NULL
1470#endif
1471
1472MODULE_ALIAS("platform:bfin-spi");
1473static struct platform_driver bfin_spi_driver = {
1474 .driver = {
1475 .name = DRV_NAME,
1476 .owner = THIS_MODULE,
1477 },
1478 .suspend = bfin_spi_suspend,
1479 .resume = bfin_spi_resume,
1480 .remove = __devexit_p(bfin_spi_remove),
1481};
1482
1483static int __init bfin_spi_init(void)
1484{
1485 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1486}
1487subsys_initcall(bfin_spi_init);
1488
1489static void __exit bfin_spi_exit(void)
1490{
1491 platform_driver_unregister(&bfin_spi_driver);
1492}
1493module_exit(bfin_spi_exit);
1494