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23#ifndef __LINUX_XHCI_HCD_H
24#define __LINUX_XHCI_HCD_H
25
26#include <linux/usb.h>
27#include <linux/timer.h>
28#include <linux/kernel.h>
29#include <linux/usb/hcd.h>
30
31
32#include "xhci-ext-caps.h"
33#include "pci-quirks.h"
34
35
36#define XHCI_SBRN_OFFSET (0x60)
37
38
39#define MAX_HC_SLOTS 256
40
41#define MAX_HC_PORTS 127
42
43
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50
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57
58
59struct xhci_cap_regs {
60 __le32 hc_capbase;
61 __le32 hcs_params1;
62 __le32 hcs_params2;
63 __le32 hcs_params3;
64 __le32 hcc_params;
65 __le32 db_off;
66 __le32 run_regs_off;
67
68};
69
70
71
72#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
73
74#define HC_VERSION(p) (((p) >> 16) & 0xffff)
75
76
77
78#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
79#define HCS_SLOTS_MASK 0xff
80
81#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
82
83#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
84
85
86
87
88#define HCS_IST(p) (((p) >> 0) & 0xf)
89
90#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
91
92
93#define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
94
95
96
97#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
98
99#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
100
101
102
103#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
104
105#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
106
107
108
109#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
110
111#define HCC_PPC(p) ((p) & (1 << 3))
112
113#define HCS_INDICATOR(p) ((p) & (1 << 4))
114
115#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
116
117#define HCC_LTC(p) ((p) & (1 << 6))
118
119#define HCC_NSS(p) ((p) & (1 << 7))
120
121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125
126#define DBOFF_MASK (~0x3)
127
128
129#define RTSOFF_MASK (~0x1f)
130
131
132
133#define NUM_PORT_REGS 4
134
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156
157struct xhci_op_regs {
158 __le32 command;
159 __le32 status;
160 __le32 page_size;
161 __le32 reserved1;
162 __le32 reserved2;
163 __le32 dev_notification;
164 __le64 cmd_ring;
165
166 __le32 reserved3[4];
167 __le64 dcbaa_ptr;
168 __le32 config_reg;
169
170 __le32 reserved4[241];
171
172 __le32 port_status_base;
173 __le32 port_power_base;
174 __le32 port_link_base;
175 __le32 reserved5;
176
177 __le32 reserved6[NUM_PORT_REGS*254];
178};
179
180
181
182#define CMD_RUN XHCI_CMD_RUN
183
184
185
186
187#define CMD_RESET (1 << 1)
188
189#define CMD_EIE XHCI_CMD_EIE
190
191#define CMD_HSEIE XHCI_CMD_HSEIE
192
193
194#define CMD_LRESET (1 << 7)
195
196#define CMD_CSS (1 << 8)
197#define CMD_CRS (1 << 9)
198
199#define CMD_EWE XHCI_CMD_EWE
200
201
202
203
204
205#define CMD_PM_INDEX (1 << 11)
206
207
208
209#define IMAN_IP (1 << 1)
210#define IMAN_IE (1 << 0)
211
212
213
214#define STS_HALT XHCI_STS_HALT
215
216#define STS_FATAL (1 << 2)
217
218#define STS_EINT (1 << 3)
219
220#define STS_PORT (1 << 4)
221
222
223#define STS_SAVE (1 << 8)
224
225#define STS_RESTORE (1 << 9)
226
227#define STS_SRE (1 << 10)
228
229#define STS_CNR XHCI_STS_CNR
230
231#define STS_HCE (1 << 12)
232
233
234
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236
237
238
239#define DEV_NOTE_MASK (0xffff)
240#define ENABLE_DEV_NOTE(x) (1 << (x))
241
242
243
244#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
245
246
247
248
249#define CMD_RING_PAUSE (1 << 1)
250
251#define CMD_RING_ABORT (1 << 2)
252
253#define CMD_RING_RUNNING (1 << 3)
254
255
256#define CMD_RING_RSVD_BITS (0x3f)
257
258
259
260#define MAX_DEVS(p) ((p) & 0xff)
261
262
263
264
265#define PORT_CONNECT (1 << 0)
266
267#define PORT_PE (1 << 1)
268
269
270#define PORT_OC (1 << 3)
271
272#define PORT_RESET (1 << 4)
273
274
275
276
277#define PORT_PLS_MASK (0xf << 5)
278#define XDEV_U0 (0x0 << 5)
279#define XDEV_U2 (0x2 << 5)
280#define XDEV_U3 (0x3 << 5)
281#define XDEV_RESUME (0xf << 5)
282
283#define PORT_POWER (1 << 9)
284
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291
292#define DEV_SPEED_MASK (0xf << 10)
293#define XDEV_FS (0x1 << 10)
294#define XDEV_LS (0x2 << 10)
295#define XDEV_HS (0x3 << 10)
296#define XDEV_SS (0x4 << 10)
297#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
298#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
299#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
300#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
301#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
302
303#define SLOT_SPEED_FS (XDEV_FS << 10)
304#define SLOT_SPEED_LS (XDEV_LS << 10)
305#define SLOT_SPEED_HS (XDEV_HS << 10)
306#define SLOT_SPEED_SS (XDEV_SS << 10)
307
308#define PORT_LED_OFF (0 << 14)
309#define PORT_LED_AMBER (1 << 14)
310#define PORT_LED_GREEN (2 << 14)
311#define PORT_LED_MASK (3 << 14)
312
313#define PORT_LINK_STROBE (1 << 16)
314
315#define PORT_CSC (1 << 17)
316
317#define PORT_PEC (1 << 18)
318
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321
322
323#define PORT_WRC (1 << 19)
324
325#define PORT_OCC (1 << 20)
326
327#define PORT_RC (1 << 21)
328
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340
341#define PORT_PLC (1 << 22)
342
343#define PORT_CEC (1 << 23)
344
345
346
347
348#define PORT_CAS (1 << 24)
349
350#define PORT_WKCONN_E (1 << 25)
351
352#define PORT_WKDISC_E (1 << 26)
353
354#define PORT_WKOC_E (1 << 27)
355
356
357#define PORT_DEV_REMOVE (1 << 30)
358
359#define PORT_WR (1 << 31)
360
361
362#define DUPLICATE_ENTRY ((u8)(-1))
363
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365
366
367
368#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
369#define PORT_U1_TIMEOUT_MASK 0xff
370
371#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
372#define PORT_U2_TIMEOUT_MASK (0xff << 8)
373
374
375
376#define PORT_L1S_MASK 7
377#define PORT_L1S_SUCCESS 1
378#define PORT_RWE (1 << 3)
379#define PORT_HIRD(p) (((p) & 0xf) << 4)
380#define PORT_HIRD_MASK (0xf << 4)
381#define PORT_L1DS(p) (((p) & 0xff) << 8)
382#define PORT_HLE (1 << 16)
383
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400
401struct xhci_intr_reg {
402 __le32 irq_pending;
403 __le32 irq_control;
404 __le32 erst_size;
405 __le32 rsvd;
406 __le64 erst_base;
407 __le64 erst_dequeue;
408};
409
410
411#define ER_IRQ_PENDING(p) ((p) & 0x1)
412
413
414#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
415#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
416#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
417
418
419
420
421
422
423#define ER_IRQ_INTERVAL_MASK (0xffff)
424
425#define ER_IRQ_COUNTER_MASK (0xffff << 16)
426
427
428
429#define ERST_SIZE_MASK (0xffff << 16)
430
431
432
433
434
435#define ERST_DESI_MASK (0x7)
436
437
438
439#define ERST_EHB (1 << 3)
440#define ERST_PTR_MASK (0xf)
441
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450
451struct xhci_run_regs {
452 __le32 microframe_index;
453 __le32 rsvd[7];
454 struct xhci_intr_reg ir_set[128];
455};
456
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464
465
466struct xhci_doorbell_array {
467 __le32 doorbell[256];
468};
469
470#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
471#define DB_VALUE_HOST 0x00000000
472
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480
481struct xhci_protocol_caps {
482 u32 revision;
483 u32 name_string;
484 u32 port_info;
485};
486
487#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
488#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
489#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
490
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500
501struct xhci_container_ctx {
502 unsigned type;
503#define XHCI_CTX_TYPE_DEVICE 0x1
504#define XHCI_CTX_TYPE_INPUT 0x2
505
506 int size;
507
508 u8 *bytes;
509 dma_addr_t dma;
510};
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522
523struct xhci_slot_ctx {
524 __le32 dev_info;
525 __le32 dev_info2;
526 __le32 tt_info;
527 __le32 dev_state;
528
529 __le32 reserved[4];
530};
531
532
533
534#define ROUTE_STRING_MASK (0xfffff)
535
536#define DEV_SPEED (0xf << 20)
537
538
539#define DEV_MTT (0x1 << 25)
540
541#define DEV_HUB (0x1 << 26)
542
543#define LAST_CTX_MASK (0x1f << 27)
544#define LAST_CTX(p) ((p) << 27)
545#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
546#define SLOT_FLAG (1 << 0)
547#define EP0_FLAG (1 << 1)
548
549
550
551#define MAX_EXIT (0xffff)
552
553#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
554#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
555
556#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
557
558
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562
563
564#define TT_SLOT (0xff)
565
566
567
568
569#define TT_PORT (0xff << 8)
570#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
571
572
573
574#define DEV_ADDR_MASK (0xff)
575
576
577#define SLOT_STATE (0x1f << 27)
578#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
579
580#define SLOT_STATE_DISABLED 0
581#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
582#define SLOT_STATE_DEFAULT 1
583#define SLOT_STATE_ADDRESSED 2
584#define SLOT_STATE_CONFIGURED 3
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604struct xhci_ep_ctx {
605 __le32 ep_info;
606 __le32 ep_info2;
607 __le64 deq;
608 __le32 tx_info;
609
610 __le32 reserved[3];
611};
612
613
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619
620
621
622
623#define EP_STATE_MASK (0xf)
624#define EP_STATE_DISABLED 0
625#define EP_STATE_RUNNING 1
626#define EP_STATE_HALTED 2
627#define EP_STATE_STOPPED 3
628#define EP_STATE_ERROR 4
629
630#define EP_MULT(p) (((p) & 0x3) << 8)
631#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
632
633
634
635#define EP_INTERVAL(p) (((p) & 0xff) << 16)
636#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
637#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
638#define EP_MAXPSTREAMS_MASK (0x1f << 10)
639#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
640
641#define EP_HAS_LSA (1 << 15)
642
643
644
645
646
647
648#define FORCE_EVENT (0x1)
649#define ERROR_COUNT(p) (((p) & 0x3) << 1)
650#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
651#define EP_TYPE(p) ((p) << 3)
652#define ISOC_OUT_EP 1
653#define BULK_OUT_EP 2
654#define INT_OUT_EP 3
655#define CTRL_EP 4
656#define ISOC_IN_EP 5
657#define BULK_IN_EP 6
658#define INT_IN_EP 7
659
660
661#define MAX_BURST(p) (((p)&0xff) << 8)
662#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
663#define MAX_PACKET(p) (((p)&0xffff) << 16)
664#define MAX_PACKET_MASK (0xffff << 16)
665#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
666
667
668
669
670#define GET_MAX_PACKET(p) ((p) & 0x7ff)
671
672
673#define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
674#define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
675#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
676
677
678#define EP_CTX_CYCLE_MASK (1 << 0)
679
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686
687
688struct xhci_input_control_ctx {
689 __le32 drop_flags;
690 __le32 add_flags;
691 __le32 rsvd2[6];
692};
693
694#define EP_IS_ADDED(ctrl_ctx, i) \
695 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
696#define EP_IS_DROPPED(ctrl_ctx, i) \
697 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
698
699
700
701
702
703struct xhci_command {
704
705 struct xhci_container_ctx *in_ctx;
706 u32 status;
707
708
709
710 struct completion *completion;
711 union xhci_trb *command_trb;
712 struct list_head cmd_list;
713};
714
715
716#define DROP_EP(x) (0x1 << x)
717
718#define ADD_EP(x) (0x1 << x)
719
720struct xhci_stream_ctx {
721
722 __le64 stream_ring;
723
724 __le32 reserved[2];
725};
726
727
728#define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
729
730#define SCT_SEC_TR 0
731
732#define SCT_PRI_TR 1
733
734#define SCT_SSA_8 2
735#define SCT_SSA_16 3
736#define SCT_SSA_32 4
737#define SCT_SSA_64 5
738#define SCT_SSA_128 6
739#define SCT_SSA_256 7
740
741
742struct xhci_stream_info {
743 struct xhci_ring **stream_rings;
744
745 unsigned int num_streams;
746
747
748
749 struct xhci_stream_ctx *stream_ctx_array;
750 unsigned int num_stream_ctxs;
751 dma_addr_t ctx_array_dma;
752
753 struct radix_tree_root trb_address_map;
754 struct xhci_command *free_streams_command;
755};
756
757#define SMALL_STREAM_ARRAY_SIZE 256
758#define MEDIUM_STREAM_ARRAY_SIZE 1024
759
760
761
762
763
764
765
766struct xhci_bw_info {
767
768 unsigned int ep_interval;
769
770 unsigned int mult;
771 unsigned int num_packets;
772 unsigned int max_packet_size;
773 unsigned int max_esit_payload;
774 unsigned int type;
775};
776
777
778
779
780
781
782#define FS_BLOCK 1
783#define HS_BLOCK 4
784#define SS_BLOCK 16
785#define DMI_BLOCK 32
786
787
788
789
790
791
792#define DMI_OVERHEAD 8
793#define DMI_OVERHEAD_BURST 4
794#define SS_OVERHEAD 8
795#define SS_OVERHEAD_BURST 32
796#define HS_OVERHEAD 26
797#define FS_OVERHEAD 20
798#define LS_OVERHEAD 128
799
800
801
802
803
804#define TT_HS_OVERHEAD (31 + 94)
805#define TT_DMI_OVERHEAD (25 + 12)
806
807
808#define FS_BW_LIMIT 1285
809#define TT_BW_LIMIT 1320
810#define HS_BW_LIMIT 1607
811#define SS_BW_LIMIT_IN 3906
812#define DMI_BW_LIMIT_IN 3906
813#define SS_BW_LIMIT_OUT 3906
814#define DMI_BW_LIMIT_OUT 3906
815
816
817#define FS_BW_RESERVED 10
818#define HS_BW_RESERVED 20
819#define SS_BW_RESERVED 10
820
821struct xhci_virt_ep {
822 struct xhci_ring *ring;
823
824 struct xhci_stream_info *stream_info;
825
826
827
828 struct xhci_ring *new_ring;
829 unsigned int ep_state;
830#define SET_DEQ_PENDING (1 << 0)
831#define EP_HALTED (1 << 1)
832#define EP_HALT_PENDING (1 << 2)
833
834#define EP_GETTING_STREAMS (1 << 3)
835#define EP_HAS_STREAMS (1 << 4)
836
837#define EP_GETTING_NO_STREAMS (1 << 5)
838
839 struct list_head cancelled_td_list;
840
841 union xhci_trb *stopped_trb;
842 struct xhci_td *stopped_td;
843 unsigned int stopped_stream;
844
845 struct timer_list stop_cmd_timer;
846 int stop_cmds_pending;
847 struct xhci_hcd *xhci;
848
849
850
851
852 struct xhci_segment *queued_deq_seg;
853 union xhci_trb *queued_deq_ptr;
854
855
856
857
858
859
860
861 bool skip;
862
863 struct xhci_bw_info bw_info;
864 struct list_head bw_endpoint_list;
865};
866
867enum xhci_overhead_type {
868 LS_OVERHEAD_TYPE = 0,
869 FS_OVERHEAD_TYPE,
870 HS_OVERHEAD_TYPE,
871};
872
873struct xhci_interval_bw {
874 unsigned int num_packets;
875
876
877
878 struct list_head endpoints;
879
880 unsigned int overhead[3];
881};
882
883#define XHCI_MAX_INTERVAL 16
884
885struct xhci_interval_bw_table {
886 unsigned int interval0_esit_payload;
887 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
888
889 unsigned int bw_used;
890 unsigned int ss_bw_in;
891 unsigned int ss_bw_out;
892};
893
894
895struct xhci_virt_device {
896 struct usb_device *udev;
897
898
899
900
901
902
903
904
905 struct xhci_container_ctx *out_ctx;
906
907 struct xhci_container_ctx *in_ctx;
908
909 struct xhci_ring **ring_cache;
910 int num_rings_cached;
911
912 int address;
913#define XHCI_MAX_RINGS_CACHED 31
914 struct xhci_virt_ep eps[31];
915 struct completion cmd_completion;
916
917 u32 cmd_status;
918 struct list_head cmd_list;
919 u8 fake_port;
920 u8 real_port;
921 struct xhci_interval_bw_table *bw_table;
922 struct xhci_tt_bw_info *tt_info;
923
924 u16 current_mel;
925};
926
927
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929
930
931
932
933
934
935struct xhci_root_port_bw_info {
936 struct list_head tts;
937 unsigned int num_active_tts;
938 struct xhci_interval_bw_table bw_table;
939};
940
941struct xhci_tt_bw_info {
942 struct list_head tt_list;
943 int slot_id;
944 int ttport;
945 struct xhci_interval_bw_table bw_table;
946 int active_eps;
947};
948
949
950
951
952
953
954struct xhci_device_context_array {
955
956 __le64 dev_context_ptrs[MAX_HC_SLOTS];
957
958 dma_addr_t dma;
959};
960
961
962
963
964
965
966
967struct xhci_transfer_event {
968
969 __le64 buffer;
970 __le32 transfer_len;
971
972 __le32 flags;
973};
974
975
976#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
977
978
979#define COMP_CODE_MASK (0xff << 24)
980#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
981#define COMP_SUCCESS 1
982
983#define COMP_DB_ERR 2
984
985#define COMP_BABBLE 3
986
987#define COMP_TX_ERR 4
988
989#define COMP_TRB_ERR 5
990
991#define COMP_STALL 6
992
993#define COMP_ENOMEM 7
994
995#define COMP_BW_ERR 8
996
997#define COMP_ENOSLOTS 9
998
999#define COMP_STREAM_ERR 10
1000
1001#define COMP_EBADSLT 11
1002
1003#define COMP_EBADEP 12
1004
1005#define COMP_SHORT_TX 13
1006
1007#define COMP_UNDERRUN 14
1008
1009#define COMP_OVERRUN 15
1010
1011#define COMP_VF_FULL 16
1012
1013#define COMP_EINVAL 17
1014
1015#define COMP_BW_OVER 18
1016
1017#define COMP_CTX_STATE 19
1018
1019#define COMP_PING_ERR 20
1020
1021#define COMP_ER_FULL 21
1022
1023#define COMP_DEV_ERR 22
1024
1025#define COMP_MISSED_INT 23
1026
1027#define COMP_CMD_STOP 24
1028
1029#define COMP_CMD_ABORT 25
1030
1031#define COMP_STOP 26
1032
1033#define COMP_STOP_INVAL 27
1034
1035#define COMP_DBG_ABORT 28
1036
1037#define COMP_MEL_ERR 29
1038
1039
1040#define COMP_BUFF_OVER 31
1041
1042#define COMP_ISSUES 32
1043
1044#define COMP_UNKNOWN 33
1045
1046#define COMP_STRID_ERR 34
1047
1048#define COMP_2ND_BW_ERR 35
1049
1050#define COMP_SPLIT_ERR 36
1051
1052struct xhci_link_trb {
1053
1054 __le64 segment_ptr;
1055 __le32 intr_target;
1056 __le32 control;
1057};
1058
1059
1060#define LINK_TOGGLE (0x1<<1)
1061
1062
1063struct xhci_event_cmd {
1064
1065 __le64 cmd_trb;
1066 __le32 status;
1067 __le32 flags;
1068};
1069
1070
1071
1072
1073#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1074#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1075
1076
1077#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1078#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1079
1080#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1081#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1082#define LAST_EP_INDEX 30
1083
1084
1085#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1086#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1087
1088
1089
1090
1091#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1092
1093
1094
1095#define TRB_LEN(p) ((p) & 0x1ffff)
1096
1097#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1098#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1099#define TRB_TBC(p) (((p) & 0x3) << 7)
1100#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1101
1102
1103#define TRB_CYCLE (1<<0)
1104
1105
1106
1107
1108#define TRB_ENT (1<<1)
1109
1110#define TRB_ISP (1<<2)
1111
1112#define TRB_NO_SNOOP (1<<3)
1113
1114#define TRB_CHAIN (1<<4)
1115
1116#define TRB_IOC (1<<5)
1117
1118#define TRB_IDT (1<<6)
1119
1120
1121#define TRB_BEI (1<<9)
1122
1123
1124#define TRB_DIR_IN (1<<16)
1125#define TRB_TX_TYPE(p) ((p) << 16)
1126#define TRB_DATA_OUT 2
1127#define TRB_DATA_IN 3
1128
1129
1130#define TRB_SIA (1<<31)
1131
1132struct xhci_generic_trb {
1133 __le32 field[4];
1134};
1135
1136union xhci_trb {
1137 struct xhci_link_trb link;
1138 struct xhci_transfer_event trans_event;
1139 struct xhci_event_cmd event_cmd;
1140 struct xhci_generic_trb generic;
1141};
1142
1143
1144#define TRB_TYPE_BITMASK (0xfc00)
1145#define TRB_TYPE(p) ((p) << 10)
1146#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1147
1148
1149#define TRB_NORMAL 1
1150
1151#define TRB_SETUP 2
1152
1153#define TRB_DATA 3
1154
1155#define TRB_STATUS 4
1156
1157#define TRB_ISOC 5
1158
1159#define TRB_LINK 6
1160#define TRB_EVENT_DATA 7
1161
1162#define TRB_TR_NOOP 8
1163
1164
1165#define TRB_ENABLE_SLOT 9
1166
1167#define TRB_DISABLE_SLOT 10
1168
1169#define TRB_ADDR_DEV 11
1170
1171#define TRB_CONFIG_EP 12
1172
1173#define TRB_EVAL_CONTEXT 13
1174
1175#define TRB_RESET_EP 14
1176
1177#define TRB_STOP_RING 15
1178
1179#define TRB_SET_DEQ 16
1180
1181#define TRB_RESET_DEV 17
1182
1183#define TRB_FORCE_EVENT 18
1184
1185#define TRB_NEG_BANDWIDTH 19
1186
1187#define TRB_SET_LT 20
1188
1189#define TRB_GET_BW 21
1190
1191#define TRB_FORCE_HEADER 22
1192
1193#define TRB_CMD_NOOP 23
1194
1195
1196
1197#define TRB_TRANSFER 32
1198
1199#define TRB_COMPLETION 33
1200
1201#define TRB_PORT_STATUS 34
1202
1203#define TRB_BANDWIDTH_EVENT 35
1204
1205#define TRB_DOORBELL 36
1206
1207#define TRB_HC_EVENT 37
1208
1209#define TRB_DEV_NOTE 38
1210
1211#define TRB_MFINDEX_WRAP 39
1212
1213
1214
1215#define TRB_NEC_CMD_COMP 48
1216
1217#define TRB_NEC_GET_FW 49
1218
1219#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1220
1221#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1222 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1223#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1224 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1225
1226#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1227#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1228
1229
1230
1231
1232
1233
1234#define TRBS_PER_SEGMENT 64
1235
1236#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1237#define SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1238#define SEGMENT_SHIFT (__ffs(SEGMENT_SIZE))
1239
1240#define TRB_MAX_BUFF_SHIFT 16
1241#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1242
1243struct xhci_segment {
1244 union xhci_trb *trbs;
1245
1246 struct xhci_segment *next;
1247 dma_addr_t dma;
1248};
1249
1250struct xhci_td {
1251 struct list_head td_list;
1252 struct list_head cancelled_td_list;
1253 struct urb *urb;
1254 struct xhci_segment *start_seg;
1255 union xhci_trb *first_trb;
1256 union xhci_trb *last_trb;
1257};
1258
1259struct xhci_dequeue_state {
1260 struct xhci_segment *new_deq_seg;
1261 union xhci_trb *new_deq_ptr;
1262 int new_cycle_state;
1263};
1264
1265enum xhci_ring_type {
1266 TYPE_CTRL = 0,
1267 TYPE_ISOC,
1268 TYPE_BULK,
1269 TYPE_INTR,
1270 TYPE_STREAM,
1271 TYPE_COMMAND,
1272 TYPE_EVENT,
1273};
1274
1275struct xhci_ring {
1276 struct xhci_segment *first_seg;
1277 struct xhci_segment *last_seg;
1278 union xhci_trb *enqueue;
1279 struct xhci_segment *enq_seg;
1280 unsigned int enq_updates;
1281 union xhci_trb *dequeue;
1282 struct xhci_segment *deq_seg;
1283 unsigned int deq_updates;
1284 struct list_head td_list;
1285
1286
1287
1288
1289
1290 u32 cycle_state;
1291 unsigned int stream_id;
1292 unsigned int num_segs;
1293 unsigned int num_trbs_free;
1294 unsigned int num_trbs_free_temp;
1295 enum xhci_ring_type type;
1296 bool last_td_was_short;
1297};
1298
1299struct xhci_erst_entry {
1300
1301 __le64 seg_addr;
1302 __le32 seg_size;
1303
1304 __le32 rsvd;
1305};
1306
1307struct xhci_erst {
1308 struct xhci_erst_entry *entries;
1309 unsigned int num_entries;
1310
1311 dma_addr_t erst_dma_addr;
1312
1313 unsigned int erst_size;
1314};
1315
1316struct xhci_scratchpad {
1317 u64 *sp_array;
1318 dma_addr_t sp_dma;
1319 void **sp_buffers;
1320 dma_addr_t *sp_dma_buffers;
1321};
1322
1323struct urb_priv {
1324 int length;
1325 int td_cnt;
1326 struct xhci_td *td[0];
1327};
1328
1329
1330
1331
1332
1333
1334#define ERST_NUM_SEGS 1
1335
1336#define ERST_SIZE 64
1337
1338#define ERST_ENTRIES 1
1339
1340#define POLL_TIMEOUT 60
1341
1342#define XHCI_STOP_EP_CMD_TIMEOUT 5
1343
1344
1345struct s3_save {
1346 u32 command;
1347 u32 dev_nt;
1348 u64 dcbaa_ptr;
1349 u32 config_reg;
1350 u32 irq_pending;
1351 u32 irq_control;
1352 u32 erst_size;
1353 u64 erst_base;
1354 u64 erst_dequeue;
1355};
1356
1357
1358struct dev_info {
1359 u32 dev_id;
1360 struct list_head list;
1361};
1362
1363struct xhci_bus_state {
1364 unsigned long bus_suspended;
1365 unsigned long next_statechange;
1366
1367
1368
1369 u32 port_c_suspend;
1370 u32 suspended_ports;
1371 u32 port_remote_wakeup;
1372 unsigned long resume_done[USB_MAXCHILDREN];
1373
1374 unsigned long resuming_ports;
1375};
1376
1377static inline unsigned int hcd_index(struct usb_hcd *hcd)
1378{
1379 if (hcd->speed == HCD_USB3)
1380 return 0;
1381 else
1382 return 1;
1383}
1384
1385
1386struct xhci_hcd {
1387 struct usb_hcd *main_hcd;
1388 struct usb_hcd *shared_hcd;
1389
1390 struct xhci_cap_regs __iomem *cap_regs;
1391 struct xhci_op_regs __iomem *op_regs;
1392 struct xhci_run_regs __iomem *run_regs;
1393 struct xhci_doorbell_array __iomem *dba;
1394
1395 struct xhci_intr_reg __iomem *ir_set;
1396
1397
1398 __u32 hcs_params1;
1399 __u32 hcs_params2;
1400 __u32 hcs_params3;
1401 __u32 hcc_params;
1402
1403 spinlock_t lock;
1404
1405
1406 u8 sbrn;
1407 u16 hci_version;
1408 u8 max_slots;
1409 u8 max_interrupters;
1410 u8 max_ports;
1411 u8 isoc_threshold;
1412 int event_ring_max;
1413 int addr_64;
1414
1415 int page_size;
1416
1417 int page_shift;
1418
1419 int msix_count;
1420 struct msix_entry *msix_entries;
1421
1422 struct xhci_device_context_array *dcbaa;
1423 struct xhci_ring *cmd_ring;
1424 unsigned int cmd_ring_reserved_trbs;
1425 struct xhci_ring *event_ring;
1426 struct xhci_erst erst;
1427
1428 struct xhci_scratchpad *scratchpad;
1429
1430 struct list_head lpm_failed_devs;
1431
1432
1433 struct completion addr_dev;
1434 int slot_id;
1435
1436 struct xhci_command *lpm_command;
1437
1438 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1439
1440 struct xhci_root_port_bw_info *rh_bw;
1441
1442
1443 struct dma_pool *device_pool;
1444 struct dma_pool *segment_pool;
1445 struct dma_pool *small_streams_pool;
1446 struct dma_pool *medium_streams_pool;
1447
1448#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1449
1450 struct timer_list event_ring_timer;
1451 int zombie;
1452#endif
1453
1454 unsigned int xhc_state;
1455
1456 u32 command;
1457 struct s3_save s3;
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470#define XHCI_STATE_DYING (1 << 0)
1471#define XHCI_STATE_HALTED (1 << 1)
1472
1473 int error_bitmask;
1474 unsigned int quirks;
1475#define XHCI_LINK_TRB_QUIRK (1 << 0)
1476#define XHCI_RESET_EP_QUIRK (1 << 1)
1477#define XHCI_NEC_HOST (1 << 2)
1478#define XHCI_AMD_PLL_FIX (1 << 3)
1479#define XHCI_SPURIOUS_SUCCESS (1 << 4)
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489#define XHCI_EP_LIMIT_QUIRK (1 << 5)
1490#define XHCI_BROKEN_MSI (1 << 6)
1491#define XHCI_RESET_ON_RESUME (1 << 7)
1492#define XHCI_SW_BW_CHECKING (1 << 8)
1493#define XHCI_AMD_0x96_HOST (1 << 9)
1494#define XHCI_TRUST_TX_LENGTH (1 << 10)
1495#define XHCI_LPM_SUPPORT (1 << 11)
1496#define XHCI_INTEL_HOST (1 << 12)
1497 unsigned int num_active_eps;
1498 unsigned int limit_active_eps;
1499
1500 struct xhci_bus_state bus_state[2];
1501
1502 u8 *port_array;
1503
1504 __le32 __iomem **usb3_ports;
1505 unsigned int num_usb3_ports;
1506
1507 __le32 __iomem **usb2_ports;
1508 unsigned int num_usb2_ports;
1509
1510 unsigned sw_lpm_support:1;
1511
1512 unsigned hw_lpm_support:1;
1513};
1514
1515
1516static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1517{
1518 return *((struct xhci_hcd **) (hcd->hcd_priv));
1519}
1520
1521static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1522{
1523 return xhci->main_hcd;
1524}
1525
1526#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1527#define XHCI_DEBUG 1
1528#else
1529#define XHCI_DEBUG 0
1530#endif
1531
1532#define xhci_dbg(xhci, fmt, args...) \
1533 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1534#define xhci_info(xhci, fmt, args...) \
1535 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1536#define xhci_err(xhci, fmt, args...) \
1537 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1538#define xhci_warn(xhci, fmt, args...) \
1539 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1540
1541
1542
1543static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1544 __le32 __iomem *regs)
1545{
1546 return readl(regs);
1547}
1548static inline void xhci_writel(struct xhci_hcd *xhci,
1549 const unsigned int val, __le32 __iomem *regs)
1550{
1551 writel(val, regs);
1552}
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1564 __le64 __iomem *regs)
1565{
1566 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1567 u64 val_lo = readl(ptr);
1568 u64 val_hi = readl(ptr + 1);
1569 return val_lo + (val_hi << 32);
1570}
1571static inline void xhci_write_64(struct xhci_hcd *xhci,
1572 const u64 val, __le64 __iomem *regs)
1573{
1574 __u32 __iomem *ptr = (__u32 __iomem *) regs;
1575 u32 val_lo = lower_32_bits(val);
1576 u32 val_hi = upper_32_bits(val);
1577
1578 writel(val_lo, ptr);
1579 writel(val_hi, ptr + 1);
1580}
1581
1582static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1583{
1584 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1585}
1586
1587
1588void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1589void xhci_print_registers(struct xhci_hcd *xhci);
1590void xhci_dbg_regs(struct xhci_hcd *xhci);
1591void xhci_print_run_regs(struct xhci_hcd *xhci);
1592void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1593void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1594void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1595void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1596void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1597void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1598void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1599void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1600char *xhci_get_slot_state(struct xhci_hcd *xhci,
1601 struct xhci_container_ctx *ctx);
1602void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1603 unsigned int slot_id, unsigned int ep_index,
1604 struct xhci_virt_ep *ep);
1605
1606
1607void xhci_mem_cleanup(struct xhci_hcd *xhci);
1608int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1609void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1610int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1611int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1612void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1613 struct usb_device *udev);
1614unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1615unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1616unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1617unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1618void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1619void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1620 struct xhci_bw_info *ep_bw,
1621 struct xhci_interval_bw_table *bw_table,
1622 struct usb_device *udev,
1623 struct xhci_virt_ep *virt_ep,
1624 struct xhci_tt_bw_info *tt_info);
1625void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1626 struct xhci_virt_device *virt_dev,
1627 int old_active_eps);
1628void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1629void xhci_update_bw_info(struct xhci_hcd *xhci,
1630 struct xhci_container_ctx *in_ctx,
1631 struct xhci_input_control_ctx *ctrl_ctx,
1632 struct xhci_virt_device *virt_dev);
1633void xhci_endpoint_copy(struct xhci_hcd *xhci,
1634 struct xhci_container_ctx *in_ctx,
1635 struct xhci_container_ctx *out_ctx,
1636 unsigned int ep_index);
1637void xhci_slot_copy(struct xhci_hcd *xhci,
1638 struct xhci_container_ctx *in_ctx,
1639 struct xhci_container_ctx *out_ctx);
1640int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1641 struct usb_device *udev, struct usb_host_endpoint *ep,
1642 gfp_t mem_flags);
1643void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1644int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1645 unsigned int num_trbs, gfp_t flags);
1646void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1647 struct xhci_virt_device *virt_dev,
1648 unsigned int ep_index);
1649struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1650 unsigned int num_stream_ctxs,
1651 unsigned int num_streams, gfp_t flags);
1652void xhci_free_stream_info(struct xhci_hcd *xhci,
1653 struct xhci_stream_info *stream_info);
1654void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1655 struct xhci_ep_ctx *ep_ctx,
1656 struct xhci_stream_info *stream_info);
1657void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1658 struct xhci_ep_ctx *ep_ctx,
1659 struct xhci_virt_ep *ep);
1660void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1661 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1662struct xhci_ring *xhci_dma_to_transfer_ring(
1663 struct xhci_virt_ep *ep,
1664 u64 address);
1665struct xhci_ring *xhci_stream_id_to_ring(
1666 struct xhci_virt_device *dev,
1667 unsigned int ep_index,
1668 unsigned int stream_id);
1669struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1670 bool allocate_in_ctx, bool allocate_completion,
1671 gfp_t mem_flags);
1672void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1673void xhci_free_command(struct xhci_hcd *xhci,
1674 struct xhci_command *command);
1675
1676#ifdef CONFIG_PCI
1677
1678int xhci_register_pci(void);
1679void xhci_unregister_pci(void);
1680#else
1681static inline int xhci_register_pci(void) { return 0; }
1682static inline void xhci_unregister_pci(void) {}
1683#endif
1684
1685#if defined(CONFIG_USB_XHCI_PLATFORM) \
1686 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1687int xhci_register_plat(void);
1688void xhci_unregister_plat(void);
1689#else
1690static inline int xhci_register_plat(void)
1691{ return 0; }
1692static inline void xhci_unregister_plat(void)
1693{ }
1694#endif
1695
1696
1697typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1698void xhci_quiesce(struct xhci_hcd *xhci);
1699int xhci_halt(struct xhci_hcd *xhci);
1700int xhci_reset(struct xhci_hcd *xhci);
1701int xhci_init(struct usb_hcd *hcd);
1702int xhci_run(struct usb_hcd *hcd);
1703void xhci_stop(struct usb_hcd *hcd);
1704void xhci_shutdown(struct usb_hcd *hcd);
1705int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1706
1707#ifdef CONFIG_PM
1708int xhci_suspend(struct xhci_hcd *xhci);
1709int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1710#else
1711#define xhci_suspend NULL
1712#define xhci_resume NULL
1713#endif
1714
1715int xhci_get_frame(struct usb_hcd *hcd);
1716irqreturn_t xhci_irq(struct usb_hcd *hcd);
1717irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1718int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1719void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1720int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1721 struct xhci_virt_device *virt_dev,
1722 struct usb_device *hdev,
1723 struct usb_tt *tt, gfp_t mem_flags);
1724int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1725 struct usb_host_endpoint **eps, unsigned int num_eps,
1726 unsigned int num_streams, gfp_t mem_flags);
1727int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1728 struct usb_host_endpoint **eps, unsigned int num_eps,
1729 gfp_t mem_flags);
1730int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1731int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1732int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1733 struct usb_device *udev, int enable);
1734int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1735 struct usb_tt *tt, gfp_t mem_flags);
1736int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1737int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1738int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1739int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1740void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1741int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1742int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1743void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1744
1745
1746dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1747struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1748 union xhci_trb *start_trb, union xhci_trb *end_trb,
1749 dma_addr_t suspect_dma);
1750int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1751void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1752int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1753int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1754 u32 slot_id);
1755int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1756 u32 field1, u32 field2, u32 field3, u32 field4);
1757int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1758 unsigned int ep_index, int suspend);
1759int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1760 int slot_id, unsigned int ep_index);
1761int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1762 int slot_id, unsigned int ep_index);
1763int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1764 int slot_id, unsigned int ep_index);
1765int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1766 struct urb *urb, int slot_id, unsigned int ep_index);
1767int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1768 u32 slot_id, bool command_must_succeed);
1769int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1770 u32 slot_id, bool command_must_succeed);
1771int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1772 unsigned int ep_index);
1773int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1774void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1775 unsigned int slot_id, unsigned int ep_index,
1776 unsigned int stream_id, struct xhci_td *cur_td,
1777 struct xhci_dequeue_state *state);
1778void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1779 unsigned int slot_id, unsigned int ep_index,
1780 unsigned int stream_id,
1781 struct xhci_dequeue_state *deq_state);
1782void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1783 struct usb_device *udev, unsigned int ep_index);
1784void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1785 unsigned int slot_id, unsigned int ep_index,
1786 struct xhci_dequeue_state *deq_state);
1787void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1788void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1789 unsigned int ep_index, unsigned int stream_id);
1790
1791
1792void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1793 int port_id, u32 link_state);
1794int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1795 struct usb_device *udev, enum usb3_link_state state);
1796int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1797 struct usb_device *udev, enum usb3_link_state state);
1798void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1799 int port_id, u32 port_bit);
1800int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1801 char *buf, u16 wLength);
1802int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1803
1804#ifdef CONFIG_PM
1805int xhci_bus_suspend(struct usb_hcd *hcd);
1806int xhci_bus_resume(struct usb_hcd *hcd);
1807#else
1808#define xhci_bus_suspend NULL
1809#define xhci_bus_resume NULL
1810#endif
1811
1812u32 xhci_port_state_to_neutral(u32 state);
1813int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1814 u16 port);
1815void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1816
1817
1818struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1819struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1820struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1821
1822#endif
1823