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25#ifndef __TWL_H_
26#define __TWL_H_
27
28#include <linux/types.h>
29#include <linux/input/matrix_keypad.h>
30
31
32
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40
41
42
43#define TWL4030_MODULE_USB 0x00
44
45
46#define TWL4030_MODULE_AUDIO_VOICE 0x01
47#define TWL4030_MODULE_GPIO 0x02
48#define TWL4030_MODULE_INTBR 0x03
49#define TWL4030_MODULE_PIH 0x04
50#define TWL4030_MODULE_TEST 0x05
51
52
53#define TWL4030_MODULE_KEYPAD 0x06
54#define TWL4030_MODULE_MADC 0x07
55#define TWL4030_MODULE_INTERRUPTS 0x08
56#define TWL4030_MODULE_LED 0x09
57#define TWL4030_MODULE_MAIN_CHARGE 0x0A
58#define TWL4030_MODULE_PRECHARGE 0x0B
59#define TWL4030_MODULE_PWM0 0x0C
60#define TWL4030_MODULE_PWM1 0x0D
61#define TWL4030_MODULE_PWMA 0x0E
62#define TWL4030_MODULE_PWMB 0x0F
63
64#define TWL5031_MODULE_ACCESSORY 0x10
65#define TWL5031_MODULE_INTERRUPTS 0x11
66
67
68#define TWL4030_MODULE_BACKUP 0x12
69#define TWL4030_MODULE_INT 0x13
70#define TWL4030_MODULE_PM_MASTER 0x14
71#define TWL4030_MODULE_PM_RECEIVER 0x15
72#define TWL4030_MODULE_RTC 0x16
73#define TWL4030_MODULE_SECURED_REG 0x17
74
75#define TWL_MODULE_USB TWL4030_MODULE_USB
76#define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
77#define TWL_MODULE_PIH TWL4030_MODULE_PIH
78#define TWL_MODULE_MADC TWL4030_MODULE_MADC
79#define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
80#define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
81#define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
82#define TWL_MODULE_RTC TWL4030_MODULE_RTC
83#define TWL_MODULE_PWM TWL4030_MODULE_PWM0
84
85#define TWL6030_MODULE_ID0 0x0D
86#define TWL6030_MODULE_ID1 0x0E
87#define TWL6030_MODULE_ID2 0x0F
88
89#define GPIO_INTR_OFFSET 0
90#define KEYPAD_INTR_OFFSET 1
91#define BCI_INTR_OFFSET 2
92#define MADC_INTR_OFFSET 3
93#define USB_INTR_OFFSET 4
94#define CHARGERFAULT_INTR_OFFSET 5
95#define BCI_PRES_INTR_OFFSET 9
96#define USB_PRES_INTR_OFFSET 10
97#define RTC_INTR_OFFSET 11
98
99
100
101
102#define PWR_INTR_OFFSET 0
103#define HOTDIE_INTR_OFFSET 12
104#define SMPSLDO_INTR_OFFSET 13
105#define BATDETECT_INTR_OFFSET 14
106#define SIMDETECT_INTR_OFFSET 15
107#define MMCDETECT_INTR_OFFSET 16
108#define GASGAUGE_INTR_OFFSET 17
109#define USBOTG_INTR_OFFSET 4
110#define CHARGER_INTR_OFFSET 2
111#define RSV_INTR_OFFSET 0
112
113
114#define REG_INT_STS_A 0x00
115#define REG_INT_STS_B 0x01
116#define REG_INT_STS_C 0x02
117
118#define REG_INT_MSK_LINE_A 0x03
119#define REG_INT_MSK_LINE_B 0x04
120#define REG_INT_MSK_LINE_C 0x05
121
122#define REG_INT_MSK_STS_A 0x06
123#define REG_INT_MSK_STS_B 0x07
124#define REG_INT_MSK_STS_C 0x08
125
126
127#define TWL6030_PWR_INT_MASK 0x07
128#define TWL6030_RTC_INT_MASK 0x18
129#define TWL6030_HOTDIE_INT_MASK 0x20
130#define TWL6030_SMPSLDOA_INT_MASK 0xC0
131
132
133#define TWL6030_SMPSLDOB_INT_MASK 0x01
134#define TWL6030_BATDETECT_INT_MASK 0x02
135#define TWL6030_SIMDETECT_INT_MASK 0x04
136#define TWL6030_MMCDETECT_INT_MASK 0x08
137#define TWL6030_GPADC_INT_MASK 0x60
138#define TWL6030_GASGAUGE_INT_MASK 0x80
139
140
141#define TWL6030_USBOTG_INT_MASK 0x0F
142#define TWL6030_CHARGER_CTRL_INT_MASK 0x10
143#define TWL6030_CHARGER_FAULT_INT_MASK 0x60
144
145#define TWL6030_MMCCTRL 0xEE
146#define VMMC_AUTO_OFF (0x1 << 3)
147#define SW_FC (0x1 << 2)
148#define STS_MMC 0x1
149
150#define TWL6030_CFG_INPUT_PUPD3 0xF2
151#define MMC_PU (0x1 << 3)
152#define MMC_PD (0x1 << 2)
153
154#define TWL_SIL_TYPE(rev) ((rev) & 0x00FFFFFF)
155#define TWL_SIL_REV(rev) ((rev) >> 24)
156#define TWL_SIL_5030 0x09002F
157#define TWL5030_REV_1_0 0x00
158#define TWL5030_REV_1_1 0x10
159#define TWL5030_REV_1_2 0x30
160
161#define TWL4030_CLASS_ID 0x4030
162#define TWL6030_CLASS_ID 0x6030
163unsigned int twl_rev(void);
164#define GET_TWL_REV (twl_rev())
165#define TWL_CLASS_IS(class, id) \
166static inline int twl_class_is_ ##class(void) \
167{ \
168 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
169}
170
171TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
172TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
173
174
175
176
177int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
178int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
179
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183
184
185
186int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
187int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
188
189int twl_get_type(void);
190int twl_get_version(void);
191
192int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
193int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
194
195
196#ifdef CONFIG_TWL4030_CORE
197int twl6030_mmc_card_detect_config(void);
198#else
199static inline int twl6030_mmc_card_detect_config(void)
200{
201 pr_debug("twl6030_mmc_card_detect_config not supported\n");
202 return 0;
203}
204#endif
205
206
207#ifdef CONFIG_TWL4030_CORE
208int twl6030_mmc_card_detect(struct device *dev, int slot);
209#else
210static inline int twl6030_mmc_card_detect(struct device *dev, int slot)
211{
212 pr_debug("Call back twl6030_mmc_card_detect not supported\n");
213 return -EIO;
214}
215#endif
216
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225
226
227#define TWL4030_SIH_CTRL_EXCLEN_MASK BIT(0)
228#define TWL4030_SIH_CTRL_PENDDIS_MASK BIT(1)
229#define TWL4030_SIH_CTRL_COR_MASK BIT(2)
230
231
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235
236
237#define REG_GPIODATAIN1 0x0
238#define REG_GPIODATAIN2 0x1
239#define REG_GPIODATAIN3 0x2
240#define REG_GPIODATADIR1 0x3
241#define REG_GPIODATADIR2 0x4
242#define REG_GPIODATADIR3 0x5
243#define REG_GPIODATAOUT1 0x6
244#define REG_GPIODATAOUT2 0x7
245#define REG_GPIODATAOUT3 0x8
246#define REG_CLEARGPIODATAOUT1 0x9
247#define REG_CLEARGPIODATAOUT2 0xA
248#define REG_CLEARGPIODATAOUT3 0xB
249#define REG_SETGPIODATAOUT1 0xC
250#define REG_SETGPIODATAOUT2 0xD
251#define REG_SETGPIODATAOUT3 0xE
252#define REG_GPIO_DEBEN1 0xF
253#define REG_GPIO_DEBEN2 0x10
254#define REG_GPIO_DEBEN3 0x11
255#define REG_GPIO_CTRL 0x12
256#define REG_GPIOPUPDCTR1 0x13
257#define REG_GPIOPUPDCTR2 0x14
258#define REG_GPIOPUPDCTR3 0x15
259#define REG_GPIOPUPDCTR4 0x16
260#define REG_GPIOPUPDCTR5 0x17
261#define REG_GPIO_ISR1A 0x19
262#define REG_GPIO_ISR2A 0x1A
263#define REG_GPIO_ISR3A 0x1B
264#define REG_GPIO_IMR1A 0x1C
265#define REG_GPIO_IMR2A 0x1D
266#define REG_GPIO_IMR3A 0x1E
267#define REG_GPIO_ISR1B 0x1F
268#define REG_GPIO_ISR2B 0x20
269#define REG_GPIO_ISR3B 0x21
270#define REG_GPIO_IMR1B 0x22
271#define REG_GPIO_IMR2B 0x23
272#define REG_GPIO_IMR3B 0x24
273#define REG_GPIO_EDR1 0x28
274#define REG_GPIO_EDR2 0x29
275#define REG_GPIO_EDR3 0x2A
276#define REG_GPIO_EDR4 0x2B
277#define REG_GPIO_EDR5 0x2C
278#define REG_GPIO_SIH_CTRL 0x2D
279
280
281
282
283#define TWL4030_GPIO_MAX 18
284
285
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289
290
291#define REG_IDCODE_7_0 0x00
292#define REG_IDCODE_15_8 0x01
293#define REG_IDCODE_16_23 0x02
294#define REG_IDCODE_31_24 0x03
295#define REG_GPPUPDCTR1 0x0F
296#define REG_UNLOCK_TEST_REG 0x12
297
298
299
300#define I2C_SCL_CTRL_PU BIT(0)
301#define I2C_SDA_CTRL_PU BIT(2)
302#define SR_I2C_SCL_CTRL_PU BIT(4)
303#define SR_I2C_SDA_CTRL_PU BIT(6)
304
305#define TWL_EEPROM_R_UNLOCK 0x49
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313
314#define TWL4030_KEYPAD_KEYP_ISR1 0x11
315#define TWL4030_KEYPAD_KEYP_IMR1 0x12
316#define TWL4030_KEYPAD_KEYP_ISR2 0x13
317#define TWL4030_KEYPAD_KEYP_IMR2 0x14
318#define TWL4030_KEYPAD_KEYP_SIR 0x15
319#define TWL4030_KEYPAD_KEYP_EDR 0x16
320#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0x17
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328
329#define TWL4030_MADC_ISR1 0x61
330#define TWL4030_MADC_IMR1 0x62
331#define TWL4030_MADC_ISR2 0x63
332#define TWL4030_MADC_IMR2 0x64
333#define TWL4030_MADC_SIR 0x65
334#define TWL4030_MADC_EDR 0x66
335#define TWL4030_MADC_SIH_CTRL 0x67
336
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341
342
343#define TWL4030_INTERRUPTS_BCIISR1A 0x0
344#define TWL4030_INTERRUPTS_BCIISR2A 0x1
345#define TWL4030_INTERRUPTS_BCIIMR1A 0x2
346#define TWL4030_INTERRUPTS_BCIIMR2A 0x3
347#define TWL4030_INTERRUPTS_BCIISR1B 0x4
348#define TWL4030_INTERRUPTS_BCIISR2B 0x5
349#define TWL4030_INTERRUPTS_BCIIMR1B 0x6
350#define TWL4030_INTERRUPTS_BCIIMR2B 0x7
351#define TWL4030_INTERRUPTS_BCISIR1 0x8
352#define TWL4030_INTERRUPTS_BCISIR2 0x9
353#define TWL4030_INTERRUPTS_BCIEDR1 0xa
354#define TWL4030_INTERRUPTS_BCIEDR2 0xb
355#define TWL4030_INTERRUPTS_BCIEDR3 0xc
356#define TWL4030_INTERRUPTS_BCISIHCTRL 0xd
357
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363
364#define TWL4030_INT_PWR_ISR1 0x0
365#define TWL4030_INT_PWR_IMR1 0x1
366#define TWL4030_INT_PWR_ISR2 0x2
367#define TWL4030_INT_PWR_IMR2 0x3
368#define TWL4030_INT_PWR_SIR 0x4
369#define TWL4030_INT_PWR_EDR1 0x5
370#define TWL4030_INT_PWR_EDR2 0x6
371#define TWL4030_INT_PWR_SIH_CTRL 0x7
372
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376
377
378#define TWL5031_ACIIMR_LSB 0x05
379#define TWL5031_ACIIMR_MSB 0x06
380#define TWL5031_ACIIDR_LSB 0x07
381#define TWL5031_ACIIDR_MSB 0x08
382#define TWL5031_ACCISR1 0x0F
383#define TWL5031_ACCIMR1 0x10
384#define TWL5031_ACCISR2 0x11
385#define TWL5031_ACCIMR2 0x12
386#define TWL5031_ACCSIR 0x13
387#define TWL5031_ACCEDR1 0x14
388#define TWL5031_ACCSIHCTRL 0x15
389
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395
396#define TWL5031_INTERRUPTS_BCIISR1 0x0
397#define TWL5031_INTERRUPTS_BCIIMR1 0x1
398#define TWL5031_INTERRUPTS_BCIISR2 0x2
399#define TWL5031_INTERRUPTS_BCIIMR2 0x3
400#define TWL5031_INTERRUPTS_BCISIR 0x4
401#define TWL5031_INTERRUPTS_BCIEDR1 0x5
402#define TWL5031_INTERRUPTS_BCIEDR2 0x6
403#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
404
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410
411#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x00
412#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x01
413#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x02
414#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x03
415#define TWL4030_PM_MASTER_STS_BOOT 0x04
416#define TWL4030_PM_MASTER_CFG_BOOT 0x05
417#define TWL4030_PM_MASTER_SHUNDAN 0x06
418#define TWL4030_PM_MASTER_BOOT_BCI 0x07
419#define TWL4030_PM_MASTER_CFG_PWRANA1 0x08
420#define TWL4030_PM_MASTER_CFG_PWRANA2 0x09
421#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x0b
422#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x0c
423#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x0d
424#define TWL4030_PM_MASTER_PROTECT_KEY 0x0e
425#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x0f
426#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x10
427#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x11
428#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x12
429#define TWL4030_PM_MASTER_STS_P123_STATE 0x13
430#define TWL4030_PM_MASTER_PB_CFG 0x14
431#define TWL4030_PM_MASTER_PB_WORD_MSB 0x15
432#define TWL4030_PM_MASTER_PB_WORD_LSB 0x16
433#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x1c
434#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x1d
435#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x1e
436#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x1f
437#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x20
438#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x21
439#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x22
440#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x23
441#define TWL4030_PM_MASTER_MEMORY_DATA 0x24
442
443#define TWL4030_PM_MASTER_KEY_CFG1 0xc0
444#define TWL4030_PM_MASTER_KEY_CFG2 0x0c
445
446#define TWL4030_PM_MASTER_KEY_TST1 0xe0
447#define TWL4030_PM_MASTER_KEY_TST2 0x0e
448
449#define TWL4030_PM_MASTER_GLOBAL_TST 0xb6
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462
463#define DEV_GRP_NULL 0x0
464#define DEV_GRP_P1 0x1
465#define DEV_GRP_P2 0x2
466#define DEV_GRP_P3 0x4
467
468
469#define RES_GRP_RES 0x0
470#define RES_GRP_PP 0x1
471#define RES_GRP_RC 0x2
472#define RES_GRP_PP_RC 0x3
473#define RES_GRP_PR 0x4
474#define RES_GRP_PP_PR 0x5
475#define RES_GRP_RC_PR 0x6
476#define RES_GRP_ALL 0x7
477
478#define RES_TYPE2_R0 0x0
479
480#define RES_TYPE_ALL 0x7
481
482
483#define RES_STATE_WRST 0xF
484#define RES_STATE_ACTIVE 0xE
485#define RES_STATE_SLEEP 0x8
486#define RES_STATE_OFF 0x0
487
488
489
490
491#define RES_VAUX1 1
492#define RES_VAUX2 2
493#define RES_VAUX3 3
494#define RES_VAUX4 4
495#define RES_VMMC1 5
496#define RES_VMMC2 6
497#define RES_VPLL1 7
498#define RES_VPLL2 8
499#define RES_VSIM 9
500#define RES_VDAC 10
501#define RES_VINTANA1 11
502#define RES_VINTANA2 12
503#define RES_VINTDIG 13
504#define RES_VIO 14
505#define RES_VDD1 15
506#define RES_VDD2 16
507#define RES_VUSB_1V5 17
508#define RES_VUSB_1V8 18
509#define RES_VUSB_3V1 19
510#define RES_VUSBCP 20
511#define RES_REGEN 21
512
513#define RES_NRES_PWRON 22
514#define RES_CLKEN 23
515#define RES_SYSEN 24
516#define RES_HFCLKOUT 25
517#define RES_32KCLKOUT 26
518#define RES_RESET 27
519
520#define RES_MAIN_REF 28
521
522#define TOTAL_RESOURCES 28
523
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534
535
536#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
537 ( (devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
538 | (type) << 4 | (state))
539
540#define MSG_SINGULAR(devgrp, id, state) \
541 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
542
543#define MSG_BROADCAST_ALL(devgrp, state) \
544 ((devgrp) << 5 | (state))
545
546#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
547#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
548#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
549
550
551struct twl4030_clock_init_data {
552 bool ck32k_lowpwr_enable;
553};
554
555struct twl4030_bci_platform_data {
556 int *battery_tmp_tbl;
557 unsigned int tblsize;
558};
559
560
561struct twl4030_gpio_platform_data {
562 int gpio_base;
563 unsigned irq_base, irq_end;
564
565
566 bool use_leds;
567
568
569 u8 mmc_cd;
570
571
572 u32 debounce;
573
574
575
576
577
578
579 u32 pullups;
580 u32 pulldowns;
581
582 int (*setup)(struct device *dev,
583 unsigned gpio, unsigned ngpio);
584 int (*teardown)(struct device *dev,
585 unsigned gpio, unsigned ngpio);
586};
587
588struct twl4030_madc_platform_data {
589 int irq_line;
590};
591
592
593
594
595
596#define PERSISTENT_KEY(r, c) KEY((r), (c), KEY_RESERVED)
597
598struct twl4030_keypad_data {
599 const struct matrix_keymap_data *keymap_data;
600 unsigned rows;
601 unsigned cols;
602 bool rep;
603};
604
605enum twl4030_usb_mode {
606 T2_USB_MODE_ULPI = 1,
607 T2_USB_MODE_CEA2011_3PIN = 2,
608};
609
610struct twl4030_usb_data {
611 enum twl4030_usb_mode usb_mode;
612 unsigned long features;
613
614 int (*phy_init)(struct device *dev);
615 int (*phy_exit)(struct device *dev);
616
617 int (*phy_power)(struct device *dev, int iD, int on);
618
619 int (*phy_set_clock)(struct device *dev, int on);
620
621 int (*phy_suspend)(struct device *dev, int suspend);
622};
623
624struct twl4030_ins {
625 u16 pmb_message;
626 u8 delay;
627};
628
629struct twl4030_script {
630 struct twl4030_ins *script;
631 unsigned size;
632 u8 flags;
633#define TWL4030_WRST_SCRIPT (1<<0)
634#define TWL4030_WAKEUP12_SCRIPT (1<<1)
635#define TWL4030_WAKEUP3_SCRIPT (1<<2)
636#define TWL4030_SLEEP_SCRIPT (1<<3)
637};
638
639struct twl4030_resconfig {
640 u8 resource;
641 u8 devgroup;
642 u8 type;
643 u8 type2;
644 u8 remap_off;
645 u8 remap_sleep;
646};
647
648struct twl4030_power_data {
649 struct twl4030_script **scripts;
650 unsigned num;
651 struct twl4030_resconfig *resource_config;
652#define TWL4030_RESCONFIG_UNDEF ((u8)-1)
653 bool use_poweroff;
654};
655
656extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
657extern int twl4030_remove_script(u8 flags);
658extern void twl4030_power_off(void);
659
660struct twl4030_codec_data {
661 unsigned int digimic_delay;
662 unsigned int ramp_delay_value;
663 unsigned int offset_cncl_path;
664 unsigned int check_defaults:1;
665 unsigned int reset_registers:1;
666 unsigned int hs_extmute:1;
667 void (*set_hs_extmute)(int mute);
668};
669
670struct twl4030_vibra_data {
671 unsigned int coexist;
672};
673
674struct twl4030_audio_data {
675 unsigned int audio_mclk;
676 struct twl4030_codec_data *codec;
677 struct twl4030_vibra_data *vibra;
678
679
680 int audpwron_gpio;
681 int naudint_irq;
682 unsigned int irq_base;
683};
684
685struct twl4030_platform_data {
686 unsigned irq_base, irq_end;
687 struct twl4030_clock_init_data *clock;
688 struct twl4030_bci_platform_data *bci;
689 struct twl4030_gpio_platform_data *gpio;
690 struct twl4030_madc_platform_data *madc;
691 struct twl4030_keypad_data *keypad;
692 struct twl4030_usb_data *usb;
693 struct twl4030_power_data *power;
694 struct twl4030_audio_data *audio;
695
696
697 struct regulator_init_data *vdac;
698 struct regulator_init_data *vaux1;
699 struct regulator_init_data *vaux2;
700 struct regulator_init_data *vaux3;
701 struct regulator_init_data *vdd1;
702 struct regulator_init_data *vdd2;
703 struct regulator_init_data *vdd3;
704
705 struct regulator_init_data *vpll1;
706 struct regulator_init_data *vpll2;
707 struct regulator_init_data *vmmc1;
708 struct regulator_init_data *vmmc2;
709 struct regulator_init_data *vsim;
710 struct regulator_init_data *vaux4;
711 struct regulator_init_data *vio;
712 struct regulator_init_data *vintana1;
713 struct regulator_init_data *vintana2;
714 struct regulator_init_data *vintdig;
715
716 struct regulator_init_data *vmmc;
717 struct regulator_init_data *vpp;
718 struct regulator_init_data *vusim;
719 struct regulator_init_data *vana;
720 struct regulator_init_data *vcxio;
721 struct regulator_init_data *vusb;
722 struct regulator_init_data *clk32kg;
723 struct regulator_init_data *v1v8;
724 struct regulator_init_data *v2v1;
725
726 struct regulator_init_data *ldo1;
727 struct regulator_init_data *ldo2;
728 struct regulator_init_data *ldo3;
729 struct regulator_init_data *ldo4;
730 struct regulator_init_data *ldo5;
731 struct regulator_init_data *ldo6;
732 struct regulator_init_data *ldo7;
733 struct regulator_init_data *ldoln;
734 struct regulator_init_data *ldousb;
735
736 struct regulator_init_data *smps3;
737 struct regulator_init_data *smps4;
738 struct regulator_init_data *vio6025;
739};
740
741struct twl_regulator_driver_data {
742 int (*set_voltage)(void *data, int target_uV);
743 int (*get_voltage)(void *data);
744 void *data;
745 unsigned long features;
746};
747
748#define TWL4030_VAUX2 BIT(0)
749#define TPS_SUBSET BIT(1)
750#define TWL5031 BIT(2)
751#define TWL6030_CLASS BIT(3)
752#define TWL6025_SUBCLASS BIT(4)
753#define TWL4030_ALLOW_UNSUPPORTED BIT(5)
754
755
756
757
758
759
760
761int twl4030_sih_setup(struct device *dev, int module, int irq_base);
762
763
764#define TWL4030_VDAC_DEV_GRP 0x3B
765#define TWL4030_VDAC_DEDICATED 0x3E
766#define TWL4030_VAUX1_DEV_GRP 0x17
767#define TWL4030_VAUX1_DEDICATED 0x1A
768#define TWL4030_VAUX2_DEV_GRP 0x1B
769#define TWL4030_VAUX2_DEDICATED 0x1E
770#define TWL4030_VAUX3_DEV_GRP 0x1F
771#define TWL4030_VAUX3_DEDICATED 0x22
772
773static inline int twl4030charger_usb_en(int enable) { return 0; }
774
775
776
777
778
779
780
781
782
783
784
785#define TWL4030_REG_VDD1 0
786#define TWL4030_REG_VDD2 1
787#define TWL4030_REG_VIO 2
788
789
790#define TWL4030_REG_VDAC 3
791#define TWL4030_REG_VPLL1 4
792#define TWL4030_REG_VPLL2 5
793#define TWL4030_REG_VMMC1 6
794#define TWL4030_REG_VMMC2 7
795#define TWL4030_REG_VSIM 8
796#define TWL4030_REG_VAUX1 9
797#define TWL4030_REG_VAUX2_4030 10
798#define TWL4030_REG_VAUX2 11
799#define TWL4030_REG_VAUX3 12
800#define TWL4030_REG_VAUX4 13
801
802
803#define TWL4030_REG_VINTANA1 14
804#define TWL4030_REG_VINTANA2 15
805#define TWL4030_REG_VINTDIG 16
806#define TWL4030_REG_VUSB1V5 17
807#define TWL4030_REG_VUSB1V8 18
808#define TWL4030_REG_VUSB3V1 19
809
810
811
812#define TWL6030_REG_VDD1 30
813#define TWL6030_REG_VDD2 31
814#define TWL6030_REG_VDD3 32
815
816
817#define TWL6030_REG_VMEM 33
818#define TWL6030_REG_V2V1 34
819#define TWL6030_REG_V1V29 35
820#define TWL6030_REG_V1V8 36
821
822
823#define TWL6030_REG_VAUX1_6030 37
824#define TWL6030_REG_VAUX2_6030 38
825#define TWL6030_REG_VAUX3_6030 39
826#define TWL6030_REG_VMMC 40
827#define TWL6030_REG_VPP 41
828#define TWL6030_REG_VUSIM 42
829#define TWL6030_REG_VANA 43
830#define TWL6030_REG_VCXIO 44
831#define TWL6030_REG_VDAC 45
832#define TWL6030_REG_VUSB 46
833
834
835#define TWL6030_REG_VRTC 47
836#define TWL6030_REG_CLK32KG 48
837
838
839#define TWL6025_REG_LDO2 49
840#define TWL6025_REG_LDO4 50
841#define TWL6025_REG_LDO3 51
842#define TWL6025_REG_LDO5 52
843#define TWL6025_REG_LDO1 53
844#define TWL6025_REG_LDO7 54
845#define TWL6025_REG_LDO6 55
846#define TWL6025_REG_LDOLN 56
847#define TWL6025_REG_LDOUSB 57
848
849
850#define TWL6025_REG_SMPS3 58
851#define TWL6025_REG_SMPS4 59
852#define TWL6025_REG_VIO 60
853
854
855#endif
856