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33#ifndef MLX4_QP_H
34#define MLX4_QP_H
35
36#include <linux/types.h>
37
38#include <linux/mlx4/device.h>
39
40#define MLX4_INVALID_LKEY 0x100
41
42enum mlx4_qp_optpar {
43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
44 MLX4_QP_OPTPAR_RRE = 1 << 1,
45 MLX4_QP_OPTPAR_RAE = 1 << 2,
46 MLX4_QP_OPTPAR_RWE = 1 << 3,
47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
58 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20
59};
60
61enum mlx4_qp_state {
62 MLX4_QP_STATE_RST = 0,
63 MLX4_QP_STATE_INIT = 1,
64 MLX4_QP_STATE_RTR = 2,
65 MLX4_QP_STATE_RTS = 3,
66 MLX4_QP_STATE_SQER = 4,
67 MLX4_QP_STATE_SQD = 5,
68 MLX4_QP_STATE_ERR = 6,
69 MLX4_QP_STATE_SQ_DRAINING = 7,
70 MLX4_QP_NUM_STATE
71};
72
73enum {
74 MLX4_QP_ST_RC = 0x0,
75 MLX4_QP_ST_UC = 0x1,
76 MLX4_QP_ST_RD = 0x2,
77 MLX4_QP_ST_UD = 0x3,
78 MLX4_QP_ST_XRC = 0x6,
79 MLX4_QP_ST_MLX = 0x7
80};
81
82enum {
83 MLX4_QP_PM_MIGRATED = 0x3,
84 MLX4_QP_PM_ARMED = 0x0,
85 MLX4_QP_PM_REARM = 0x1
86};
87
88enum {
89
90 MLX4_QP_BIT_SRE = 1 << 15,
91 MLX4_QP_BIT_SWE = 1 << 14,
92 MLX4_QP_BIT_SAE = 1 << 13,
93
94 MLX4_QP_BIT_RRE = 1 << 15,
95 MLX4_QP_BIT_RWE = 1 << 14,
96 MLX4_QP_BIT_RAE = 1 << 13,
97 MLX4_QP_BIT_RIC = 1 << 4,
98};
99
100enum {
101 MLX4_RSS_HASH_XOR = 0,
102 MLX4_RSS_HASH_TOP = 1,
103
104 MLX4_RSS_UDP_IPV6 = 1 << 0,
105 MLX4_RSS_UDP_IPV4 = 1 << 1,
106 MLX4_RSS_TCP_IPV6 = 1 << 2,
107 MLX4_RSS_IPV6 = 1 << 3,
108 MLX4_RSS_TCP_IPV4 = 1 << 4,
109 MLX4_RSS_IPV4 = 1 << 5,
110
111
112 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
113
114 MLX4_RSS_QPC_FLAG_OFFSET = 13,
115};
116
117struct mlx4_rss_context {
118 __be32 base_qpn;
119 __be32 default_qpn;
120 u16 reserved;
121 u8 hash_fn;
122 u8 flags;
123 __be32 rss_key[10];
124 __be32 base_qpn_udp;
125};
126
127struct mlx4_qp_path {
128 u8 fl;
129 u8 reserved1[2];
130 u8 pkey_index;
131 u8 counter_index;
132 u8 grh_mylmc;
133 __be16 rlid;
134 u8 ackto;
135 u8 mgid_index;
136 u8 static_rate;
137 u8 hop_limit;
138 __be32 tclass_flowlabel;
139 u8 rgid[16];
140 u8 sched_queue;
141 u8 vlan_index;
142 u8 feup;
143 u8 reserved3;
144 u8 reserved4[2];
145 u8 dmac[6];
146};
147
148struct mlx4_qp_context {
149 __be32 flags;
150 __be32 pd;
151 u8 mtu_msgmax;
152 u8 rq_size_stride;
153 u8 sq_size_stride;
154 u8 rlkey;
155 __be32 usr_page;
156 __be32 local_qpn;
157 __be32 remote_qpn;
158 struct mlx4_qp_path pri_path;
159 struct mlx4_qp_path alt_path;
160 __be32 params1;
161 u32 reserved1;
162 __be32 next_send_psn;
163 __be32 cqn_send;
164 u32 reserved2[2];
165 __be32 last_acked_psn;
166 __be32 ssn;
167 __be32 params2;
168 __be32 rnr_nextrecvpsn;
169 __be32 xrcd;
170 __be32 cqn_recv;
171 __be64 db_rec_addr;
172 __be32 qkey;
173 __be32 srqn;
174 __be32 msn;
175 __be16 rq_wqe_counter;
176 __be16 sq_wqe_counter;
177 u32 reserved3[2];
178 __be32 param3;
179 __be32 nummmcpeers_basemkey;
180 u8 log_page_size;
181 u8 reserved4[2];
182 u8 mtt_base_addr_h;
183 __be32 mtt_base_addr_l;
184 u32 reserved5[10];
185};
186
187
188#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
189
190enum {
191 MLX4_WQE_CTRL_NEC = 1 << 29,
192 MLX4_WQE_CTRL_FENCE = 1 << 6,
193 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
194 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
195 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
196 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
197 MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
198 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
199 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
200};
201
202struct mlx4_wqe_ctrl_seg {
203 __be32 owner_opcode;
204 __be16 vlan_tag;
205 u8 ins_vlan;
206 u8 fence_size;
207
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213
214
215
216 union {
217 __be32 srcrb_flags;
218 __be16 srcrb_flags16[2];
219 };
220
221
222
223
224
225 __be32 imm;
226};
227
228enum {
229 MLX4_WQE_MLX_VL15 = 1 << 17,
230 MLX4_WQE_MLX_SLR = 1 << 16
231};
232
233struct mlx4_wqe_mlx_seg {
234 u8 owner;
235 u8 reserved1[2];
236 u8 opcode;
237 __be16 sched_prio;
238 u8 reserved2;
239 u8 size;
240
241
242
243
244
245
246
247
248
249 __be32 flags;
250 __be16 rlid;
251 u16 reserved3;
252};
253
254struct mlx4_wqe_datagram_seg {
255 __be32 av[8];
256 __be32 dqpn;
257 __be32 qkey;
258 __be16 vlan;
259 u8 mac[6];
260};
261
262struct mlx4_wqe_lso_seg {
263 __be32 mss_hdr_size;
264 __be32 header[0];
265};
266
267struct mlx4_wqe_bind_seg {
268 __be32 flags1;
269 __be32 flags2;
270 __be32 new_rkey;
271 __be32 lkey;
272 __be64 addr;
273 __be64 length;
274};
275
276enum {
277 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
278 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
279 MLX4_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
280 MLX4_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
281 MLX4_WQE_FMR_PERM_ATOMIC = 1 << 31
282};
283
284struct mlx4_wqe_fmr_seg {
285 __be32 flags;
286 __be32 mem_key;
287 __be64 buf_list;
288 __be64 start_addr;
289 __be64 reg_len;
290 __be32 offset;
291 __be32 page_size;
292 u32 reserved[2];
293};
294
295struct mlx4_wqe_fmr_ext_seg {
296 u8 flags;
297 u8 reserved;
298 __be16 app_mask;
299 __be16 wire_app_tag;
300 __be16 mem_app_tag;
301 __be32 wire_ref_tag_base;
302 __be32 mem_ref_tag_base;
303};
304
305struct mlx4_wqe_local_inval_seg {
306 __be32 flags;
307 u32 reserved1;
308 __be32 mem_key;
309 u32 reserved2[2];
310 __be32 guest_id;
311 __be64 pa;
312};
313
314struct mlx4_wqe_raddr_seg {
315 __be64 raddr;
316 __be32 rkey;
317 u32 reserved;
318};
319
320struct mlx4_wqe_atomic_seg {
321 __be64 swap_add;
322 __be64 compare;
323};
324
325struct mlx4_wqe_masked_atomic_seg {
326 __be64 swap_add;
327 __be64 compare;
328 __be64 swap_add_mask;
329 __be64 compare_mask;
330};
331
332struct mlx4_wqe_data_seg {
333 __be32 byte_count;
334 __be32 lkey;
335 __be64 addr;
336};
337
338enum {
339 MLX4_INLINE_ALIGN = 64,
340 MLX4_INLINE_SEG = 1 << 31,
341};
342
343struct mlx4_wqe_inline_seg {
344 __be32 byte_count;
345};
346
347int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
348 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
349 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
350 int sqd_event, struct mlx4_qp *qp);
351
352int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
353 struct mlx4_qp_context *context);
354
355int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
356 struct mlx4_qp_context *context,
357 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
358
359static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
360{
361 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
362}
363
364void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
365
366#endif
367