LXR linux/arch/mips/include/asm/processor.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 1994 Waldorf GMBH
   7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8 * Copyright (C) 1996 Paul M. Antoine
   9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10 */
  11#ifndef _ASM_PROCESSOR_H
  12#define _ASM_PROCESSOR_H
  13
  14#include <linux/cpumask.h>
  15#include <linux/threads.h>
  16
  17#include <asm/cachectl.h>
  18#include <asm/cpu.h>
  19#include <asm/cpu-info.h>
  20#include <asm/mipsregs.h>
  21#include <asm/prefetch.h>
  22
  23/*
  24 * Return current * instruction pointer ("program counter").
  25 */
  26#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  27
  28/*
  29 * System setup and hardware flags..
  30 */
  31extern void (*cpu_wait)(void);
  32
  33extern unsigned int vced_count, vcei_count;
  34
  35/*
  36 * MIPS does have an arch_pick_mmap_layout()
  37 */
  38#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
  39
  40/*
  41 * A special page (the vdso) is mapped into all processes at the very
  42 * top of the virtual memory space.
  43 */
  44#define SPECIAL_PAGES_SIZE PAGE_SIZE
  45
  46#ifdef CONFIG_32BIT
  47/*
  48 * User space process size: 2GB. This is hardcoded into a few places,
  49 * so don't change it unless you know what you are doing.
  50 */
  51#define TASK_SIZE       0x7fff8000UL
  52
  53#ifdef __KERNEL__
  54#define STACK_TOP_MAX   TASK_SIZE
  55#endif
  56
  57#define TASK_IS_32BIT_ADDR 1
  58
  59#endif
  60
  61#ifdef CONFIG_64BIT
  62/*
  63 * User space process size: 1TB. This is hardcoded into a few places,
  64 * so don't change it unless you know what you are doing.  TASK_SIZE
  65 * is limited to 1TB by the R4000 architecture; R10000 and better can
  66 * support 16TB; the architectural reserve for future expansion is
  67 * 8192EB ...
  68 */
  69#define TASK_SIZE32     0x7fff8000UL
  70#define TASK_SIZE64     0x10000000000UL
  71#define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  72
  73#ifdef __KERNEL__
  74#define STACK_TOP_MAX   TASK_SIZE64
  75#endif
  76
  77
  78#define TASK_SIZE_OF(tsk)                                               \
  79        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
  80
  81#define TASK_IS_32BIT_ADDR test_thread_flag(TIF_32BIT_ADDR)
  82
  83#endif
  84
  85#define STACK_TOP       ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE)
  86
  87/*
  88 * This decides where the kernel will search for a free chunk of vm
  89 * space during mmap's.
  90 */
  91#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE / 3)
  92
  93
  94#define NUM_FPU_REGS    32
  95
  96typedef __u64 fpureg_t;
  97
  98/*
  99 * It would be nice to add some more fields for emulator statistics, but there
 100 * are a number of fixed offsets in offset.h and elsewhere that would have to
 101 * be recalculated by hand.  So the additional information will be private to
 102 * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 103 */
 104
 105struct mips_fpu_struct {
 106        fpureg_t        fpr[NUM_FPU_REGS];
 107        unsigned int    fcr31;
 108};
 109
 110#define NUM_DSP_REGS   6
 111
 112typedef __u32 dspreg_t;
 113
 114struct mips_dsp_state {
 115        dspreg_t        dspr[NUM_DSP_REGS];
 116        unsigned int    dspcontrol;
 117};
 118
 119#define INIT_CPUMASK { \
 120        {0,} \
 121}
 122
 123struct mips3264_watch_reg_state {
 124        /* The width of watchlo is 32 in a 32 bit kernel and 64 in a
 125           64 bit kernel.  We use unsigned long as it has the same
 126           property. */
 127        unsigned long watchlo[NUM_WATCH_REGS];
 128        /* Only the mask and IRW bits from watchhi. */
 129        u16 watchhi[NUM_WATCH_REGS];
 130};
 131
 132union mips_watch_reg_state {
 133        struct mips3264_watch_reg_state mips3264;
 134};
 135
 136#ifdef CONFIG_CPU_CAVIUM_OCTEON
 137
 138struct octeon_cop2_state {
 139        /* DMFC2 rt, 0x0201 */
 140        unsigned long   cop2_crc_iv;
 141        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
 142        unsigned long   cop2_crc_length;
 143        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
 144        unsigned long   cop2_crc_poly;
 145        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
 146        unsigned long   cop2_llm_dat[2];
 147       /* DMFC2 rt, 0x0084 */
 148        unsigned long   cop2_3des_iv;
 149        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
 150        unsigned long   cop2_3des_key[3];
 151        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
 152        unsigned long   cop2_3des_result;
 153        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
 154        unsigned long   cop2_aes_inp0;
 155        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
 156        unsigned long   cop2_aes_iv[2];
 157        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
 158         * rt, 0x0107 */
 159        unsigned long   cop2_aes_key[4];
 160        /* DMFC2 rt, 0x0110 */
 161        unsigned long   cop2_aes_keylen;
 162        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
 163        unsigned long   cop2_aes_result[2];
 164        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
 165         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
 166         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
 167         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
 168         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
 169        unsigned long   cop2_hsh_datw[15];
 170        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
 171         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
 172         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
 173        unsigned long   cop2_hsh_ivw[8];
 174        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
 175        unsigned long   cop2_gfm_mult[2];
 176        /* DMFC2 rt, 0x025E - Pass2 */
 177        unsigned long   cop2_gfm_poly;
 178        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
 179        unsigned long   cop2_gfm_result[2];
 180};
 181#define INIT_OCTEON_COP2 {0,}
 182
 183struct octeon_cvmseg_state {
 184        unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
 185                            [cpu_dcache_line_size() / sizeof(unsigned long)];
 186};
 187
 188#endif
 189
 190typedef struct {
 191        unsigned long seg;
 192} mm_segment_t;
 193
 194#define ARCH_MIN_TASKALIGN      8
 195
 196struct mips_abi;
 197
 198/*
 199 * If you change thread_struct remember to change the #defines below too!
 200 */
 201struct thread_struct {
 202        /* Saved main processor registers. */
 203        unsigned long reg16;
 204        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 205        unsigned long reg29, reg30, reg31;
 206
 207        /* Saved cp0 stuff. */
 208        unsigned long cp0_status;
 209
 210        /* Saved fpu/fpu emulator stuff. */
 211        struct mips_fpu_struct fpu;
 212#ifdef CONFIG_MIPS_MT_FPAFF
 213        /* Emulated instruction count */
 214        unsigned long emulated_fp;
 215        /* Saved per-thread scheduler affinity mask */
 216        cpumask_t user_cpus_allowed;
 217#endif /* CONFIG_MIPS_MT_FPAFF */
 218
 219        /* Saved state of the DSP ASE, if available. */
 220        struct mips_dsp_state dsp;
 221
 222        /* Saved watch register state, if available. */
 223        union mips_watch_reg_state watch;
 224
 225        /* Other stuff associated with the thread. */
 226        unsigned long cp0_badvaddr;     /* Last user fault */
 227        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 228        unsigned long error_code;
 229        unsigned long irix_trampoline;  /* Wheee... */
 230        unsigned long irix_oldctx;
 231#ifdef CONFIG_CPU_CAVIUM_OCTEON
 232    struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
 233    struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
 234#endif
 235        struct mips_abi *abi;
 236};
 237
 238#ifdef CONFIG_MIPS_MT_FPAFF
 239#define FPAFF_INIT                                              \
 240        .emulated_fp                    = 0,                    \
 241        .user_cpus_allowed              = INIT_CPUMASK,
 242#else
 243#define FPAFF_INIT
 244#endif /* CONFIG_MIPS_MT_FPAFF */
 245
 246#ifdef CONFIG_CPU_CAVIUM_OCTEON
 247#define OCTEON_INIT                                             \
 248        .cp2                    = INIT_OCTEON_COP2,
 249#else
 250#define OCTEON_INIT
 251#endif /* CONFIG_CPU_CAVIUM_OCTEON */
 252
 253#define INIT_THREAD  {                                          \
 254        /*                                                      \
 255         * Saved main processor registers                       \
 256         */                                                     \
 257        .reg16                  = 0,                            \
 258        .reg17                  = 0,                            \
 259        .reg18                  = 0,                            \
 260        .reg19                  = 0,                            \
 261        .reg20                  = 0,                            \
 262        .reg21                  = 0,                            \
 263        .reg22                  = 0,                            \
 264        .reg23                  = 0,                            \
 265        .reg29                  = 0,                            \
 266        .reg30                  = 0,                            \
 267        .reg31                  = 0,                            \
 268        /*                                                      \
 269         * Saved cp0 stuff                                      \
 270         */                                                     \
 271        .cp0_status             = 0,                            \
 272        /*                                                      \
 273         * Saved FPU/FPU emulator stuff                         \
 274         */                                                     \
 275        .fpu                    = {                             \
 276                .fpr            = {0,},                         \
 277                .fcr31          = 0,                            \
 278        },                                                      \
 279        /*                                                      \
 280         * FPU affinity state (null if not FPAFF)               \
 281         */                                                     \
 282        FPAFF_INIT                                              \
 283        /*                                                      \
 284         * Saved DSP stuff                                      \
 285         */                                                     \
 286        .dsp                    = {                             \
 287                .dspr           = {0, },                        \
 288                .dspcontrol     = 0,                            \
 289        },                                                      \
 290        /*                                                      \
 291         * saved watch register stuff                           \
 292         */                                                     \
 293        .watch = {{{0,},},},                                    \
 294        /*                                                      \
 295         * Other stuff associated with the process              \
 296         */                                                     \
 297        .cp0_badvaddr           = 0,                            \
 298        .cp0_baduaddr           = 0,                            \
 299        .error_code             = 0,                            \
 300        .irix_trampoline        = 0,                            \
 301        .irix_oldctx            = 0,                            \
 302        /*                                                      \
 303         * Cavium Octeon specifics (null if not Octeon)         \
 304         */                                                     \
 305        OCTEON_INIT                                             \
 306}
 307
 308struct task_struct;
 309
 310/* Free all resources held by a thread. */
 311#define release_thread(thread) do { } while(0)
 312
 313extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 314
 315extern unsigned long thread_saved_pc(struct task_struct *tsk);
 316
 317/*
 318 * Do necessary setup to start up a newly executed thread.
 319 */
 320extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 321
 322unsigned long get_wchan(struct task_struct *p);
 323
 324#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
 325                         THREAD_SIZE - 32 - sizeof(struct pt_regs))
 326#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk))
 327#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
 328#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
 329#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
 330
 331#define cpu_relax()     barrier()
 332
 333/*
 334 * Return_address is a replacement for __builtin_return_address(count)
 335 * which on certain architectures cannot reasonably be implemented in GCC
 336 * (MIPS, Alpha) or is unusable with -fomit-frame-pointer (i386).
 337 * Note that __builtin_return_address(x>=1) is forbidden because GCC
 338 * aborts compilation on some CPUs.  It's simply not possible to unwind
 339 * some CPU's stackframes.
 340 *
 341 * __builtin_return_address works only for non-leaf functions.  We avoid the
 342 * overhead of a function call by forcing the compiler to save the return
 343 * address register on the stack.
 344 */
 345#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 346
 347#ifdef CONFIG_CPU_HAS_PREFETCH
 348
 349#define ARCH_HAS_PREFETCH
 350#define prefetch(x) __builtin_prefetch((x), 0, 1)
 351
 352#define ARCH_HAS_PREFETCHW
 353#define prefetchw(x) __builtin_prefetch((x), 1, 1)
 354
 355/*
 356 * See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
 357 * systems.
 358 */
 359#define __ARCH_WANT_UNLOCKED_CTXSW
 360
 361#endif
 362
 363#endif /* _ASM_PROCESSOR_H */
 364