1#ifndef _ASM_X86_ACPI_H
2#define _ASM_X86_ACPI_H
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26#include <acpi/pdc_intel.h>
27
28#include <asm/numa.h>
29#include <asm/processor.h>
30#include <asm/mmu.h>
31#include <asm/mpspec.h>
32#include <asm/realmode.h>
33
34#define COMPILER_DEPENDENT_INT64 long long
35#define COMPILER_DEPENDENT_UINT64 unsigned long long
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44
45#define ACPI_SYSTEM_XFACE
46#define ACPI_EXTERNAL_XFACE
47#define ACPI_INTERNAL_XFACE
48#define ACPI_INTERNAL_VAR_XFACE
49
50
51
52#define ACPI_ASM_MACROS
53#define BREAKPOINT3
54#define ACPI_DISABLE_IRQS() local_irq_disable()
55#define ACPI_ENABLE_IRQS() local_irq_enable()
56#define ACPI_FLUSH_CPU_CACHE() wbinvd()
57
58int __acpi_acquire_global_lock(unsigned int *lock);
59int __acpi_release_global_lock(unsigned int *lock);
60
61#define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
62 ((Acq) = __acpi_acquire_global_lock(&facs->global_lock))
63
64#define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
65 ((Acq) = __acpi_release_global_lock(&facs->global_lock))
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69
70#define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \
71 asm("divl %2;" \
72 : "=a"(q32), "=d"(r32) \
73 : "r"(d32), \
74 "0"(n_lo), "1"(n_hi))
75
76
77#define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
78 asm("shrl $1,%2 ;" \
79 "rcrl $1,%3;" \
80 : "=r"(n_hi), "=r"(n_lo) \
81 : "0"(n_hi), "1"(n_lo))
82
83#ifdef CONFIG_ACPI
84extern int acpi_lapic;
85extern int acpi_ioapic;
86extern int acpi_noirq;
87extern int acpi_strict;
88extern int acpi_disabled;
89extern int acpi_pci_disabled;
90extern int acpi_skip_timer_override;
91extern int acpi_use_timer_override;
92extern int acpi_fix_pin2_polarity;
93
94extern u8 acpi_sci_flags;
95extern int acpi_sci_override_gsi;
96void acpi_pic_sci_set_trigger(unsigned int, u16);
97
98extern int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
99 int trigger, int polarity);
100
101static inline void disable_acpi(void)
102{
103 acpi_disabled = 1;
104 acpi_pci_disabled = 1;
105 acpi_noirq = 1;
106}
107
108extern int acpi_gsi_to_irq(u32 gsi, unsigned int *irq);
109
110static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
111static inline void acpi_disable_pci(void)
112{
113 acpi_pci_disabled = 1;
114 acpi_noirq_set();
115}
116
117
118extern int acpi_suspend_lowlevel(void);
119
120
121#define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start))
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125
126static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
127{
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134 if (boot_cpu_data.x86 == 0x0F &&
135 boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
136 boot_cpu_data.x86_model <= 0x05 &&
137 boot_cpu_data.x86_mask < 0x0A)
138 return 1;
139 else if (amd_e400_c1e_detected)
140 return 1;
141 else
142 return max_cstate;
143}
144
145static inline bool arch_has_acpi_pdc(void)
146{
147 struct cpuinfo_x86 *c = &cpu_data(0);
148 return (c->x86_vendor == X86_VENDOR_INTEL ||
149 c->x86_vendor == X86_VENDOR_CENTAUR);
150}
151
152static inline void arch_acpi_set_pdc_bits(u32 *buf)
153{
154 struct cpuinfo_x86 *c = &cpu_data(0);
155
156 buf[2] |= ACPI_PDC_C_CAPABILITY_SMP;
157
158 if (cpu_has(c, X86_FEATURE_EST))
159 buf[2] |= ACPI_PDC_EST_CAPABILITY_SWSMP;
160
161 if (cpu_has(c, X86_FEATURE_ACPI))
162 buf[2] |= ACPI_PDC_T_FFH;
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166
167 if (!cpu_has(c, X86_FEATURE_MWAIT))
168 buf[2] &= ~(ACPI_PDC_C_C2C3_FFH);
169}
170
171#else
172
173#define acpi_lapic 0
174#define acpi_ioapic 0
175static inline void acpi_noirq_set(void) { }
176static inline void acpi_disable_pci(void) { }
177static inline void disable_acpi(void) { }
178
179#endif
180
181#define ARCH_HAS_POWER_INIT 1
182
183#ifdef CONFIG_ACPI_NUMA
184extern int acpi_numa;
185extern int x86_acpi_numa_init(void);
186#endif
187
188#define acpi_unlazy_tlb(x) leave_mm(x)
189
190#endif
191