1#include <linux/module.h>
2#include <linux/slab.h>
3#include <linux/pci.h>
4#include <linux/perf_event.h>
5#include "perf_event.h"
6
7#define UNCORE_PMU_NAME_LEN 32
8#define UNCORE_PMU_HRTIMER_INTERVAL (60LL * NSEC_PER_SEC)
9
10#define UNCORE_FIXED_EVENT 0xff
11#define UNCORE_PMC_IDX_MAX_GENERIC 8
12#define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC
13#define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1)
14
15#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
16
17
18#define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
19#define SNB_UNC_CTL_UMASK_MASK 0x0000ff00
20#define SNB_UNC_CTL_EDGE_DET (1 << 18)
21#define SNB_UNC_CTL_EN (1 << 22)
22#define SNB_UNC_CTL_INVERT (1 << 23)
23#define SNB_UNC_CTL_CMASK_MASK 0x1f000000
24#define NHM_UNC_CTL_CMASK_MASK 0xff000000
25#define NHM_UNC_FIXED_CTR_CTL_EN (1 << 0)
26
27#define SNB_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
28 SNB_UNC_CTL_UMASK_MASK | \
29 SNB_UNC_CTL_EDGE_DET | \
30 SNB_UNC_CTL_INVERT | \
31 SNB_UNC_CTL_CMASK_MASK)
32
33#define NHM_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
34 SNB_UNC_CTL_UMASK_MASK | \
35 SNB_UNC_CTL_EDGE_DET | \
36 SNB_UNC_CTL_INVERT | \
37 NHM_UNC_CTL_CMASK_MASK)
38
39
40#define SNB_UNC_PERF_GLOBAL_CTL 0x391
41#define SNB_UNC_FIXED_CTR_CTRL 0x394
42#define SNB_UNC_FIXED_CTR 0x395
43
44
45#define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
46#define SNB_UNC_GLOBAL_CTL_EN (1 << 29)
47
48
49#define SNB_UNC_CBO_0_PERFEVTSEL0 0x700
50#define SNB_UNC_CBO_0_PER_CTR0 0x706
51#define SNB_UNC_CBO_MSR_OFFSET 0x10
52
53
54#define NHM_UNC_PERF_GLOBAL_CTL 0x391
55#define NHM_UNC_FIXED_CTR 0x394
56#define NHM_UNC_FIXED_CTR_CTRL 0x395
57
58
59#define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
60#define NHM_UNC_GLOBAL_CTL_EN_FC (1ULL << 32)
61
62
63#define NHM_UNC_PERFEVTSEL0 0x3c0
64#define NHM_UNC_UNCORE_PMC0 0x3b0
65
66
67#define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
68#define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1)
69#define SNBEP_PMON_BOX_CTL_FRZ (1 << 8)
70#define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16)
71#define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \
72 SNBEP_PMON_BOX_CTL_RST_CTRS | \
73 SNBEP_PMON_BOX_CTL_FRZ_EN)
74
75#define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
76#define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
77#define SNBEP_PMON_CTL_RST (1 << 17)
78#define SNBEP_PMON_CTL_EDGE_DET (1 << 18)
79#define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21)
80#define SNBEP_PMON_CTL_EN (1 << 22)
81#define SNBEP_PMON_CTL_INVERT (1 << 23)
82#define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
83#define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \
84 SNBEP_PMON_CTL_UMASK_MASK | \
85 SNBEP_PMON_CTL_EDGE_DET | \
86 SNBEP_PMON_CTL_INVERT | \
87 SNBEP_PMON_CTL_TRESH_MASK)
88
89
90#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
91#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \
92 (SNBEP_PMON_CTL_EV_SEL_MASK | \
93 SNBEP_PMON_CTL_UMASK_MASK | \
94 SNBEP_PMON_CTL_EDGE_DET | \
95 SNBEP_PMON_CTL_INVERT | \
96 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
97
98#define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19)
99#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
100 SNBEP_CBO_PMON_CTL_TID_EN)
101
102
103#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
104#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
105#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30)
106#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31)
107#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \
108 (SNBEP_PMON_CTL_EV_SEL_MASK | \
109 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
110 SNBEP_PMON_CTL_EDGE_DET | \
111 SNBEP_PMON_CTL_INVERT | \
112 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
113 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
114 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
115
116#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
117 (SNBEP_PMON_RAW_EVENT_MASK | \
118 SNBEP_PMON_CTL_EV_SEL_EXT)
119
120
121#define SNBEP_PCI_PMON_BOX_CTL 0xf4
122#define SNBEP_PCI_PMON_CTL0 0xd8
123
124#define SNBEP_PCI_PMON_CTR0 0xa0
125
126
127#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40
128#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44
129#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48
130
131#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0
132#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0
133
134#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228
135#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c
136#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238
137#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c
138
139
140#define SNBEP_U_MSR_PMON_CTR0 0xc16
141#define SNBEP_U_MSR_PMON_CTL0 0xc10
142
143#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08
144#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09
145
146
147#define SNBEP_C0_MSR_PMON_CTR0 0xd16
148#define SNBEP_C0_MSR_PMON_CTL0 0xd10
149#define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
150#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
151#define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK 0xfffffc1f
152#define SNBEP_CBO_MSR_OFFSET 0x20
153
154
155#define SNBEP_PCU_MSR_PMON_CTR0 0xc36
156#define SNBEP_PCU_MSR_PMON_CTL0 0xc30
157#define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
158#define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
159#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff
160#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
161#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
162
163
164#define NHMEX_PMON_CTL_EV_SEL_MASK 0x000000ff
165#define NHMEX_PMON_CTL_UMASK_MASK 0x0000ff00
166#define NHMEX_PMON_CTL_EN_BIT0 (1 << 0)
167#define NHMEX_PMON_CTL_EDGE_DET (1 << 18)
168#define NHMEX_PMON_CTL_PMI_EN (1 << 20)
169#define NHMEX_PMON_CTL_EN_BIT22 (1 << 22)
170#define NHMEX_PMON_CTL_INVERT (1 << 23)
171#define NHMEX_PMON_CTL_TRESH_MASK 0xff000000
172#define NHMEX_PMON_RAW_EVENT_MASK (NHMEX_PMON_CTL_EV_SEL_MASK | \
173 NHMEX_PMON_CTL_UMASK_MASK | \
174 NHMEX_PMON_CTL_EDGE_DET | \
175 NHMEX_PMON_CTL_INVERT | \
176 NHMEX_PMON_CTL_TRESH_MASK)
177
178
179#define NHMEX_U_MSR_PMON_GLOBAL_CTL 0xc00
180#define NHMEX_U_MSR_PMON_CTR 0xc11
181#define NHMEX_U_MSR_PMON_EV_SEL 0xc10
182
183#define NHMEX_U_PMON_GLOBAL_EN (1 << 0)
184#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL 0x0000001e
185#define NHMEX_U_PMON_GLOBAL_EN_ALL (1 << 28)
186#define NHMEX_U_PMON_GLOBAL_RST_ALL (1 << 29)
187#define NHMEX_U_PMON_GLOBAL_FRZ_ALL (1 << 31)
188
189#define NHMEX_U_PMON_RAW_EVENT_MASK \
190 (NHMEX_PMON_CTL_EV_SEL_MASK | \
191 NHMEX_PMON_CTL_EDGE_DET)
192
193
194#define NHMEX_C0_MSR_PMON_GLOBAL_CTL 0xd00
195#define NHMEX_C0_MSR_PMON_CTR0 0xd11
196#define NHMEX_C0_MSR_PMON_EV_SEL0 0xd10
197#define NHMEX_C_MSR_OFFSET 0x20
198
199
200#define NHMEX_B0_MSR_PMON_GLOBAL_CTL 0xc20
201#define NHMEX_B0_MSR_PMON_CTR0 0xc31
202#define NHMEX_B0_MSR_PMON_CTL0 0xc30
203#define NHMEX_B_MSR_OFFSET 0x40
204#define NHMEX_B0_MSR_MATCH 0xe45
205#define NHMEX_B0_MSR_MASK 0xe46
206#define NHMEX_B1_MSR_MATCH 0xe4d
207#define NHMEX_B1_MSR_MASK 0xe4e
208
209#define NHMEX_B_PMON_CTL_EN (1 << 0)
210#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT 1
211#define NHMEX_B_PMON_CTL_EV_SEL_MASK \
212 (0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)
213#define NHMEX_B_PMON_CTR_SHIFT 6
214#define NHMEX_B_PMON_CTR_MASK \
215 (0x3 << NHMEX_B_PMON_CTR_SHIFT)
216#define NHMEX_B_PMON_RAW_EVENT_MASK \
217 (NHMEX_B_PMON_CTL_EV_SEL_MASK | \
218 NHMEX_B_PMON_CTR_MASK)
219
220
221#define NHMEX_S0_MSR_PMON_GLOBAL_CTL 0xc40
222#define NHMEX_S0_MSR_PMON_CTR0 0xc51
223#define NHMEX_S0_MSR_PMON_CTL0 0xc50
224#define NHMEX_S_MSR_OFFSET 0x80
225#define NHMEX_S0_MSR_MM_CFG 0xe48
226#define NHMEX_S0_MSR_MATCH 0xe49
227#define NHMEX_S0_MSR_MASK 0xe4a
228#define NHMEX_S1_MSR_MM_CFG 0xe58
229#define NHMEX_S1_MSR_MATCH 0xe59
230#define NHMEX_S1_MSR_MASK 0xe5a
231
232#define NHMEX_S_PMON_MM_CFG_EN (0x1ULL << 63)
233#define NHMEX_S_EVENT_TO_R_PROG_EV 0
234
235
236#define NHMEX_M0_MSR_GLOBAL_CTL 0xca0
237#define NHMEX_M0_MSR_PMU_DSP 0xca5
238#define NHMEX_M0_MSR_PMU_ISS 0xca6
239#define NHMEX_M0_MSR_PMU_MAP 0xca7
240#define NHMEX_M0_MSR_PMU_MSC_THR 0xca8
241#define NHMEX_M0_MSR_PMU_PGT 0xca9
242#define NHMEX_M0_MSR_PMU_PLD 0xcaa
243#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC 0xcab
244#define NHMEX_M0_MSR_PMU_CTL0 0xcb0
245#define NHMEX_M0_MSR_PMU_CNT0 0xcb1
246#define NHMEX_M_MSR_OFFSET 0x40
247#define NHMEX_M0_MSR_PMU_MM_CFG 0xe54
248#define NHMEX_M1_MSR_PMU_MM_CFG 0xe5c
249
250#define NHMEX_M_PMON_MM_CFG_EN (1ULL << 63)
251#define NHMEX_M_PMON_ADDR_MATCH_MASK 0x3ffffffffULL
252#define NHMEX_M_PMON_ADDR_MASK_MASK 0x7ffffffULL
253#define NHMEX_M_PMON_ADDR_MASK_SHIFT 34
254
255#define NHMEX_M_PMON_CTL_EN (1 << 0)
256#define NHMEX_M_PMON_CTL_PMI_EN (1 << 1)
257#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT 2
258#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK \
259 (0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)
260#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT 4
261#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK \
262 (0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)
263#define NHMEX_M_PMON_CTL_WRAP_MODE (1 << 6)
264#define NHMEX_M_PMON_CTL_FLAG_MODE (1 << 7)
265#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT 9
266#define NHMEX_M_PMON_CTL_INC_SEL_MASK \
267 (0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
268#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT 19
269#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK \
270 (0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)
271#define NHMEX_M_PMON_RAW_EVENT_MASK \
272 (NHMEX_M_PMON_CTL_COUNT_MODE_MASK | \
273 NHMEX_M_PMON_CTL_STORAGE_MODE_MASK | \
274 NHMEX_M_PMON_CTL_WRAP_MODE | \
275 NHMEX_M_PMON_CTL_FLAG_MODE | \
276 NHMEX_M_PMON_CTL_INC_SEL_MASK | \
277 NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
278
279#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 11) - 1) | (1 << 23))
280#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (11 + 3 * (n)))
281
282#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK (((1 << 12) - 1) | (1 << 24))
283#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n) (0x7 << (12 + 3 * (n)))
284
285
286
287
288
289#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
290#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \
291 NHMEX_M_PMON_CTL_FLAG_MODE)
292#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \
293 NHMEX_M_PMON_CTL_FLAG_MODE)
294#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \
295 NHMEX_M_PMON_CTL_FLAG_MODE)
296#define MBOX_INC_SEL_EXTAR_REG(c, r) \
297 EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \
298 MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)
299#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \
300 EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \
301 MBOX_SET_FLAG_SEL_MASK, \
302 (u64)-1, NHMEX_M_##r)
303
304
305#define NHMEX_R_MSR_GLOBAL_CTL 0xe00
306#define NHMEX_R_MSR_PMON_CTL0 0xe10
307#define NHMEX_R_MSR_PMON_CNT0 0xe11
308#define NHMEX_R_MSR_OFFSET 0x20
309
310#define NHMEX_R_MSR_PORTN_QLX_CFG(n) \
311 ((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))
312#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n) (0xe04 + (n))
313#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n) (0xe24 + (n))
314#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n) \
315 (((n) < 4 ? 0 : 0x10) + (n) * 4)
316#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) \
317 (0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
318#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n) \
319 (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)
320#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n) \
321 (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)
322#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) \
323 (0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
324#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n) \
325 (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)
326#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n) \
327 (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)
328
329#define NHMEX_R_PMON_CTL_EN (1 << 0)
330#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT 1
331#define NHMEX_R_PMON_CTL_EV_SEL_MASK \
332 (0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)
333#define NHMEX_R_PMON_CTL_PMI_EN (1 << 6)
334#define NHMEX_R_PMON_RAW_EVENT_MASK NHMEX_R_PMON_CTL_EV_SEL_MASK
335
336
337#define NHMEX_W_MSR_GLOBAL_CTL 0xc80
338#define NHMEX_W_MSR_PMON_CNT0 0xc90
339#define NHMEX_W_MSR_PMON_EVT_SEL0 0xc91
340#define NHMEX_W_MSR_PMON_FIXED_CTR 0x394
341#define NHMEX_W_MSR_PMON_FIXED_CTL 0x395
342
343#define NHMEX_W_PMON_GLOBAL_FIXED_EN (1ULL << 31)
344
345struct intel_uncore_ops;
346struct intel_uncore_pmu;
347struct intel_uncore_box;
348struct uncore_event_desc;
349
350struct intel_uncore_type {
351 const char *name;
352 int num_counters;
353 int num_boxes;
354 int perf_ctr_bits;
355 int fixed_ctr_bits;
356 unsigned perf_ctr;
357 unsigned event_ctl;
358 unsigned event_mask;
359 unsigned fixed_ctr;
360 unsigned fixed_ctl;
361 unsigned box_ctl;
362 unsigned msr_offset;
363 unsigned num_shared_regs:8;
364 unsigned single_fixed:1;
365 unsigned pair_ctr_ctl:1;
366 unsigned *msr_offsets;
367 struct event_constraint unconstrainted;
368 struct event_constraint *constraints;
369 struct intel_uncore_pmu *pmus;
370 struct intel_uncore_ops *ops;
371 struct uncore_event_desc *event_descs;
372 const struct attribute_group *attr_groups[3];
373};
374
375#define format_group attr_groups[0]
376
377struct intel_uncore_ops {
378 void (*init_box)(struct intel_uncore_box *);
379 void (*disable_box)(struct intel_uncore_box *);
380 void (*enable_box)(struct intel_uncore_box *);
381 void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
382 void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
383 u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
384 int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
385 struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
386 struct perf_event *);
387 void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
388};
389
390struct intel_uncore_pmu {
391 struct pmu pmu;
392 char name[UNCORE_PMU_NAME_LEN];
393 int pmu_idx;
394 int func_id;
395 struct intel_uncore_type *type;
396 struct intel_uncore_box ** __percpu box;
397 struct list_head box_list;
398};
399
400struct intel_uncore_extra_reg {
401 raw_spinlock_t lock;
402 u64 config, config1, config2;
403 atomic_t ref;
404};
405
406struct intel_uncore_box {
407 int phys_id;
408 int n_active;
409 int n_events;
410 int cpu;
411 unsigned long flags;
412 atomic_t refcnt;
413 struct perf_event *events[UNCORE_PMC_IDX_MAX];
414 struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
415 unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
416 u64 tags[UNCORE_PMC_IDX_MAX];
417 struct pci_dev *pci_dev;
418 struct intel_uncore_pmu *pmu;
419 struct hrtimer hrtimer;
420 struct list_head list;
421 struct intel_uncore_extra_reg shared_regs[0];
422};
423
424#define UNCORE_BOX_FLAG_INITIATED 0
425
426struct uncore_event_desc {
427 struct kobj_attribute attr;
428 const char *config;
429};
430
431#define INTEL_UNCORE_EVENT_DESC(_name, _config) \
432{ \
433 .attr = __ATTR(_name, 0444, uncore_event_show, NULL), \
434 .config = _config, \
435}
436
437#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \
438static ssize_t __uncore_##_var##_show(struct kobject *kobj, \
439 struct kobj_attribute *attr, \
440 char *page) \
441{ \
442 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
443 return sprintf(page, _format "\n"); \
444} \
445static struct kobj_attribute format_attr_##_var = \
446 __ATTR(_name, 0444, __uncore_##_var##_show, NULL)
447
448
449static ssize_t uncore_event_show(struct kobject *kobj,
450 struct kobj_attribute *attr, char *buf)
451{
452 struct uncore_event_desc *event =
453 container_of(attr, struct uncore_event_desc, attr);
454 return sprintf(buf, "%s", event->config);
455}
456
457static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
458{
459 return box->pmu->type->box_ctl;
460}
461
462static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
463{
464 return box->pmu->type->fixed_ctl;
465}
466
467static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
468{
469 return box->pmu->type->fixed_ctr;
470}
471
472static inline
473unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
474{
475 return idx * 4 + box->pmu->type->event_ctl;
476}
477
478static inline
479unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
480{
481 return idx * 8 + box->pmu->type->perf_ctr;
482}
483
484static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
485{
486 struct intel_uncore_pmu *pmu = box->pmu;
487 return pmu->type->msr_offsets ?
488 pmu->type->msr_offsets[pmu->pmu_idx] :
489 pmu->type->msr_offset * pmu->pmu_idx;
490}
491
492static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
493{
494 if (!box->pmu->type->box_ctl)
495 return 0;
496 return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
497}
498
499static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
500{
501 if (!box->pmu->type->fixed_ctl)
502 return 0;
503 return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
504}
505
506static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
507{
508 return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
509}
510
511static inline
512unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
513{
514 return box->pmu->type->event_ctl +
515 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
516 uncore_msr_box_offset(box);
517}
518
519static inline
520unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
521{
522 return box->pmu->type->perf_ctr +
523 (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
524 uncore_msr_box_offset(box);
525}
526
527static inline
528unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
529{
530 if (box->pci_dev)
531 return uncore_pci_fixed_ctl(box);
532 else
533 return uncore_msr_fixed_ctl(box);
534}
535
536static inline
537unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
538{
539 if (box->pci_dev)
540 return uncore_pci_fixed_ctr(box);
541 else
542 return uncore_msr_fixed_ctr(box);
543}
544
545static inline
546unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
547{
548 if (box->pci_dev)
549 return uncore_pci_event_ctl(box, idx);
550 else
551 return uncore_msr_event_ctl(box, idx);
552}
553
554static inline
555unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
556{
557 if (box->pci_dev)
558 return uncore_pci_perf_ctr(box, idx);
559 else
560 return uncore_msr_perf_ctr(box, idx);
561}
562
563static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
564{
565 return box->pmu->type->perf_ctr_bits;
566}
567
568static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
569{
570 return box->pmu->type->fixed_ctr_bits;
571}
572
573static inline int uncore_num_counters(struct intel_uncore_box *box)
574{
575 return box->pmu->type->num_counters;
576}
577
578static inline void uncore_disable_box(struct intel_uncore_box *box)
579{
580 if (box->pmu->type->ops->disable_box)
581 box->pmu->type->ops->disable_box(box);
582}
583
584static inline void uncore_enable_box(struct intel_uncore_box *box)
585{
586 if (box->pmu->type->ops->enable_box)
587 box->pmu->type->ops->enable_box(box);
588}
589
590static inline void uncore_disable_event(struct intel_uncore_box *box,
591 struct perf_event *event)
592{
593 box->pmu->type->ops->disable_event(box, event);
594}
595
596static inline void uncore_enable_event(struct intel_uncore_box *box,
597 struct perf_event *event)
598{
599 box->pmu->type->ops->enable_event(box, event);
600}
601
602static inline u64 uncore_read_counter(struct intel_uncore_box *box,
603 struct perf_event *event)
604{
605 return box->pmu->type->ops->read_counter(box, event);
606}
607
608static inline void uncore_box_init(struct intel_uncore_box *box)
609{
610 if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
611 if (box->pmu->type->ops->init_box)
612 box->pmu->type->ops->init_box(box);
613 }
614}
615
616static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
617{
618 return (box->phys_id < 0);
619}
620
