LXR linux/drivers/gpu/drm/nouveau/nv50

   1/*
   2 * Copyright 2012 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24
  25#include "drmP.h"
  26
  27#include "nouveau_drv.h"
  28#include "nouveau_ramht.h"
  29#include "nouveau_software.h"
  30
  31#include "nv50_display.h"
  32
  33struct nv50_software_priv {
  34        struct nouveau_software_priv base;
  35};
  36
  37struct nv50_software_chan {
  38        struct nouveau_software_chan base;
  39};
  40
  41static int
  42mthd_dma_vblsem(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
  43{
  44        struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
  45        struct nouveau_gpuobj *gpuobj;
  46
  47        gpuobj = nouveau_ramht_find(chan, data);
  48        if (!gpuobj)
  49                return -ENOENT;
  50
  51        pch->base.vblank.ctxdma = gpuobj->cinst >> 4;
  52        return 0;
  53}
  54
  55static int
  56mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
  57{
  58        struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
  59        pch->base.vblank.offset = data;
  60        return 0;
  61}
  62
  63static int
  64mthd_vblsem_value(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
  65{
  66        struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
  67        pch->base.vblank.value = data;
  68        return 0;
  69}
  70
  71static int
  72mthd_vblsem_release(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
  73{
  74        struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW);
  75        struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
  76        struct drm_device *dev = chan->dev;
  77
  78        if (data > 1)
  79                return -EINVAL;
  80
  81        drm_vblank_get(dev, data);
  82
  83        pch->base.vblank.head = data;
  84        list_add(&pch->base.vblank.list, &psw->base.vblank);
  85        return 0;
  86}
  87
  88static int
  89mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
  90{
  91        nouveau_finish_page_flip(chan, NULL);
  92        return 0;
  93}
  94
  95static int
  96nv50_software_context_new(struct nouveau_channel *chan, int engine)
  97{
  98        struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW);
  99        struct nv50_display *pdisp = nv50_display(chan->dev);
 100        struct nv50_software_chan *pch;
 101        int ret = 0, i;
 102
 103        pch = kzalloc(sizeof(*pch), GFP_KERNEL);
 104        if (!pch)
 105                return -ENOMEM;
 106
 107        nouveau_software_context_new(&pch->base);
 108        pch->base.vblank.channel = chan->ramin->vinst >> 12;
 109        chan->engctx[engine] = pch;
 110
 111        /* dma objects for display sync channel semaphore blocks */
 112        for (i = 0; i < chan->dev->mode_config.num_crtc; i++) {
 113                struct nv50_display_crtc *dispc = &pdisp->crtc[i];
 114                struct nouveau_gpuobj *obj = NULL;
 115
 116                ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
 117                                             dispc->sem.bo->bo.offset, 0x1000,
 118                                             NV_MEM_ACCESS_RW,
 119                                             NV_MEM_TARGET_VRAM, &obj);
 120                if (ret)
 121                        break;
 122
 123                ret = nouveau_ramht_insert(chan, NvEvoSema0 + i, obj);
 124                nouveau_gpuobj_ref(NULL, &obj);
 125        }
 126
 127        if (ret)
 128                psw->base.base.context_del(chan, engine);
 129        return ret;
 130}
 131
 132static void
 133nv50_software_context_del(struct nouveau_channel *chan, int engine)
 134{
 135        struct nv50_software_chan *pch = chan->engctx[engine];
 136        chan->engctx[engine] = NULL;
 137        kfree(pch);
 138}
 139
 140static int
 141nv50_software_object_new(struct nouveau_channel *chan, int engine,
 142                         u32 handle, u16 class)
 143{
 144        struct drm_device *dev = chan->dev;
 145        struct nouveau_gpuobj *obj = NULL;
 146        int ret;
 147
 148        ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
 149        if (ret)
 150                return ret;
 151        obj->engine = 0;
 152        obj->class  = class;
 153
 154        ret = nouveau_ramht_insert(chan, handle, obj);
 155        nouveau_gpuobj_ref(NULL, &obj);
 156        return ret;
 157}
 158
 159static int
 160nv50_software_init(struct drm_device *dev, int engine)
 161{
 162        return 0;
 163}
 164
 165static int
 166nv50_software_fini(struct drm_device *dev, int engine, bool suspend)
 167{
 168        return 0;
 169}
 170
 171static void
 172nv50_software_destroy(struct drm_device *dev, int engine)
 173{
 174        struct nv50_software_priv *psw = nv_engine(dev, engine);
 175
 176        NVOBJ_ENGINE_DEL(dev, SW);
 177        kfree(psw);
 178}
 179
 180int
 181nv50_software_create(struct drm_device *dev)
 182{
 183        struct nv50_software_priv *psw = kzalloc(sizeof(*psw), GFP_KERNEL);
 184        if (!psw)
 185                return -ENOMEM;
 186
 187        psw->base.base.destroy = nv50_software_destroy;
 188        psw->base.base.init = nv50_software_init;
 189        psw->base.base.fini = nv50_software_fini;
 190        psw->base.base.context_new = nv50_software_context_new;
 191        psw->base.base.context_del = nv50_software_context_del;
 192        psw->base.base.object_new = nv50_software_object_new;
 193        nouveau_software_create(&psw->base);
 194
 195        NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
 196        NVOBJ_CLASS(dev, 0x506e, SW);
 197        NVOBJ_MTHD (dev, 0x506e, 0x018c, mthd_dma_vblsem);
 198        NVOBJ_MTHD (dev, 0x506e, 0x0400, mthd_vblsem_offset);
 199        NVOBJ_MTHD (dev, 0x506e, 0x0404, mthd_vblsem_value);
 200        NVOBJ_MTHD (dev, 0x506e, 0x0408, mthd_vblsem_release);
 201        NVOBJ_MTHD (dev, 0x506e, 0x0500, mthd_flip);
 202        return 0;
 203}
 204