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28#include "drmP.h"
29#include "radeon.h"
30#include "evergreend.h"
31#include "evergreen_reg_safe.h"
32#include "cayman_reg_safe.h"
33
34#define MAX(a,b) (((a)>(b))?(a):(b))
35#define MIN(a,b) (((a)<(b))?(a):(b))
36
37static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
38 struct radeon_cs_reloc **cs_reloc);
39
40struct evergreen_cs_track {
41 u32 group_size;
42 u32 nbanks;
43 u32 npipes;
44 u32 row_size;
45
46 u32 nsamples;
47 struct radeon_bo *cb_color_bo[12];
48 u32 cb_color_bo_offset[12];
49 struct radeon_bo *cb_color_fmask_bo[8];
50 struct radeon_bo *cb_color_cmask_bo[8];
51 u32 cb_color_info[12];
52 u32 cb_color_view[12];
53 u32 cb_color_pitch[12];
54 u32 cb_color_slice[12];
55 u32 cb_color_slice_idx[12];
56 u32 cb_color_attrib[12];
57 u32 cb_color_cmask_slice[8];
58 u32 cb_color_fmask_slice[8];
59 u32 cb_target_mask;
60 u32 cb_shader_mask;
61 u32 vgt_strmout_config;
62 u32 vgt_strmout_buffer_config;
63 struct radeon_bo *vgt_strmout_bo[4];
64 u32 vgt_strmout_bo_offset[4];
65 u32 vgt_strmout_size[4];
66 u32 db_depth_control;
67 u32 db_depth_view;
68 u32 db_depth_slice;
69 u32 db_depth_size;
70 u32 db_z_info;
71 u32 db_z_read_offset;
72 u32 db_z_write_offset;
73 struct radeon_bo *db_z_read_bo;
74 struct radeon_bo *db_z_write_bo;
75 u32 db_s_info;
76 u32 db_s_read_offset;
77 u32 db_s_write_offset;
78 struct radeon_bo *db_s_read_bo;
79 struct radeon_bo *db_s_write_bo;
80 bool sx_misc_kill_all_prims;
81 bool cb_dirty;
82 bool db_dirty;
83 bool streamout_dirty;
84 u32 htile_offset;
85 u32 htile_surface;
86 struct radeon_bo *htile_bo;
87};
88
89static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
90{
91 if (tiling_flags & RADEON_TILING_MACRO)
92 return ARRAY_2D_TILED_THIN1;
93 else if (tiling_flags & RADEON_TILING_MICRO)
94 return ARRAY_1D_TILED_THIN1;
95 else
96 return ARRAY_LINEAR_GENERAL;
97}
98
99static u32 evergreen_cs_get_num_banks(u32 nbanks)
100{
101 switch (nbanks) {
102 case 2:
103 return ADDR_SURF_2_BANK;
104 case 4:
105 return ADDR_SURF_4_BANK;
106 case 8:
107 default:
108 return ADDR_SURF_8_BANK;
109 case 16:
110 return ADDR_SURF_16_BANK;
111 }
112}
113
114static void evergreen_cs_track_init(struct evergreen_cs_track *track)
115{
116 int i;
117
118 for (i = 0; i < 8; i++) {
119 track->cb_color_fmask_bo[i] = NULL;
120 track->cb_color_cmask_bo[i] = NULL;
121 track->cb_color_cmask_slice[i] = 0;
122 track->cb_color_fmask_slice[i] = 0;
123 }
124
125 for (i = 0; i < 12; i++) {
126 track->cb_color_bo[i] = NULL;
127 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
128 track->cb_color_info[i] = 0;
129 track->cb_color_view[i] = 0xFFFFFFFF;
130 track->cb_color_pitch[i] = 0;
131 track->cb_color_slice[i] = 0xfffffff;
132 track->cb_color_slice_idx[i] = 0;
133 }
134 track->cb_target_mask = 0xFFFFFFFF;
135 track->cb_shader_mask = 0xFFFFFFFF;
136 track->cb_dirty = true;
137
138 track->db_depth_slice = 0xffffffff;
139 track->db_depth_view = 0xFFFFC000;
140 track->db_depth_size = 0xFFFFFFFF;
141 track->db_depth_control = 0xFFFFFFFF;
142 track->db_z_info = 0xFFFFFFFF;
143 track->db_z_read_offset = 0xFFFFFFFF;
144 track->db_z_write_offset = 0xFFFFFFFF;
145 track->db_z_read_bo = NULL;
146 track->db_z_write_bo = NULL;
147 track->db_s_info = 0xFFFFFFFF;
148 track->db_s_read_offset = 0xFFFFFFFF;
149 track->db_s_write_offset = 0xFFFFFFFF;
150 track->db_s_read_bo = NULL;
151 track->db_s_write_bo = NULL;
152 track->db_dirty = true;
153 track->htile_bo = NULL;
154 track->htile_offset = 0xFFFFFFFF;
155 track->htile_surface = 0;
156
157 for (i = 0; i < 4; i++) {
158 track->vgt_strmout_size[i] = 0;
159 track->vgt_strmout_bo[i] = NULL;
160 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
161 }
162 track->streamout_dirty = true;
163 track->sx_misc_kill_all_prims = false;
164}
165
166struct eg_surface {
167
168 unsigned nbx;
169 unsigned nby;
170 unsigned format;
171 unsigned mode;
172 unsigned nbanks;
173 unsigned bankw;
174 unsigned bankh;
175 unsigned tsplit;
176 unsigned mtilea;
177 unsigned nsamples;
178
179 unsigned bpe;
180 unsigned layer_size;
181 unsigned palign;
182 unsigned halign;
183 unsigned long base_align;
184};
185
186static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
187 struct eg_surface *surf,
188 const char *prefix)
189{
190 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
191 surf->base_align = surf->bpe;
192 surf->palign = 1;
193 surf->halign = 1;
194 return 0;
195}
196
197static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
198 struct eg_surface *surf,
199 const char *prefix)
200{
201 struct evergreen_cs_track *track = p->track;
202 unsigned palign;
203
204 palign = MAX(64, track->group_size / surf->bpe);
205 surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
206 surf->base_align = track->group_size;
207 surf->palign = palign;
208 surf->halign = 1;
209 if (surf->nbx & (palign - 1)) {
210 if (prefix) {
211 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
212 __func__, __LINE__, prefix, surf->nbx, palign);
213 }
214 return -EINVAL;
215 }
216 return 0;
217}
218
219static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
220 struct eg_surface *surf,
221 const char *prefix)
222{
223 struct evergreen_cs_track *track = p->track;
224 unsigned palign;
225
226 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
227 palign = MAX(8, palign);
228 surf->layer_size = surf->nbx * surf->nby * surf->bpe;
229 surf->base_align = track->group_size;
230 surf->palign = palign;
231 surf->halign = 8;
232 if ((surf->nbx & (palign - 1))) {
233 if (prefix) {
234 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
235 __func__, __LINE__, prefix, surf->nbx, palign,
236 track->group_size, surf->bpe, surf->nsamples);
237 }
238 return -EINVAL;
239 }
240 if ((surf->nby & (8 - 1))) {
241 if (prefix) {
242 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
243 __func__, __LINE__, prefix, surf->nby);
244 }
245 return -EINVAL;
246 }
247 return 0;
248}
249
250static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
251 struct eg_surface *surf,
252 const char *prefix)
253{
254 struct evergreen_cs_track *track = p->track;
255 unsigned palign, halign, tileb, slice_pt;
256 unsigned mtile_pr, mtile_ps, mtileb;
257
258 tileb = 64 * surf->bpe * surf->nsamples;
259 slice_pt = 1;
260 if (tileb > surf->tsplit) {
261 slice_pt = tileb / surf->tsplit;
262 }
263 tileb = tileb / slice_pt;
264
265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
267 mtileb = (palign / 8) * (halign / 8) * tileb;;
268 mtile_pr = surf->nbx / palign;
269 mtile_ps = (mtile_pr * surf->nby) / halign;
270 surf->layer_size = mtile_ps * mtileb * slice_pt;
271 surf->base_align = (palign / 8) * (halign / 8) * tileb;
272 surf->palign = palign;
273 surf->halign = halign;
274
275 if ((surf->nbx & (palign - 1))) {
276 if (prefix) {
277 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
278 __func__, __LINE__, prefix, surf->nbx, palign);
279 }
280 return -EINVAL;
281 }
282 if ((surf->nby & (halign - 1))) {
283 if (prefix) {
284 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
285 __func__, __LINE__, prefix, surf->nby, halign);
286 }
287 return -EINVAL;
288 }
289
290 return 0;
291}
292
293static int evergreen_surface_check(struct radeon_cs_parser *p,
294 struct eg_surface *surf,
295 const char *prefix)
296{
297
298 surf->bpe = r600_fmt_get_blocksize(surf->format);
299
300 switch (surf->mode) {
301 case ARRAY_LINEAR_GENERAL:
302 return evergreen_surface_check_linear(p, surf, prefix);
303 case ARRAY_LINEAR_ALIGNED:
304 return evergreen_surface_check_linear_aligned(p, surf, prefix);
305 case ARRAY_1D_TILED_THIN1:
306 return evergreen_surface_check_1d(p, surf, prefix);
307 case ARRAY_2D_TILED_THIN1:
308 return evergreen_surface_check_2d(p, surf, prefix);
309 default:
310 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
311 __func__, __LINE__, prefix, surf->mode);
312 return -EINVAL;
313 }
314 return -EINVAL;
315}
316
317static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
318 struct eg_surface *surf,
319 const char *prefix)
320{
321 switch (surf->mode) {
322 case ARRAY_2D_TILED_THIN1:
323 break;
324 case ARRAY_LINEAR_GENERAL:
325 case ARRAY_LINEAR_ALIGNED:
326 case ARRAY_1D_TILED_THIN1:
327 return 0;
328 default:
329 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
330 __func__, __LINE__, prefix, surf->mode);
331 return -EINVAL;
332 }
333
334 switch (surf->nbanks) {
335 case 0: surf->nbanks = 2; break;
336 case 1: surf->nbanks = 4; break;
337 case 2: surf->nbanks = 8; break;
338 case 3: surf->nbanks = 16; break;
339 default:
340 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
341 __func__, __LINE__, prefix, surf->nbanks);
342 return -EINVAL;
343 }
344 switch (surf->bankw) {
345 case 0: surf->bankw = 1; break;
346 case 1: surf->bankw = 2; break;
347 case 2: surf->bankw = 4; break;
348 case 3: surf->bankw = 8; break;
349 default:
350 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
351 __func__, __LINE__, prefix, surf->bankw);
352 return -EINVAL;
353 }
354 switch (surf->bankh) {
355 case 0: surf->bankh = 1; break;
356 case 1: surf->bankh = 2; break;
357 case 2: surf->bankh = 4; break;
358 case 3: surf->bankh = 8; break;
359 default:
360 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
361 __func__, __LINE__, prefix, surf->bankh);
362 return -EINVAL;
363 }
364 switch (surf->mtilea) {
365 case 0: surf->mtilea = 1; break;
366 case 1: surf->mtilea = 2; break;
367 case 2: surf->mtilea = 4; break;
368 case 3: surf->mtilea = 8; break;
369 default:
370 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
371 __func__, __LINE__, prefix, surf->mtilea);
372 return -EINVAL;
373 }
374 switch (surf->tsplit) {
375 case 0: surf->tsplit = 64; break;
376 case 1: surf->tsplit = 128; break;
377 case 2: surf->tsplit = 256; break;
378 case 3: surf->tsplit = 512; break;
379 case 4: surf->tsplit = 1024; break;
380 case 5: surf->tsplit = 2048; break;
381 case 6: surf->tsplit = 4096; break;
382 default:
383 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
384 __func__, __LINE__, prefix, surf->tsplit);
385 return -EINVAL;
386 }
387 return 0;
388}
389
390static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
391{
392 struct evergreen_cs_track *track = p->track;
393 struct eg_surface surf;
394 unsigned pitch, slice, mslice;
395 unsigned long offset;
396 int r;
397
398 mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
399 pitch = track->cb_color_pitch[id];
400 slice = track->cb_color_slice[id];
401 surf.nbx = (pitch + 1) * 8;
402 surf.nby = ((slice + 1) * 64) / surf.nbx;
403 surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
404 surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
405 surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
406 surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
407 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
408 surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
409 surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
410 surf.nsamples = 1;
411
412 if (!r600_fmt_is_valid_color(surf.format)) {
413 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
414 __func__, __LINE__, surf.format,
415 id, track->cb_color_info[id]);
416 return -EINVAL;
417 }
418
419 r = evergreen_surface_value_conv_check(p, &surf, "cb");
420 if (r) {
421 return r;
422 }
423
424 r = evergreen_surface_check(p, &surf, "cb");
425 if (r) {
426 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
427 __func__, __LINE__, id, track->cb_color_pitch[id],
428 track->cb_color_slice[id], track->cb_color_attrib[id],
429 track->cb_color_info[id]);
430 return r;
431 }
432
433 offset = track->cb_color_bo_offset[id] << 8;
434 if (offset & (surf.base_align - 1)) {
435 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
436 __func__, __LINE__, id, offset, surf.base_align);
437 return -EINVAL;
438 }
439
440 offset += surf.layer_size * mslice;
441 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
442
443
444
445
446 if (!surf.mode) {
447 volatile u32 *ib = p->ib.ptr;
448 unsigned long tmp, nby, bsize, size, min = 0;
449
450
451 if (surf.nby > 8) {
452 min = surf.nby - 8;
453 }
454 bsize = radeon_bo_size(track->cb_color_bo[id]);
455 tmp = track->cb_color_bo_offset[id] << 8;
456 for (nby = surf.nby; nby > min; nby--) {
457 size = nby * surf.nbx * surf.bpe * surf.nsamples;
458 if ((tmp + size * mslice) <= bsize) {
459 break;
460 }
461 }
462 if (nby > min) {
463 surf.nby = nby;
464 slice = ((nby * surf.nbx) / 64) - 1;
465 if (!evergreen_surface_check(p, &surf, "cb")) {
466
467 tmp += surf.layer_size * mslice;
468 if (tmp <= bsize) {
469 ib[track->cb_color_slice_idx[id]] = slice;
470 goto old_ddx_ok;
471 }
472 }
473 }
474 }
475 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
476 "offset %d, max layer %d, bo size %ld, slice %d)\n",
477 __func__, __LINE__, id, surf.layer_size,
478 track->cb_color_bo_offset[id] << 8, mslice,
479 radeon_bo_size(track->cb_color_bo[id]), slice);
480 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
481 __func__, __LINE__, surf.nbx, surf.nby,
482 surf.mode, surf.bpe, surf.nsamples,
483 surf.bankw, surf.bankh,
484 surf.tsplit, surf.mtilea);
485 return -EINVAL;
486 }
487old_ddx_ok:
488
489 return 0;
490}
491
492static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
493 unsigned nbx, unsigned nby)
494{
495 struct evergreen_cs_track *track = p->track;
496 unsigned long size;
497
498 if (track->htile_bo == NULL) {
499 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
500 __func__, __LINE__, track->db_z_info);
501 return -EINVAL;
502 }
503
504 if (G_028ABC_LINEAR(track->htile_surface)) {
505
506 nbx = round_up(nbx, 16 * 8);
507
508 nby = round_up(nby, track->npipes * 8);
509 } else {
510 switch (track->npipes) {
511 case 8:
512 nbx = round_up(nbx, 64 * 8);
513 nby = round_up(nby, 64 * 8);
514 break;
515 case 4:
516 nbx = round_up(nbx, 64 * 8);
517 nby = round_up(nby, 32 * 8);
518 break;
519 case 2:
520 nbx = round_up(nbx, 32 * 8);
521 nby = round_up(nby, 32 * 8);
522 break;
523 case 1:
524 nbx = round_up(nbx, 32 * 8);
525 nby = round_up(nby, 16 * 8);
526 break;
527 default:
528 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
529 __func__, __LINE__, track->npipes);
530 return -EINVAL;
531 }
532 }
533
534 nbx = nbx / 8;
535 nby = nby / 8;
536 size = nbx * nby * 4;
537 size += track->htile_offset;
538
539 if (size > radeon_bo_size(track->htile_bo)) {
540 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
541 __func__, __LINE__, radeon_bo_size(track->htile_bo),
542 size, nbx, nby);
543 return -EINVAL;
544 }
545 return 0;
546}
547
548static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
549{
550 struct evergreen_cs_track *track = p->track;
551 struct eg_surface surf;
552 unsigned pitch, slice, mslice;
553 unsigned long offset;
554 int r;
555
556 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
557 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
558 slice = track->db_depth_slice;
559 surf.nbx = (pitch + 1) * 8;
560 surf.nby = ((slice + 1) * 64) / surf.nbx;
561 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
562 surf.format = G_028044_FORMAT(track->db_s_info);
563 surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
564 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
565 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
566 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
567 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
568 surf.nsamples = 1;
569
570 if (surf.format != 1) {
571 dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
572 __func__, __LINE__, surf.format);
573 return -EINVAL;
574 }
575
576 surf.format = V_028C70_COLOR_8;
577
578 r = evergreen_surface_value_conv_check(p, &surf, "stencil");
579 if (r) {
580 return r;
581 }
582
583 r = evergreen_surface_check(p, &surf, NULL);
584 if (r) {
585
586
587
588
589 surf.format = V_028C70_COLOR_8_8_8_8;
590 r = evergreen_surface_check(p, &surf, "stencil");
591 if (r) {
592 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
593 __func__, __LINE__, track->db_depth_size,
594 track->db_depth_slice, track->db_s_info, track->db_z_info);
595 }
596 return r;
597 }
598
599 offset = track->db_s_read_offset << 8;
600 if (offset & (surf.base_align - 1)) {
601 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
602 __func__, __LINE__, offset, surf.base_align);
603 return -EINVAL;
604 }
605 offset += surf.layer_size * mslice;
606 if (offset > radeon_bo_size(track->db_s_read_bo)) {
607 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
608 "offset %ld, max layer %d, bo size %ld)\n",
609 __func__, __LINE__, surf.layer_size,
610 (unsigned long)track->db_s_read_offset << 8, mslice,
611 radeon_bo_size(track->db_s_read_bo));
612 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
613 __func__, __LINE__, track->db_depth_size,
614 track->db_depth_slice, track->db_s_info, track->db_z_info);
615 return -EINVAL;
616 }
617
618 offset = track->db_s_write_offset << 8;
619 if (offset & (surf.base_align - 1)) {
620 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
621 __func__, __LINE__, offset, surf.base_align);
622 return -EINVAL;
623 }
624 offset += surf.layer_size * mslice;
625 if (offset > radeon_bo_size(track->db_s_write_bo)) {
626 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
627 "offset %ld, max layer %d, bo size %ld)\n",
628 __func__, __LINE__, surf.layer_size,
629 (unsigned long)track->db_s_write_offset << 8, mslice,
630 radeon_bo_size(track->db_s_write_bo));
631 return -EINVAL;
632 }
633
634
635 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
636 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
637 if (r) {
638 return r;
639 }
640 }
641
642 return 0;
643}
644
645static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
646{
647 struct evergreen_cs_track *track = p->track;
648 struct eg_surface surf;
649 unsigned pitch, slice, mslice;
650 unsigned long offset;
651 int r;
652
653 mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
654 pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
655 slice = track->db_depth_slice;
656 surf.nbx = (pitch + 1) * 8;
657 surf.nby = ((slice + 1) * 64) / surf.nbx;
658 surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
659 surf.format = G_028040_FORMAT(track->db_z_info);
660 surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
661 surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
662 surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
663 surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
664 surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
665 surf.nsamples = 1;
666
667 switch (surf.format) {
668 case V_028040_Z_16:
669 surf.format = V_028C70_COLOR_16;
670 break;
671 case V_028040_Z_24:
672 case V_028040_Z_32_FLOAT:
673 surf.format = V_028C70_COLOR_8_8_8_8;
674 break;
675 default:
676 dev_warn(p->dev, "%s:%d depth invalid format %d\n",
677 __func__, __LINE__, surf.format);
678 return -EINVAL;
679 }
680
681 r = evergreen_surface_value_conv_check(p, &surf, "depth");
682 if (r) {
683 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
684 __func__, __LINE__, track->db_depth_size,
685 track->db_depth_slice, track->db_z_info);
686 return r;
687 }
688
689 r = evergreen_surface_check(p, &surf, "depth");
690 if (r) {
691 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
692 __func__, __LINE__, track->db_depth_size,
693 track->db_depth_slice, track->db_z_info);
694 return r;
695 }
696
697 offset = track->db_z_read_offset << 8;
698 if (offset & (surf.base_align - 1)) {
699 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
700 __func__, __LINE__, offset, surf.base_align);
701 return -EINVAL;
702 }
703 offset += surf.layer_size * mslice;
704 if (offset > radeon_bo_size(track->db_z_read_bo)) {
705 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
706 "offset %ld, max layer %d, bo size %ld)\n",
707 __func__, __LINE__, surf.layer_size,
708 (unsigned long)track->db_z_read_offset << 8, mslice,
709 radeon_bo_size(track->db_z_read_bo));
710 return -EINVAL;
711 }
712
713 offset = track->db_z_write_offset << 8;
714 if (offset & (surf.base_align - 1)) {
715 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
716 __func__, __LINE__, offset, surf.base_align);
717 return -EINVAL;
718 }
719 offset += surf.layer_size * mslice;
720 if (offset > radeon_bo_size(track->db_z_write_bo)) {
721 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
722 "offset %ld, max layer %d, bo size %ld)\n",
723 __func__, __LINE__, surf.layer_size,
724 (unsigned long)track->db_z_write_offset << 8, mslice,
725 radeon_bo_size(track->db_z_write_bo));
726 return -EINVAL;
727 }
728
729
730 if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
731 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
732 if (r) {
733 return r;
734 }
735 }
736
737 return 0;
738}
739
740static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
741 struct radeon_bo *texture,
742 struct radeon_bo *mipmap,
743 unsigned idx)
744{
745 struct eg_surface surf;
746 unsigned long toffset, moffset;
747 unsigned dim, llevel, mslice, width, height, depth, i;
748 u32 texdw[8];
749 int r;
750
751 texdw[0] = radeon_get_ib_value(p, idx + 0);
752 texdw[1] = radeon_get_ib_value(p, idx + 1);
753 texdw[2] = radeon_get_ib_value(p, idx + 2);
754 texdw[3] = radeon_get_ib_value(p, idx + 3);
755 texdw[4] = radeon_get_ib_value(p, idx + 4);
756 texdw[5] = radeon_get_ib_value(p, idx + 5);
757 texdw[6] = radeon_get_ib_value(p, idx + 6);
758 texdw[7] = radeon_get_ib_value(p, idx + 7);
759 dim = G_030000_DIM(texdw[0]);
760 llevel = G_030014_LAST_LEVEL(texdw[5]);
761 mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
762 width = G_030000_TEX_WIDTH(texdw[0]) + 1;
763 height = G_030004_TEX_HEIGHT(texdw[1]) + 1;
764 depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
765 surf.format = G_03001C_DATA_FORMAT(texdw[7]);
766 surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
767 surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
768 surf.nby = r600_fmt_get_nblocksy(surf.format, height);
769 surf.mode = G_030004_ARRAY_MODE(texdw[1]);
770 surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
771 surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
772 surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
773 surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
774 surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
775 surf.nsamples = 1;
776 toffset = texdw[2] << 8;
777 moffset = texdw[3] << 8;
778
779 if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
780 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
781 __func__, __LINE__, surf.format);
782 return -EINVAL;
783 }
784 switch (dim) {
785 case V_030000_SQ_TEX_DIM_1D:
786 case V_030000_SQ_TEX_DIM_2D:
787 case V_030000_SQ_TEX_DIM_CUBEMAP:
788 case V_030000_SQ_TEX_DIM_1D_ARRAY:
789 case V_030000_SQ_TEX_DIM_2D_ARRAY:
790 depth = 1;
791 break;
792 case V_030000_SQ_TEX_DIM_2D_MSAA:
793 case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
794 surf.nsamples = 1 << llevel;
795 llevel = 0;
796 depth = 1;
797 break;
798 case V_030000_SQ_TEX_DIM_3D:
799 break;
800 default:
801 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
802 __func__, __LINE__, dim);
803 return -EINVAL;
804 }
805
806 r = evergreen_surface_value_conv_check(p, &surf, "texture");
807 if (r) {
808 return r;
809 }
810
811
812 evergreen_surface_check(p, &surf, NULL);
813 surf.nby = ALIGN(surf.nby, surf.halign);
814
815 r = evergreen_surface_check(p, &surf, "texture");
816 if (r) {
817 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
818 __func__, __LINE__, texdw[0], texdw[1], texdw[4],
819 texdw[5], texdw[6], texdw[7]);
820 return r;
821 }
822
823
824 if (toffset & (surf.base_align - 1)) {
825 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
826 __func__, __LINE__, toffset, surf.base_align);
827 return -EINVAL;
828 }
829 if (moffset & (surf.base_align - 1)) {
830 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
831 __func__, __LINE__, moffset, surf.base_align);
832 return -EINVAL;
833 }
834 if (dim == SQ_TEX_DIM_3D) {
835 toffset += surf.layer_size * depth;
836 } else {
837 toffset += surf.layer_size * mslice;
838 }
839 if (toffset > radeon_bo_size(texture)) {
840 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
841 "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
842 __func__, __LINE__, surf.layer_size,
843 (unsigned long)texdw[2] << 8, mslice,
844 depth, radeon_bo_size(texture),
845 surf.nbx, surf.nby);
846 return -EINVAL;
847 }
848
849
850 for (i = 1; i <= llevel; i++) {
851 unsigned w, h, d;
852
853 w = r600_mip_minify(width, i);
854 h = r600_mip_minify(height, i);
855 d = r600_mip_minify(depth, i);
856 surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
857 surf.nby = r600_fmt_get_nblocksy(surf.format, h);
858
859 switch (surf.mode) {
860 case ARRAY_2D_TILED_THIN1:
861 if (surf.nbx < surf.palign || surf.nby < surf.halign) {
862 surf.mode = ARRAY_1D_TILED_THIN1;
863 }
864
865 evergreen_surface_check(p, &surf, NULL);
866 break;
867 case ARRAY_LINEAR_GENERAL:
868 case ARRAY_LINEAR_ALIGNED:
869 case ARRAY_1D_TILED_THIN1:
870 break;
871 default:
872 dev_warn(p->dev, "%s:%d invalid array mode %d\n",
873 __func__, __LINE__, surf.mode);
874 return -EINVAL;
875 }
876 surf.nbx = ALIGN(surf.nbx, surf.palign);
877 surf.nby = ALIGN(surf.nby, surf.halign);
878
879 r = evergreen_surface_check(p, &surf, "mipmap");
880 if (r) {
881 return r;
882 }
883
884 if (dim == SQ_TEX_DIM_3D) {
885 moffset += surf.layer_size * d;
886 } else {
887 moffset += surf.layer_size * mslice;
888 }
889 if (moffset > radeon_bo_size(mipmap)) {
890 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
891 "offset %ld, coffset %ld, max layer %d, depth %d, "
892 "bo size %ld) level0 (%d %d %d)\n",
893 __func__, __LINE__, i, surf.layer_size,
894 (unsigned long)texdw[3] << 8, moffset, mslice,
895 d, radeon_bo_size(mipmap),
896 width, height, depth);
897 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
898 __func__, __LINE__, surf.nbx, surf.nby,
899 surf.mode, surf.bpe, surf.nsamples,
900 surf.bankw, surf.bankh,
901 surf.tsplit, surf.mtilea);
902 return -EINVAL;
903 }
904 }
905
906 return 0;
907}
908
909static int evergreen_cs_track_check(struct radeon_cs_parser *p)
910{
911 struct evergreen_cs_track *track = p->track;
912 unsigned tmp, i;
913 int r;
914 unsigned buffer_mask = 0;
915
916
917 if (track->streamout_dirty && track->vgt_strmout_config) {
918 for (i = 0; i < 4; i++) {
919 if (track->vgt_strmout_config & (1 << i)) {
920 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
921 }
922 }
923
924 for (i = 0; i < 4; i++) {
925 if (buffer_mask & (1 << i)) {
926 if (track->vgt_strmout_bo[i]) {
927 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
928 (u64)track->vgt_strmout_size[i];
929 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
930 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
931 i, offset,
932 radeon_bo_size(track->vgt_strmout_bo[i]));
933 return -EINVAL;
934 }
935 } else {
936 dev_warn(p->dev, "No buffer for streamout %d\n", i);
937 return -EINVAL;
938 }
939 }
940 }
941 track->streamout_dirty = false;
942 }
943
944 if (track->sx_misc_kill_all_prims)
945 return 0;
946
947
948
949 if (track->cb_dirty) {
950 tmp = track->cb_target_mask;
951 for (i = 0; i < 8; i++) {
952 if ((tmp >> (i * 4)) & 0xF) {
953
954 if (track->cb_color_bo[i] == NULL) {
955 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
956 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
957 return -EINVAL;
958 }
959
960 r = evergreen_cs_track_validate_cb(p, i);
961 if (r) {
962 return r;
963 }
964 }
965 }
966 track->cb_dirty = false;
967 }
968
969 if (track->db_dirty) {
970
971 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
972 G_028800_STENCIL_ENABLE(track->db_depth_control)) {
973 r = evergreen_cs_track_validate_stencil(p);
974 if (r)
975 return r;
976 }
977
978 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
979 G_028800_Z_ENABLE(track->db_depth_control)) {
980 r = evergreen_cs_track_validate_depth(p);
981 if (r)
982 return r;
983 }
984 track->db_dirty = false;
985 }
986
987 return 0;
988}
989
990
991
992
993
994
995
996
997
998int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
999 struct radeon_cs_packet *pkt,
1000 unsigned idx)
1001{
1002 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1003 uint32_t header;
1004
1005 if (idx >= ib_chunk->length_dw) {
1006 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1007 idx, ib_chunk->length_dw);
1008 return -EINVAL;
1009 }
1010 header = radeon_get_ib_value(p, idx);
1011 pkt->idx = idx;
1012 pkt->type = CP_PACKET_GET_TYPE(header);
1013 pkt->count = CP_PACKET_GET_COUNT(header);
1014 pkt->one_reg_wr = 0;
1015 switch (pkt->type) {
1016 case PACKET_TYPE0:
1017 pkt->reg = CP_PACKET0_GET_REG(header);
1018 break;
1019 case PACKET_TYPE3:
1020 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1021 break;
1022 case PACKET_TYPE2:
1023 pkt->count = -1;
1024 break;
1025 default:
1026 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1027 return -EINVAL;
1028 }
1029 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1030 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1031 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1032 return -EINVAL;
1033 }
1034 return 0;
1035}
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
1049 struct radeon_cs_reloc **cs_reloc)
1050{
1051 struct radeon_cs_chunk *relocs_chunk;
1052 struct radeon_cs_packet p3reloc;
1053 unsigned idx;
1054 int r;
1055
1056 if (p->chunk_relocs_idx == -1) {
1057 DRM_ERROR("No relocation chunk !\n");
1058 return -EINVAL;
1059 }
1060 *cs_reloc = NULL;
1061 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1062 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
1063 if (r) {
1064 return r;
1065 }
1066 p->idx += p3reloc.count + 2;
1067 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1068 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1069 p3reloc.idx);
1070 return -EINVAL;
1071 }
1072 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1073 if (idx >= relocs_chunk->length_dw) {
1074 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1075 idx, relocs_chunk->length_dw);
1076 return -EINVAL;
1077 }
1078
1079 *cs_reloc = p->relocs_ptr[(idx / 4)];
1080 return 0;
1081}
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1098{
1099 struct drm_mode_object *obj;
1100 struct drm_crtc *crtc;
1101 struct radeon_crtc *radeon_crtc;
1102 struct radeon_cs_packet p3reloc, wait_reg_mem;
1103 int crtc_id;
1104 int r;
1105 uint32_t header, h_idx, reg, wait_reg_mem_info;
1106 volatile uint32_t *ib;
1107
1108 ib = p->ib.ptr;
1109
1110
1111 r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
1112 if (r)
1113 return r;
1114
1115
1116 if (wait_reg_mem.type != PACKET_TYPE3 ||
1117 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1118 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1119 return -EINVAL;
1120 }
1121
1122 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1123
1124 if (wait_reg_mem_info & 0x10) {
1125 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1126 return -EINVAL;
1127 }
1128
1129 if ((wait_reg_mem_info & 0x7) != 0x3) {
1130 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1131 return -EINVAL;
1132 }
1133 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
1134 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1135 return -EINVAL;
1136 }
1137
1138 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
1139 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1140 return -EINVAL;
1141 }
1142
1143
1144 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1145 if (r)
1146 return r;
1147
1148 h_idx = p->idx - 2;
1149 p->idx += wait_reg_mem.count + 2;
1150 p->idx += p3reloc.count + 2;
1151
1152 header = radeon_get_ib_value(p, h_idx);
1153 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1154 reg = CP_PACKET0_GET_REG(header);
1155 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1156 if (!obj) {
1157 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1158 return -EINVAL;
1159 }
1160 crtc = obj_to_crtc(obj);
1161 radeon_crtc = to_radeon_crtc(crtc);
1162 crtc_id = radeon_crtc->crtc_id;
1163
1164 if (!crtc->enabled) {
1165
1166 ib[h_idx + 2] = PACKET2(0);
1167 ib[h_idx + 3] = PACKET2(0);
1168 ib[h_idx + 4] = PACKET2(0);
1169 ib[h_idx + 5] = PACKET2(0);
1170 ib[h_idx + 6] = PACKET2(0);
1171 ib[h_idx + 7] = PACKET2(0);
1172 ib[h_idx + 8] = PACKET2(0);
1173 } else {
1174 switch (reg) {
1175 case EVERGREEN_VLINE_START_END:
1176 header &= ~R600_CP_PACKET0_REG_MASK;
1177 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
1178 ib[h_idx] = header;
1179 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
1180 break;
1181 default:
1182 DRM_ERROR("unknown crtc reloc\n");
1183 return -EINVAL;
1184 }
1185 }
1186 return 0;
1187}
1188
1189static int evergreen_packet0_check(struct radeon_cs_parser *p,
1190 struct radeon_cs_packet *pkt,
1191 unsigned idx, unsigned reg)
1192{
1193 int r;
1194
1195 switch (reg) {
1196 case EVERGREEN_VLINE_START_END:
1197 r = evergreen_cs_packet_parse_vline(p);
1198 if (r) {
1199 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1200 idx, reg);
1201 return r;
1202 }
1203 break;
1204 default:
1205 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1206 reg, idx);
1207 return -EINVAL;
1208 }
1209 return 0;
1210}
1211
1212static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1213 struct radeon_cs_packet *pkt)
1214{
1215 unsigned reg, i;
1216 unsigned idx;
1217 int r;
1218
1219 idx = pkt->idx + 1;
1220 reg = pkt->reg;
1221 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1222 r = evergreen_packet0_check(p, pkt, idx, reg);
1223 if (r) {
1224 return r;
1225 }
1226 }
1227 return 0;
1228}
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1241{
1242 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1243 struct radeon_cs_reloc *reloc;
1244 u32 last_reg;
1245 u32 m, i, tmp, *ib;
1246 int r;
1247
1248 if (p->rdev->family >= CHIP_CAYMAN)
1249 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1250 else
1251 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1252
1253 i = (reg >> 7);
1254 if (i >= last_reg) {
1255 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1256 return -EINVAL;
1257 }
1258 m = 1 << ((reg >> 2) & 31);
1259 if (p->rdev->family >= CHIP_CAYMAN) {
1260 if (!(cayman_reg_safe_bm[i] & m))
1261 return 0;
1262 } else {
1263 if (!(evergreen_reg_safe_bm[i] & m))
1264 return 0;
1265 }
1266 ib = p->ib.ptr;
1267 switch (reg) {
1268
1269
1270
1271
1272 case SQ_ESGS_RING_SIZE:
1273 case SQ_GSVS_RING_SIZE:
1274 case SQ_ESTMP_RING_SIZE:
1275 case SQ_GSTMP_RING_SIZE:
1276 case SQ_HSTMP_RING_SIZE:
1277 case SQ_LSTMP_RING_SIZE:
1278 case SQ_PSTMP_RING_SIZE:
1279 case SQ_VSTMP_RING_SIZE:
1280 case SQ_ESGS_RING_ITEMSIZE:
1281 case SQ_ESTMP_RING_ITEMSIZE:
1282 case SQ_GSTMP_RING_ITEMSIZE:
1283 case SQ_GSVS_RING_ITEMSIZE:
1284 case SQ_GS_VERT_ITEMSIZE:
1285 case SQ_GS_VERT_ITEMSIZE_1:
1286 case SQ_GS_VERT_ITEMSIZE_2:
1287 case SQ_GS_VERT_ITEMSIZE_3:
1288 case SQ_GSVS_RING_OFFSET_1:
1289 case SQ_GSVS_RING_OFFSET_2:
1290 case SQ_GSVS_RING_OFFSET_3:
1291 case SQ_HSTMP_RING_ITEMSIZE:
1292 case SQ_LSTMP_RING_ITEMSIZE:
1293 case SQ_PSTMP_RING_ITEMSIZE:
1294 case SQ_VSTMP_RING_ITEMSIZE:
1295 case VGT_TF_RING_SIZE:
1296
1297
1298
1299 break;
1300 case SQ_ESGS_RING_BASE:
1301 case SQ_GSVS_RING_BASE:
1302 case SQ_ESTMP_RING_BASE:
1303 case SQ_GSTMP_RING_BASE:
1304 case SQ_HSTMP_RING_BASE:
1305 case SQ_LSTMP_RING_BASE:
1306 case SQ_PSTMP_RING_BASE:
1307 case SQ_VSTMP_RING_BASE:
1308 r = evergreen_cs_packet_next_reloc(p, &reloc);
1309 if (r) {
1310 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1311 "0x%04X\n", reg);
1312 return -EINVAL;
1313 }
1314 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1315 break;
1316 case DB_DEPTH_CONTROL:
1317 track->db_depth_control = radeon_get_ib_value(p, idx);
1318 track->db_dirty = true;
1319 break;
1320 case CAYMAN_DB_EQAA:
1321 if (p->rdev->family < CHIP_CAYMAN) {
1322 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1323 "0x%04X\n", reg);
1324 return -EINVAL;
1325 }
1326 break;
1327 case CAYMAN_DB_DEPTH_INFO:
1328 if (p->rdev->family < CHIP_CAYMAN) {
1329 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1330 "0x%04X\n", reg);
1331 return -EINVAL;
1332 }
1333 break;
1334 case DB_Z_INFO:
1335 track->db_z_info = radeon_get_ib_value(p, idx);
1336 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1337 r = evergreen_cs_packet_next_reloc(p, &reloc);
1338 if (r) {
1339 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1340 "0x%04X\n", reg);
1341 return -EINVAL;
1342 }
1343 ib[idx] &= ~Z_ARRAY_MODE(0xf);
1344 track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1345 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1346 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1347 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1348 unsigned bankw, bankh, mtaspect, tile_split;
1349
1350 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1351 &bankw, &bankh, &mtaspect,
1352 &tile_split);
1353 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1354 ib[idx] |= DB_TILE_SPLIT(tile_split) |
1355 DB_BANK_WIDTH(bankw) |
1356 DB_BANK_HEIGHT(bankh) |
1357 DB_MACRO_TILE_ASPECT(mtaspect);
1358 }
1359 }
1360 track->db_dirty = true;
1361 break;
1362 case DB_STENCIL_INFO:
1363 track->db_s_info = radeon_get_ib_value(p, idx);
1364 track->db_dirty = true;
1365 break;
1366 case DB_DEPTH_VIEW:
1367 track->db_depth_view = radeon_get_ib_value(p, idx);
1368 track->db_dirty = true;
1369 break;
1370 case DB_DEPTH_SIZE:
1371 track->db_depth_size = radeon_get_ib_value(p, idx);
1372 track->db_dirty = true;
1373 break;
1374 case R_02805C_DB_DEPTH_SLICE:
1375 track->db_depth_slice = radeon_get_ib_value(p, idx);
1376 track->db_dirty = true;
1377 break;
1378 case DB_Z_READ_BASE:
1379 r = evergreen_cs_packet_next_reloc(p, &reloc);
1380 if (r) {
1381 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1382 "0x%04X\n", reg);
1383 return -EINVAL;
1384 }
1385 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1386 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1387 track->db_z_read_bo = reloc->robj;
1388 track->db_dirty = true;
1389 break;
1390 case DB_Z_WRITE_BASE:
1391 r = evergreen_cs_packet_next_reloc(p, &reloc);
1392 if (r) {
1393 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1394 "0x%04X\n", reg);
1395 return -EINVAL;
1396 }
1397 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1398 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1399 track->db_z_write_bo = reloc->robj;
1400 track->db_dirty = true;
1401 break;
1402 case DB_STENCIL_READ_BASE:
1403 r = evergreen_cs_packet_next_reloc(p, &reloc);
1404 if (r) {
1405 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1406 "0x%04X\n", reg);
1407 return -EINVAL;
1408 }
1409 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1410 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1411 track->db_s_read_bo = reloc->robj;
1412 track->db_dirty = true;
1413 break;
1414 case DB_STENCIL_WRITE_BASE:
1415 r = evergreen_cs_packet_next_reloc(p, &reloc);
1416 if (r) {
1417 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1418 "0x%04X\n", reg);
1419 return -EINVAL;
1420 }
1421 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1422 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1423 track->db_s_write_bo = reloc->robj;
1424 track->db_dirty = true;
1425 break;
1426 case VGT_STRMOUT_CONFIG:
1427 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1428 track->streamout_dirty = true;
1429 break;
1430 case VGT_STRMOUT_BUFFER_CONFIG:
1431 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1432 track->streamout_dirty = true;
1433 break;
1434 case VGT_STRMOUT_BUFFER_BASE_0:
1435 case VGT_STRMOUT_BUFFER_BASE_1:
1436 case VGT_STRMOUT_BUFFER_BASE_2:
1437 case VGT_STRMOUT_BUFFER_BASE_3:
1438 r = evergreen_cs_packet_next_reloc(p, &reloc);
1439 if (r) {
1440 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1441 "0x%04X\n", reg);
1442 return -EINVAL;
1443 }
1444 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1445 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1446 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1447 track->vgt_strmout_bo[tmp] = reloc->robj;
1448 track->streamout_dirty = true;
1449 break;
1450 case VGT_STRMOUT_BUFFER_SIZE_0:
1451 case VGT_STRMOUT_BUFFER_SIZE_1:
1452 case VGT_STRMOUT_BUFFER_SIZE_2:
1453 case VGT_STRMOUT_BUFFER_SIZE_3:
1454 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1455
1456 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1457 track->streamout_dirty = true;
1458 break;
1459 case CP_COHER_BASE:
1460 r = evergreen_cs_packet_next_reloc(p, &reloc);
1461 if (r) {
1462 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1463 "0x%04X\n", reg);
1464 return -EINVAL;
1465 }
1466 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1467 case CB_TARGET_MASK:
1468 track->cb_target_mask = radeon_get_ib_value(p, idx);
1469 track->cb_dirty = true;
1470 break;
1471 case CB_SHADER_MASK:
1472 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1473 track->cb_dirty = true;
1474 break;
1475 case PA_SC_AA_CONFIG:
1476 if (p->rdev->family >= CHIP_CAYMAN) {
1477 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1478 "0x%04X\n", reg);
1479 return -EINVAL;
1480 }
1481 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1482 track->nsamples = 1 << tmp;
1483 break;
1484 case CAYMAN_PA_SC_AA_CONFIG:
1485 if (p->rdev->family < CHIP_CAYMAN) {
1486 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1487 "0x%04X\n", reg);
1488 return -EINVAL;
1489 }
1490 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1491 track->nsamples = 1 << tmp;
1492 break;
1493 case CB_COLOR0_VIEW:
1494 case CB_COLOR1_VIEW:
1495 case CB_COLOR2_VIEW:
1496 case CB_COLOR3_VIEW:
1497 case CB_COLOR4_VIEW:
1498 case CB_COLOR5_VIEW:
1499 case CB_COLOR6_VIEW:
1500 case CB_COLOR7_VIEW:
1501 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1502 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1503 track->cb_dirty = true;
1504 break;
1505 case CB_COLOR8_VIEW:
1506 case CB_COLOR9_VIEW:
1507 case CB_COLOR10_VIEW:
1508 case CB_COLOR11_VIEW:
1509 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1510 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1511 track->cb_dirty = true;
1512 break;
1513 case CB_COLOR0_INFO:
1514 case CB_COLOR1_INFO:
1515 case CB_COLOR2_INFO:
1516 case CB_COLOR3_INFO:
1517 case CB_COLOR4_INFO:
1518 case CB_COLOR5_INFO:
1519 case CB_COLOR6_INFO:
1520 case CB_COLOR7_INFO:
1521 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1522 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1523 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1524 r = evergreen_cs_packet_next_reloc(p, &reloc);
1525 if (r) {
1526 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1527 "0x%04X\n", reg);
1528 return -EINVAL;
1529 }
1530 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1531 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1532 }
1533 track->cb_dirty = true;
1534 break;
1535 case CB_COLOR8_INFO:
1536 case CB_COLOR9_INFO:
1537 case CB_COLOR10_INFO:
1538 case CB_COLOR11_INFO:
1539 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1540 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1541 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1542 r = evergreen_cs_packet_next_reloc(p, &reloc);
1543 if (r) {
1544 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1545 "0x%04X\n", reg);
1546 return -EINVAL;
1547 }
1548 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1549 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1550 }
1551 track->cb_dirty = true;
1552 break;
1553 case CB_COLOR0_PITCH:
1554 case CB_COLOR1_PITCH:
1555 case CB_COLOR2_PITCH:
1556 case CB_COLOR3_PITCH:
1557 case CB_COLOR4_PITCH:
1558 case CB_COLOR5_PITCH:
1559 case CB_COLOR6_PITCH:
1560 case CB_COLOR7_PITCH:
1561 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1562 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1563 track->cb_dirty = true;
1564 break;
1565 case CB_COLOR8_PITCH:
1566 case CB_COLOR9_PITCH:
1567 case CB_COLOR10_PITCH:
1568 case CB_COLOR11_PITCH:
1569 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1570 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1571 track->cb_dirty = true;
1572 break;
1573 case CB_COLOR0_SLICE:
1574 case CB_COLOR1_SLICE:
1575 case CB_COLOR2_SLICE:
1576 case CB_COLOR3_SLICE:
1577 case CB_COLOR4_SLICE:
1578 case CB_COLOR5_SLICE:
1579 case CB_COLOR6_SLICE:
1580 case CB_COLOR7_SLICE:
1581 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1582 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1583 track->cb_color_slice_idx[tmp] = idx;
1584 track->cb_dirty = true;
1585 break;
1586 case CB_COLOR8_SLICE:
1587 case CB_COLOR9_SLICE:
1588 case CB_COLOR10_SLICE:
1589 case CB_COLOR11_SLICE:
1590 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1591 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1592 track->cb_color_slice_idx[tmp] = idx;
1593 track->cb_dirty = true;
1594 break;
1595 case CB_COLOR0_ATTRIB:
1596 case CB_COLOR1_ATTRIB:
1597 case CB_COLOR2_ATTRIB:
1598 case CB_COLOR3_ATTRIB:
1599 case CB_COLOR4_ATTRIB:
1600 case CB_COLOR5_ATTRIB:
1601 case CB_COLOR6_ATTRIB:
1602 case CB_COLOR7_ATTRIB:
1603 r = evergreen_cs_packet_next_reloc(p, &reloc);
1604 if (r) {
1605 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1606 "0x%04X\n", reg);
1607 return -EINVAL;
1608 }
1609 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1610 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1611 unsigned bankw, bankh, mtaspect, tile_split;
1612
1613 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1614 &bankw, &bankh, &mtaspect,
1615 &tile_split);
1616 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1617 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1618 CB_BANK_WIDTH(bankw) |
1619 CB_BANK_HEIGHT(bankh) |
1620 CB_MACRO_TILE_ASPECT(mtaspect);
1621 }
1622 }
1623 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1624 track->cb_color_attrib[tmp] = ib[idx];
1625 track->cb_dirty = true;
1626 break;
1627 case CB_COLOR8_ATTRIB:
1628 case CB_COLOR9_ATTRIB:
1629 case CB_COLOR10_ATTRIB:
1630 case CB_COLOR11_ATTRIB:
1631 r = evergreen_cs_packet_next_reloc(p, &reloc);
1632 if (r) {
1633 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1634 "0x%04X\n", reg);
1635 return -EINVAL;
1636 }
1637 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1638 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1639 unsigned bankw, bankh, mtaspect, tile_split;
1640
1641 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1642 &bankw, &bankh, &mtaspect,
1643 &tile_split);
1644 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1645 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1646 CB_BANK_WIDTH(bankw) |
1647 CB_BANK_HEIGHT(bankh) |
1648 CB_MACRO_TILE_ASPECT(mtaspect);
1649 }
1650 }
1651 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1652 track->cb_color_attrib[tmp] = ib[idx];
1653 track->cb_dirty = true;
1654 break;
1655 case CB_COLOR0_FMASK:
1656 case CB_COLOR1_FMASK:
1657 case CB_COLOR2_FMASK:
1658 case CB_COLOR3_FMASK:
1659 case CB_COLOR4_FMASK:
1660 case CB_COLOR5_FMASK:
1661 case CB_COLOR6_FMASK:
1662 case CB_COLOR7_FMASK:
1663 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1664 r = evergreen_cs_packet_next_reloc(p, &reloc);
1665 if (r) {
1666 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1667 return -EINVAL;
1668 }
1669 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1670 track->cb_color_fmask_bo[tmp] = reloc->robj;
1671 break;
1672 case CB_COLOR0_CMASK:
1673 case CB_COLOR1_CMASK:
1674 case CB_COLOR2_CMASK:
1675 case CB_COLOR3_CMASK:
1676 case CB_COLOR4_CMASK:
1677 case CB_COLOR5_CMASK:
1678 case CB_COLOR6_CMASK:
1679 case CB_COLOR7_CMASK:
1680 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1681 r = evergreen_cs_packet_next_reloc(p, &reloc);
1682 if (r) {
1683 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1684 return -EINVAL;
1685 }
1686 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1687 track->cb_color_cmask_bo[tmp] = reloc->robj;
1688 break;
1689 case CB_COLOR0_FMASK_SLICE:
1690 case CB_COLOR1_FMASK_SLICE:
1691 case CB_COLOR2_FMASK_SLICE:
1692 case CB_COLOR3_FMASK_SLICE:
1693 case CB_COLOR4_FMASK_SLICE:
1694 case CB_COLOR5_FMASK_SLICE:
1695 case CB_COLOR6_FMASK_SLICE:
1696 case CB_COLOR7_FMASK_SLICE:
1697 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1698 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1699 break;
1700 case CB_COLOR0_CMASK_SLICE:
1701 case CB_COLOR1_CMASK_SLICE:
1702 case CB_COLOR2_CMASK_SLICE:
1703 case CB_COLOR3_CMASK_SLICE:
1704 case CB_COLOR4_CMASK_SLICE:
1705 case CB_COLOR5_CMASK_SLICE:
1706 case CB_COLOR6_CMASK_SLICE:
1707 case CB_COLOR7_CMASK_SLICE:
1708 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1709 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1710 break;
1711 case CB_COLOR0_BASE:
1712 case CB_COLOR1_BASE:
1713 case CB_COLOR2_BASE:
1714 case CB_COLOR3_BASE:
1715 case CB_COLOR4_BASE:
1716 case CB_COLOR5_BASE:
1717 case CB_COLOR6_BASE:
1718 case CB_COLOR7_BASE:
1719 r = evergreen_cs_packet_next_reloc(p, &reloc);
1720 if (r) {
1721 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1722 "0x%04X\n", reg);
1723 return -EINVAL;
1724 }
1725 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1726 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1727 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1728 track->cb_color_bo[tmp] = reloc->robj;
1729 track->cb_dirty = true;
1730 break;
1731 case CB_COLOR8_BASE:
1732 case CB_COLOR9_BASE:
1733 case CB_COLOR10_BASE:
1734 case CB_COLOR11_BASE:
1735 r = evergreen_cs_packet_next_reloc(p, &reloc);
1736 if (r) {
1737 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1738 "0x%04X\n", reg);
1739 return -EINVAL;
1740 }
1741 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1742 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1743 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1744 track->cb_color_bo[tmp] = reloc->robj;
1745 track->cb_dirty = true;
1746 break;
1747 case DB_HTILE_DATA_BASE:
1748 r = evergreen_cs_packet_next_reloc(p, &reloc);
1749 if (r) {
1750 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1751 "0x%04X\n", reg);
1752 return -EINVAL;
1753 }
1754 track->htile_offset = radeon_get_ib_value(p, idx);
1755 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1756 track->htile_bo = reloc->robj;
1757 track->db_dirty = true;
1758 break;
1759 case DB_HTILE_SURFACE:
1760
1761 track->htile_surface = radeon_get_ib_value(p, idx);
1762 track->db_dirty = true;
1763 break;
1764 case CB_IMMED0_BASE:
1765 case CB_IMMED1_BASE:
1766 case CB_IMMED2_BASE:
1767 case CB_IMMED3_BASE:
1768 case CB_IMMED4_BASE:
1769 case CB_IMMED5_BASE:
1770 case CB_IMMED6_BASE:
1771 case CB_IMMED7_BASE:
1772 case CB_IMMED8_BASE:
1773 case CB_IMMED9_BASE:
1774 case CB_IMMED10_BASE:
1775 case CB_IMMED11_BASE:
1776 case SQ_PGM_START_FS:
1777 case SQ_PGM_START_ES:
1778 case SQ_PGM_START_VS:
1779 case SQ_PGM_START_GS:
1780 case SQ_PGM_START_PS:
1781 case SQ_PGM_START_HS:
1782 case SQ_PGM_START_LS:
1783 case SQ_CONST_MEM_BASE:
1784 case SQ_ALU_CONST_CACHE_GS_0:
1785 case SQ_ALU_CONST_CACHE_GS_1:
1786 case SQ_ALU_CONST_CACHE_GS_2:
1787 case SQ_ALU_CONST_CACHE_GS_3:
1788 case SQ_ALU_CONST_CACHE_GS_4:
1789 case SQ_ALU_CONST_CACHE_GS_5:
1790 case SQ_ALU_CONST_CACHE_GS_6:
1791 case SQ_ALU_CONST_CACHE_GS_7:
1792 case SQ_ALU_CONST_CACHE_GS_8:
1793 case SQ_ALU_CONST_CACHE_GS_9:
1794 case SQ_ALU_CONST_CACHE_GS_10:
1795 case SQ_ALU_CONST_CACHE_GS_11:
1796 case SQ_ALU_CONST_CACHE_GS_12:
1797 case SQ_ALU_CONST_CACHE_GS_13:
1798 case SQ_ALU_CONST_CACHE_GS_14:
1799 case SQ_ALU_CONST_CACHE_GS_15:
1800 case SQ_ALU_CONST_CACHE_PS_0:
1801 case SQ_ALU_CONST_CACHE_PS_1:
1802 case SQ_ALU_CONST_CACHE_PS_2:
1803 case SQ_ALU_CONST_CACHE_PS_3:
1804 case SQ_ALU_CONST_CACHE_PS_4:
1805 case SQ_ALU_CONST_CACHE_PS_5:
1806 case SQ_ALU_CONST_CACHE_PS_6:
1807 case SQ_ALU_CONST_CACHE_PS_7:
1808 case SQ_ALU_CONST_CACHE_PS_8:
1809 case SQ_ALU_CONST_CACHE_PS_9:
1810 case SQ_ALU_CONST_CACHE_PS_10:
1811 case SQ_ALU_CONST_CACHE_PS_11:
1812 case SQ_ALU_CONST_CACHE_PS_12:
1813 case SQ_ALU_CONST_CACHE_PS_13:
1814 case SQ_ALU_CONST_CACHE_PS_14:
1815 case SQ_ALU_CONST_CACHE_PS_15:
1816 case SQ_ALU_CONST_CACHE_VS_0:
1817 case SQ_ALU_CONST_CACHE_VS_1:
1818 case SQ_ALU_CONST_CACHE_VS_2:
1819 case SQ_ALU_CONST_CACHE_VS_3:
1820 case SQ_ALU_CONST_CACHE_VS_4:
1821 case SQ_ALU_CONST_CACHE_VS_5:
1822 case SQ_ALU_CONST_CACHE_VS_6:
1823 case SQ_ALU_CONST_CACHE_VS_7:
1824 case SQ_ALU_CONST_CACHE_VS_8:
1825 case SQ_ALU_CONST_CACHE_VS_9:
1826 case SQ_ALU_CONST_CACHE_VS_10:
1827 case SQ_ALU_CONST_CACHE_VS_11:
1828 case SQ_ALU_CONST_CACHE_VS_12:
1829 case SQ_ALU_CONST_CACHE_VS_13:
1830 case SQ_ALU_CONST_CACHE_VS_14:
1831 case SQ_ALU_CONST_CACHE_VS_15:
1832 case SQ_ALU_CONST_CACHE_HS_0:
1833 case SQ_ALU_CONST_CACHE_HS_1:
1834 case SQ_ALU_CONST_CACHE_HS_2:
1835 case SQ_ALU_CONST_CACHE_HS_3:
1836 case SQ_ALU_CONST_CACHE_HS_4:
1837 case SQ_ALU_CONST_CACHE_HS_5:
1838 case SQ_ALU_CONST_CACHE_HS_6:
1839 case SQ_ALU_CONST_CACHE_HS_7:
1840 case SQ_ALU_CONST_CACHE_HS_8:
1841 case SQ_ALU_CONST_CACHE_HS_9:
1842 case SQ_ALU_CONST_CACHE_HS_10:
1843 case SQ_ALU_CONST_CACHE_HS_11:
1844 case SQ_ALU_CONST_CACHE_HS_12:
1845 case SQ_ALU_CONST_CACHE_HS_13:
1846 case SQ_ALU_CONST_CACHE_HS_14:
1847 case SQ_ALU_CONST_CACHE_HS_15:
1848 case SQ_ALU_CONST_CACHE_LS_0:
1849 case SQ_ALU_CONST_CACHE_LS_1:
1850 case SQ_ALU_CONST_CACHE_LS_2:
1851 case SQ_ALU_CONST_CACHE_LS_3:
1852 case SQ_ALU_CONST_CACHE_LS_4:
1853 case SQ_ALU_CONST_CACHE_LS_5:
1854 case SQ_ALU_CONST_CACHE_LS_6:
1855 case SQ_ALU_CONST_CACHE_LS_7:
1856 case SQ_ALU_CONST_CACHE_LS_8:
1857 case SQ_ALU_CONST_CACHE_LS_9:
1858 case SQ_ALU_CONST_CACHE_LS_10:
1859 case SQ_ALU_CONST_CACHE_LS_11:
1860 case SQ_ALU_CONST_CACHE_LS_12:
1861 case SQ_ALU_CONST_CACHE_LS_13:
1862 case SQ_ALU_CONST_CACHE_LS_14:
1863 case SQ_ALU_CONST_CACHE_LS_15:
1864 r = evergreen_cs_packet_next_reloc(p, &reloc);
1865 if (r) {
1866 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1867 "0x%04X\n", reg);
1868 return -EINVAL;
1869 }
1870 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1871 break;
1872 case SX_MEMORY_EXPORT_BASE:
1873 if (p->rdev->family >= CHIP_CAYMAN) {
1874 dev_warn(p->dev, "bad SET_CONFIG_REG "
1875 "0x%04X\n", reg);
1876 return -EINVAL;
1877 }
1878 r = evergreen_cs_packet_next_reloc(p, &reloc);
1879 if (r) {
1880 dev_warn(p->dev, "bad SET_CONFIG_REG "
1881 "0x%04X\n", reg);
1882 return -EINVAL;
1883 }
1884 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1885 break;
1886 case CAYMAN_SX_SCATTER_EXPORT_BASE:
1887 if (p->rdev->family < CHIP_CAYMAN) {
1888 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1889 "0x%04X\n", reg);
1890 return -EINVAL;
1891 }
1892 r = evergreen_cs_packet_next_reloc(p, &reloc);
1893 if (r) {
1894 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1895 "0x%04X\n", reg);
1896 return -EINVAL;
1897 }
1898 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1899 break;
1900 case SX_MISC:
1901 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1902 break;
1903 default:
1904 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1905 return -EINVAL;
1906 }
1907 return 0;
1908}
1909
1910static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1911{
1912 u32 last_reg, m, i;
1913
1914 if (p->rdev->family >= CHIP_CAYMAN)
1915 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1916 else
1917 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1918
1919 i = (reg >> 7);
1920 if (i >= last_reg) {
1921 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1922 return false;
1923 }
1924 m = 1 << ((reg >> 2) & 31);
1925 if (p->rdev->family >= CHIP_CAYMAN) {
1926 if (!(cayman_reg_safe_bm[i] & m))
1927 return true;
1928 } else {
1929 if (!(evergreen_reg_safe_bm[i] & m))
1930 return true;
1931 }
1932 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1933 return false;
1934}
1935
1936static int evergreen_packet3_check(struct radeon_cs_parser *p,
1937 struct radeon_cs_packet *pkt)
1938{
1939 struct radeon_cs_reloc *reloc;
1940 struct evergreen_cs_track *track;
1941 volatile u32 *ib;
1942 unsigned idx;
1943 unsigned i;
1944 unsigned start_reg, end_reg, reg;
1945 int r;
1946 u32 idx_value;
1947
1948 track = (struct evergreen_cs_track *)p->track;
1949 ib = p->ib.ptr;
1950 idx = pkt->idx + 1;
1951 idx_value = radeon_get_ib_value(p, idx);
1952
1953 switch (pkt->opcode) {
1954 case PACKET3_SET_PREDICATION:
1955 {
1956 int pred_op;
1957 int tmp;
1958 uint64_t offset;
1959
1960 if (pkt->count != 1) {
1961 DRM_ERROR("bad SET PREDICATION\n");
1962 return -EINVAL;
1963 }
1964
1965 tmp = radeon_get_ib_value(p, idx + 1);
1966 pred_op = (tmp >> 16) & 0x7;
1967
1968
1969 if (pred_op == 0)
1970 return 0;
1971
1972 if (pred_op > 2) {
1973 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1974 return -EINVAL;
1975 }
1976
1977 r = evergreen_cs_packet_next_reloc(p, &reloc);
1978 if (r) {
1979 DRM_ERROR("bad SET PREDICATION\n");
1980 return -EINVAL;
1981 }
1982
1983 offset = reloc->lobj.gpu_offset +
1984 (idx_value & 0xfffffff0) +
1985 ((u64)(tmp & 0xff) << 32);
1986
1987 ib[idx + 0] = offset;
1988 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1989 }
1990 break;
1991 case PACKET3_CONTEXT_CONTROL:
1992 if (pkt->count != 1) {
1993 DRM_ERROR("bad CONTEXT_CONTROL\n");
1994 return -EINVAL;
1995 }
1996 break;
1997 case PACKET3_INDEX_TYPE:
1998 case PACKET3_NUM_INSTANCES:
1999 case PACKET3_CLEAR_STATE:
2000 if (pkt->count) {
2001 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2002 return -EINVAL;
2003 }
2004 break;
2005 case CAYMAN_PACKET3_DEALLOC_STATE:
2006 if (p->rdev->family < CHIP_CAYMAN) {
2007 DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
2008 return -EINVAL;
2009 }
2010 if (pkt->count) {
2011 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2012 return -EINVAL;
2013 }
2014 break;
2015 case PACKET3_INDEX_BASE:
2016 {
2017 uint64_t offset;
2018
2019 if (pkt->count != 1) {
2020 DRM_ERROR("bad INDEX_BASE\n");
2021 return -EINVAL;
2022 }
2023 r = evergreen_cs_packet_next_reloc(p, &reloc);
2024 if (r) {
2025 DRM_ERROR("bad INDEX_BASE\n");
2026 return -EINVAL;
2027 }
2028
2029 offset = reloc->lobj.gpu_offset +
2030 idx_value +
2031 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2032
2033 ib[idx+0] = offset;
2034 ib[idx+1] = upper_32_bits(offset) & 0xff;
2035
2036 r = evergreen_cs_track_check(p);
2037 if (r) {
2038 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2039 return r;
2040 }
2041 break;
2042 }
2043 case PACKET3_DRAW_INDEX:
2044 {
2045 uint64_t offset;
2046 if (pkt->count != 3) {
2047 DRM_ERROR("bad DRAW_INDEX\n");
2048 return -EINVAL;
2049 }
2050 r = evergreen_cs_packet_next_reloc(p, &reloc);
2051 if (r) {
2052 DRM_ERROR("bad DRAW_INDEX\n");
2053 return -EINVAL;
2054 }
2055
2056 offset = reloc->lobj.gpu_offset +
2057 idx_value +
2058 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2059
2060 ib[idx+0] = offset;
2061 ib[idx+1] = upper_32_bits(offset) & 0xff;
2062
2063 r = evergreen_cs_track_check(p);
2064 if (r) {
2065 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2066 return r;
2067 }
2068 break;
2069 }
2070 case PACKET3_DRAW_INDEX_2:
2071 {
2072 uint64_t offset;
2073
2074 if (pkt->count != 4) {
2075 DRM_ERROR("bad DRAW_INDEX_2\n");
2076 return -EINVAL;
2077 }
2078 r = evergreen_cs_packet_next_reloc(p, &reloc);
2079 if (r) {
2080 DRM_ERROR("bad DRAW_INDEX_2\n");
2081 return -EINVAL;
2082 }
2083
2084 offset = reloc->lobj.gpu_offset +
2085 radeon_get_ib_value(p, idx+1) +
2086 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2087
2088 ib[idx+1] = offset;
2089 ib[idx+2] = upper_32_bits(offset) & 0xff;
2090
2091 r = evergreen_cs_track_check(p);
2092 if (r) {
2093 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2094 return r;
2095 }
2096 break;
2097 }
2098 case PACKET3_DRAW_INDEX_AUTO:
2099 if (pkt->count != 1) {
2100 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
2101 return -EINVAL;
2102 }
2103 r = evergreen_cs_track_check(p);
2104 if (r) {
2105 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2106 return r;
2107 }
2108 break;
2109 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2110 if (pkt->count != 2) {
2111 DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
2112 return -EINVAL;
2113 }
2114 r = evergreen_cs_track_check(p);
2115 if (r) {
2116 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2117 return r;
2118 }
2119 break;
2120 case PACKET3_DRAW_INDEX_IMMD:
2121 if (pkt->count < 2) {
2122 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
2123 return -EINVAL;
2124 }
2125 r = evergreen_cs_track_check(p);
2126 if (r) {
2127 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2128 return r;
2129 }
2130 break;
2131 case PACKET3_DRAW_INDEX_OFFSET:
2132 if (pkt->count != 2) {
2133 DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
2134 return -EINVAL;
2135 }
2136 r = evergreen_cs_track_check(p);
2137 if (r) {
2138 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2139 return r;
2140 }
2141 break;
2142 case PACKET3_DRAW_INDEX_OFFSET_2:
2143 if (pkt->count != 3) {
2144 DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
2145 return -EINVAL;
2146 }
2147 r = evergreen_cs_track_check(p);
2148 if (r) {
2149 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2150 return r;
2151 }
2152 break;
2153 case PACKET3_DISPATCH_DIRECT:
2154 if (pkt->count != 3) {
2155 DRM_ERROR("bad DISPATCH_DIRECT\n");
2156 return -EINVAL;
2157 }
2158 r = evergreen_cs_track_check(p);
2159 if (r) {
2160 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2161 return r;
2162 }
2163 break;
2164 case PACKET3_DISPATCH_INDIRECT:
2165 if (pkt->count != 1) {
2166 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2167 return -EINVAL;
2168 }
2169 r = evergreen_cs_packet_next_reloc(p, &reloc);
2170 if (r) {
2171 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2172 return -EINVAL;
2173 }
2174 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2175 r = evergreen_cs_track_check(p);
2176 if (r) {
2177 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2178 return r;
2179 }
2180 break;
2181 case PACKET3_WAIT_REG_MEM:
2182 if (pkt->count != 5) {
2183 DRM_ERROR("bad WAIT_REG_MEM\n");
2184 return -EINVAL;
2185 }
2186
2187 if (idx_value & 0x10) {
2188 uint64_t offset;
2189
2190 r = evergreen_cs_packet_next_reloc(p, &reloc);
2191 if (r) {
2192 DRM_ERROR("bad WAIT_REG_MEM\n");
2193 return -EINVAL;
2194 }
2195
2196 offset = reloc->lobj.gpu_offset +
2197 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2198 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2199
2200 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2201 ib[idx+2] = upper_32_bits(offset) & 0xff;
2202 }
2203 break;
2204 case PACKET3_SURFACE_SYNC:
2205 if (pkt->count != 3) {
2206 DRM_ERROR("bad SURFACE_SYNC\n");
2207 return -EINVAL;
2208 }
2209
2210 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2211 radeon_get_ib_value(p, idx + 2) != 0) {
2212 r = evergreen_cs_packet_next_reloc(p, &reloc);
2213 if (r) {
2214 DRM_ERROR("bad SURFACE_SYNC\n");
2215 return -EINVAL;
2216 }
2217 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2218 }
2219 break;
2220 case PACKET3_EVENT_WRITE:
2221 if (pkt->count != 2 && pkt->count != 0) {
2222 DRM_ERROR("bad EVENT_WRITE\n");
2223 return -EINVAL;
2224 }
2225 if (pkt->count) {
2226 uint64_t offset;
2227
2228 r = evergreen_cs_packet_next_reloc(p, &reloc);
2229 if (r) {
2230 DRM_ERROR("bad EVENT_WRITE\n");
2231 return -EINVAL;
2232 }
2233 offset = reloc->lobj.gpu_offset +
2234 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2235 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2236
2237 ib[idx+1] = offset & 0xfffffff8;
2238 ib[idx+2] = upper_32_bits(offset) & 0xff;
2239 }
2240 break;
2241 case PACKET3_EVENT_WRITE_EOP:
2242 {
2243 uint64_t offset;
2244
2245 if (pkt->count != 4) {
2246 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2247 return -EINVAL;
2248 }
2249 r = evergreen_cs_packet_next_reloc(p, &reloc);
2250 if (r) {
2251 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2252 return -EINVAL;
2253 }
2254
2255 offset = reloc->lobj.gpu_offset +
2256 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2257 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2258
2259 ib[idx+1] = offset & 0xfffffffc;
2260 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2261 break;
2262 }
2263 case PACKET3_EVENT_WRITE_EOS:
2264 {
2265 uint64_t offset;
2266
2267 if (pkt->count != 3) {
2268 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2269 return -EINVAL;
2270 }
2271 r = evergreen_cs_packet_next_reloc(p, &reloc);
2272 if (r) {
2273 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2274 return -EINVAL;
2275 }
2276
2277 offset = reloc->lobj.gpu_offset +
2278 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2279 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2280
2281 ib[idx+1] = offset & 0xfffffffc;
2282 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2283 break;
2284 }
2285 case PACKET3_SET_CONFIG_REG:
2286 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2287 end_reg = 4 * pkt->count + start_reg - 4;
2288 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2289 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2290 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2291 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2292 return -EINVAL;
2293 }
2294 for (i = 0; i < pkt->count; i++) {
2295 reg = start_reg + (4 * i);
2296 r = evergreen_cs_check_reg(p, reg, idx+1+i);
2297 if (r)
2298 return r;
2299 }
2300 break;
2301 case PACKET3_SET_CONTEXT_REG:
2302 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2303 end_reg = 4 * pkt->count + start_reg - 4;
2304 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
2305 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2306 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2307 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2308 return -EINVAL;
2309 }
2310 for (i = 0; i < pkt->count; i++) {
2311 reg = start_reg + (4 * i);
2312 r = evergreen_cs_check_reg(p, reg, idx+1+i);
2313 if (r)
2314 return r;
2315 }
2316 break;
2317 case PACKET3_SET_RESOURCE:
2318 if (pkt->count % 8) {
2319 DRM_ERROR("bad SET_RESOURCE\n");
2320 return -EINVAL;
2321 }
2322 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2323 end_reg = 4 * pkt->count + start_reg - 4;
2324 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
2325 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2326 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2327 DRM_ERROR("bad SET_RESOURCE\n");
2328 return -EINVAL;
2329 }
2330 for (i = 0; i < (pkt->count / 8); i++) {
2331 struct radeon_bo *texture, *mipmap;
2332 u32 toffset, moffset;
2333 u32 size, offset;
2334
2335 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2336 case SQ_TEX_VTX_VALID_TEXTURE:
2337
2338 r = evergreen_cs_packet_next_reloc(p, &reloc);
2339 if (r) {
2340 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2341 return -EINVAL;
2342 }
2343 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2344 ib[idx+1+(i*8)+1] |=
2345 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2346 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
2347 unsigned bankw, bankh, mtaspect, tile_split;
2348
2349 evergreen_tiling_fields(reloc->lobj.tiling_flags,
2350 &bankw, &bankh, &mtaspect,
2351 &tile_split);
2352 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
2353 ib[idx+1+(i*8)+7] |=
2354 TEX_BANK_WIDTH(bankw) |
2355 TEX_BANK_HEIGHT(bankh) |
2356 MACRO_TILE_ASPECT(mtaspect) |
2357 TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2358 }
2359 }
2360 texture = reloc->robj;
2361 toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2362
2363 r = evergreen_cs_packet_next_reloc(p, &reloc);
2364 if (r) {
2365 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2366 return -EINVAL;
2367 }
2368 moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2369 mipmap = reloc->robj;
2370 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
2371 if (r)
2372 return r;
2373 ib[idx+1+(i*8)+2] += toffset;
2374 ib[idx+1+(i*8)+3] += moffset;
2375 break;
2376 case SQ_TEX_VTX_VALID_BUFFER:
2377 {
2378 uint64_t offset64;
2379
2380 r = evergreen_cs_packet_next_reloc(p, &reloc);
2381 if (r) {
2382 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2383 return -EINVAL;
2384 }
2385 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2386 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2387 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2388
2389 dev_warn(p->dev, "vbo resource seems too big for the bo\n");
2390 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2391 }
2392
2393 offset64 = reloc->lobj.gpu_offset + offset;
2394 ib[idx+1+(i*8)+0] = offset64;
2395 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2396 (upper_32_bits(offset64) & 0xff);
2397 break;
2398 }
2399 case SQ_TEX_VTX_INVALID_TEXTURE:
2400 case SQ_TEX_VTX_INVALID_BUFFER:
2401 default:
2402 DRM_ERROR("bad SET_RESOURCE\n");
2403 return -EINVAL;
2404 }
2405 }
2406 break;
2407 case PACKET3_SET_ALU_CONST:
2408
2409 break;
2410 case PACKET3_SET_BOOL_CONST:
2411 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2412 end_reg = 4 * pkt->count + start_reg - 4;
2413 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
2414 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2415 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2416 DRM_ERROR("bad SET_BOOL_CONST\n");
2417 return -EINVAL;
2418 }
2419 break;
2420 case PACKET3_SET_LOOP_CONST:
2421 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2422 end_reg = 4 * pkt->count + start_reg - 4;
2423 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
2424 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2425 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2426 DRM_ERROR("bad SET_LOOP_CONST\n");
2427 return -EINVAL;
2428 }
2429 break;
2430 case PACKET3_SET_CTL_CONST:
2431 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2432 end_reg = 4 * pkt->count + start_reg - 4;
2433 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
2434 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2435 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2436 DRM_ERROR("bad SET_CTL_CONST\n");
2437 return -EINVAL;
2438 }
2439 break;
2440 case PACKET3_SET_SAMPLER:
2441 if (pkt->count % 3) {
2442 DRM_ERROR("bad SET_SAMPLER\n");
2443 return -EINVAL;
2444 }
2445 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2446 end_reg = 4 * pkt->count + start_reg - 4;
2447 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
2448 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2449 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2450 DRM_ERROR("bad SET_SAMPLER\n");
2451 return -EINVAL;
2452 }
2453 break;
2454 case PACKET3_STRMOUT_BUFFER_UPDATE:
2455 if (pkt->count != 4) {
2456 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2457 return -EINVAL;
2458 }
2459
2460 if (idx_value & 0x1) {
2461 u64 offset;
2462 r = evergreen_cs_packet_next_reloc(p, &reloc);
2463 if (r) {
2464 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2465 return -EINVAL;
2466 }
2467 offset = radeon_get_ib_value(p, idx+1);
2468 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2469 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2470 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2471 offset + 4, radeon_bo_size(reloc->robj));
2472 return -EINVAL;
2473 }
2474 offset += reloc->lobj.gpu_offset;
2475 ib[idx+1] = offset;
2476 ib[idx+2] = upper_32_bits(offset) & 0xff;
2477 }
2478
2479 if (((idx_value >> 1) & 0x3) == 2) {
2480 u64 offset;
2481 r = evergreen_cs_packet_next_reloc(p, &reloc);
2482 if (r) {
2483 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2484 return -EINVAL;
2485 }
2486 offset = radeon_get_ib_value(p, idx+3);
2487 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2488 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2489 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2490 offset + 4, radeon_bo_size(reloc->robj));
2491 return -EINVAL;
2492 }
2493 offset += reloc->lobj.gpu_offset;
2494 ib[idx+3] = offset;
2495 ib[idx+4] = upper_32_bits(offset) & 0xff;
2496 }
2497 break;
2498 case PACKET3_COPY_DW:
2499 if (pkt->count != 4) {
2500 DRM_ERROR("bad COPY_DW (invalid count)\n");
2501 return -EINVAL;
2502 }
2503 if (idx_value & 0x1) {
2504 u64 offset;
2505
2506 r = evergreen_cs_packet_next_reloc(p, &reloc);
2507 if (r) {
2508 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2509 return -EINVAL;
2510 }
2511 offset = radeon_get_ib_value(p, idx+1);
2512 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2513 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2514 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2515 offset + 4, radeon_bo_size(reloc->robj));
2516 return -EINVAL;
2517 }
2518 offset += reloc->lobj.gpu_offset;
2519 ib[idx+1] = offset;
2520 ib[idx+2] = upper_32_bits(offset) & 0xff;
2521 } else {
2522
2523 reg = radeon_get_ib_value(p, idx+1) << 2;
2524 if (!evergreen_is_safe_reg(p, reg, idx+1))
2525 return -EINVAL;
2526 }
2527 if (idx_value & 0x2) {
2528 u64 offset;
2529
2530 r = evergreen_cs_packet_next_reloc(p, &reloc);
2531 if (r) {
2532 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2533 return -EINVAL;
2534 }
2535 offset = radeon_get_ib_value(p, idx+3);
2536 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2537 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2538 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2539 offset + 4, radeon_bo_size(reloc->robj));
2540 return -EINVAL;
2541 }
2542 offset += reloc->lobj.gpu_offset;
2543 ib[idx+3] = offset;
2544 ib[idx+4] = upper_32_bits(offset) & 0xff;
2545 } else {
2546
2547 reg = radeon_get_ib_value(p, idx+3) << 2;
2548 if (!evergreen_is_safe_reg(p, reg, idx+3))
2549 return -EINVAL;
2550 }
2551 break;
2552 case PACKET3_NOP:
2553 break;
2554 default:
2555 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2556 return -EINVAL;
2557 }
2558 return 0;
2559}
2560
2561int evergreen_cs_parse(struct radeon_cs_parser *p)
2562{
2563 struct radeon_cs_packet pkt;
2564 struct evergreen_cs_track *track;
2565 u32 tmp;
2566 int r;
2567
2568 if (p->track == NULL) {
2569
2570 track = kzalloc(sizeof(*track), GFP_KERNEL);
2571 if (track == NULL)
2572 return -ENOMEM;
2573 evergreen_cs_track_init(track);
2574 if (p->rdev->family >= CHIP_CAYMAN)
2575 tmp = p->rdev->config.cayman.tile_config;
2576 else
2577 tmp = p->rdev->config.evergreen.tile_config;
2578
2579 switch (tmp & 0xf) {
2580 case 0:
2581 track->npipes = 1;
2582 break;
2583 case 1:
2584 default:
2585 track->npipes = 2;
2586 break;
2587 case 2:
2588 track->npipes = 4;
2589 break;
2590 case 3:
2591 track->npipes = 8;
2592 break;
2593 }
2594
2595 switch ((tmp & 0xf0) >> 4) {
2596 case 0:
2597 track->nbanks = 4;
2598 break;
2599 case 1:
2600 default:
2601 track->nbanks = 8;
2602 break;
2603 case 2:
2604 track->nbanks = 16;
2605 break;
2606 }
2607
2608 switch ((tmp & 0xf00) >> 8) {
2609 case 0:
2610 track->group_size = 256;
2611 break;
2612 case 1:
2613 default:
2614 track->group_size = 512;
2615 break;
2616 }
2617
2618 switch ((tmp & 0xf000) >> 12) {
2619 case 0:
2620 track->row_size = 1;
2621 break;
2622 case 1:
2623 default:
2624 track->row_size = 2;
2625 break;
2626 case 2:
2627 track->row_size = 4;
2628 break;
2629 }
2630
2631 p->track = track;
2632 }
2633 do {
2634 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
2635 if (r) {
2636 kfree(p->track);
2637 p->track = NULL;
2638 return r;
2639 }
2640 p->idx += pkt.count + 2;
2641 switch (pkt.type) {
2642 case PACKET_TYPE0:
2643 r = evergreen_cs_parse_packet0(p, &pkt);
2644 break;
2645 case PACKET_TYPE2:
2646 break;
2647 case PACKET_TYPE3:
2648 r = evergreen_packet3_check(p, &pkt);
2649 break;
2650 default:
2651 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2652 kfree(p->track);
2653 p->track = NULL;
2654 return -EINVAL;
2655 }
2656 if (r) {
2657 kfree(p->track);
2658 p->track = NULL;
2659 return r;
2660 }
2661 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2662#if 0
2663 for (r = 0; r < p->ib.length_dw; r++) {
2664 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
2665 mdelay(1);
2666 }
2667#endif
2668 kfree(p->track);
2669 p->track = NULL;
2670 return 0;
2671}
2672
2673
2674static bool evergreen_vm_reg_valid(u32 reg)
2675{
2676
2677 if (reg >= 0x28000)
2678 return true;
2679
2680
2681 switch (reg) {
2682 case GRBM_GFX_INDEX:
2683 case VGT_VTX_VECT_EJECT_REG:
2684 case VGT_CACHE_INVALIDATION:
2685 case VGT_GS_VERTEX_REUSE:
2686 case VGT_PRIMITIVE_TYPE:
2687 case VGT_INDEX_TYPE:
2688 case VGT_NUM_INDICES:
2689 case VGT_NUM_INSTANCES:
2690 case VGT_COMPUTE_DIM_X:
2691 case VGT_COMPUTE_DIM_Y:
2692 case VGT_COMPUTE_DIM_Z:
2693 case VGT_COMPUTE_START_X:
2694 case VGT_COMPUTE_START_Y:
2695 case VGT_COMPUTE_START_Z:
2696 case VGT_COMPUTE_INDEX:
2697 case VGT_COMPUTE_THREAD_GROUP_SIZE:
2698 case VGT_HS_OFFCHIP_PARAM:
2699 case PA_CL_ENHANCE:
2700 case PA_SU_LINE_STIPPLE_VALUE:
2701 case PA_SC_LINE_STIPPLE_STATE:
2702 case PA_SC_ENHANCE:
2703 case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
2704 case SQ_DYN_GPR_SIMD_LOCK_EN:
2705 case SQ_CONFIG:
2706 case SQ_GPR_RESOURCE_MGMT_1:
2707 case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
2708 case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
2709 case SQ_CONST_MEM_BASE:
2710 case SQ_STATIC_THREAD_MGMT_1:
2711 case SQ_STATIC_THREAD_MGMT_2:
2712 case SQ_STATIC_THREAD_MGMT_3:
2713 case SPI_CONFIG_CNTL:
2714 case SPI_CONFIG_CNTL_1:
2715 case TA_CNTL_AUX:
2716 case DB_DEBUG:
2717 case DB_DEBUG2:
2718 case DB_DEBUG3:
2719 case DB_DEBUG4:
2720 case DB_WATERMARKS:
2721 case TD_PS_BORDER_COLOR_INDEX:
2722 case TD_PS_BORDER_COLOR_RED:
2723 case TD_PS_BORDER_COLOR_GREEN:
2724 case TD_PS_BORDER_COLOR_BLUE:
2725 case TD_PS_BORDER_COLOR_ALPHA:
2726 case TD_VS_BORDER_COLOR_INDEX:
2727 case TD_VS_BORDER_COLOR_RED:
2728 case TD_VS_BORDER_COLOR_GREEN:
2729 case TD_VS_BORDER_COLOR_BLUE:
2730 case TD_VS_BORDER_COLOR_ALPHA:
2731 case TD_GS_BORDER_COLOR_INDEX:
2732 case TD_GS_BORDER_COLOR_RED:
2733 case TD_GS_BORDER_COLOR_GREEN:
2734 case TD_GS_BORDER_COLOR_BLUE:
2735 case TD_GS_BORDER_COLOR_ALPHA:
2736 case TD_HS_BORDER_COLOR_INDEX:
2737 case TD_HS_BORDER_COLOR_RED:
2738 case TD_HS_BORDER_COLOR_GREEN:
2739 case TD_HS_BORDER_COLOR_BLUE:
2740 case TD_HS_BORDER_COLOR_ALPHA:
2741 case TD_LS_BORDER_COLOR_INDEX:
2742 case TD_LS_BORDER_COLOR_RED:
2743 case TD_LS_BORDER_COLOR_GREEN:
2744 case TD_LS_BORDER_COLOR_BLUE:
2745 case TD_LS_BORDER_COLOR_ALPHA:
2746 case TD_CS_BORDER_COLOR_INDEX:
2747 case TD_CS_BORDER_COLOR_RED:
2748 case TD_CS_BORDER_COLOR_GREEN:
2749 case TD_CS_BORDER_COLOR_BLUE:
2750 case TD_CS_BORDER_COLOR_ALPHA:
2751 case SQ_ESGS_RING_SIZE:
2752 case SQ_GSVS_RING_SIZE:
2753 case SQ_ESTMP_RING_SIZE:
2754 case SQ_GSTMP_RING_SIZE:
2755 case SQ_HSTMP_RING_SIZE:
2756 case SQ_LSTMP_RING_SIZE:
2757 case SQ_PSTMP_RING_SIZE:
2758 case SQ_VSTMP_RING_SIZE:
2759 case SQ_ESGS_RING_ITEMSIZE:
2760 case SQ_ESTMP_RING_ITEMSIZE:
2761 case SQ_GSTMP_RING_ITEMSIZE:
2762 case SQ_GSVS_RING_ITEMSIZE:
2763 case SQ_GS_VERT_ITEMSIZE:
2764 case SQ_GS_VERT_ITEMSIZE_1:
2765 case SQ_GS_VERT_ITEMSIZE_2:
2766 case SQ_GS_VERT_ITEMSIZE_3:
2767 case SQ_GSVS_RING_OFFSET_1:
2768 case SQ_GSVS_RING_OFFSET_2:
2769 case SQ_GSVS_RING_OFFSET_3:
2770 case SQ_HSTMP_RING_ITEMSIZE:
2771 case SQ_LSTMP_RING_ITEMSIZE:
2772 case SQ_PSTMP_RING_ITEMSIZE:
2773 case SQ_VSTMP_RING_ITEMSIZE:
2774 case VGT_TF_RING_SIZE:
2775 case SQ_ESGS_RING_BASE:
2776 case SQ_GSVS_RING_BASE:
2777 case SQ_ESTMP_RING_BASE:
2778 case SQ_GSTMP_RING_BASE:
2779 case SQ_HSTMP_RING_BASE:
2780 case SQ_LSTMP_RING_BASE:
2781 case SQ_PSTMP_RING_BASE:
2782 case SQ_VSTMP_RING_BASE:
2783 case CAYMAN_VGT_OFFCHIP_LDS_BASE:
2784 case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
2785 return true;
2786 default:
2787 return false;
2788 }
2789}
2790
2791static int evergreen_vm_packet3_check(struct radeon_device *rdev,
2792 u32 *ib, struct radeon_cs_packet *pkt)
2793{
2794 u32 idx = pkt->idx + 1;
2795 u32 idx_value = ib[idx];
2796 u32 start_reg, end_reg, reg, i;
2797
2798 switch (pkt->opcode) {
2799 case PACKET3_NOP:
2800 case PACKET3_SET_BASE:
2801 case PACKET3_CLEAR_STATE:
2802 case PACKET3_INDEX_BUFFER_SIZE:
2803 case PACKET3_DISPATCH_DIRECT:
2804 case PACKET3_DISPATCH_INDIRECT:
2805 case PACKET3_MODE_CONTROL:
2806 case PACKET3_SET_PREDICATION:
2807 case PACKET3_COND_EXEC:
2808 case PACKET3_PRED_EXEC:
2809 case PACKET3_DRAW_INDIRECT:
2810 case PACKET3_DRAW_INDEX_INDIRECT:
2811 case PACKET3_INDEX_BASE:
2812 case PACKET3_DRAW_INDEX_2:
2813 case PACKET3_CONTEXT_CONTROL:
2814 case PACKET3_DRAW_INDEX_OFFSET:
2815 case PACKET3_INDEX_TYPE:
2816 case PACKET3_DRAW_INDEX:
2817 case PACKET3_DRAW_INDEX_AUTO:
2818 case PACKET3_DRAW_INDEX_IMMD:
2819 case PACKET3_NUM_INSTANCES:
2820 case PACKET3_DRAW_INDEX_MULTI_AUTO:
2821 case PACKET3_STRMOUT_BUFFER_UPDATE:
2822 case PACKET3_DRAW_INDEX_OFFSET_2:
2823 case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2824 case PACKET3_MPEG_INDEX:
2825 case PACKET3_WAIT_REG_MEM:
2826 case PACKET3_MEM_WRITE:
2827 case PACKET3_SURFACE_SYNC:
2828 case PACKET3_EVENT_WRITE:
2829 case PACKET3_EVENT_WRITE_EOP:
2830 case PACKET3_EVENT_WRITE_EOS:
2831 case PACKET3_SET_CONTEXT_REG:
2832 case PACKET3_SET_BOOL_CONST:
2833 case PACKET3_SET_LOOP_CONST:
2834 case PACKET3_SET_RESOURCE:
2835 case PACKET3_SET_SAMPLER:
2836 case PACKET3_SET_CTL_CONST:
2837 case PACKET3_SET_RESOURCE_OFFSET:
2838 case PACKET3_SET_CONTEXT_REG_INDIRECT:
2839 case PACKET3_SET_RESOURCE_INDIRECT:
2840 case CAYMAN_PACKET3_DEALLOC_STATE:
2841 break;
2842 case PACKET3_COND_WRITE:
2843 if (idx_value & 0x100) {
2844 reg = ib[idx + 5] * 4;
2845 if (!evergreen_vm_reg_valid(reg))
2846 return -EINVAL;
2847 }
2848 break;
2849 case PACKET3_COPY_DW:
2850 if (idx_value & 0x2) {
2851 reg = ib[idx + 3] * 4;
2852 if (!evergreen_vm_reg_valid(reg))
2853 return -EINVAL;
2854 }
2855 break;
2856 case PACKET3_SET_CONFIG_REG:
2857 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2858 end_reg = 4 * pkt->count + start_reg - 4;
2859 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2860 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2861 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2862 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2863 return -EINVAL;
2864 }
2865 for (i = 0; i < pkt->count; i++) {
2866 reg = start_reg + (4 * i);
2867 if (!evergreen_vm_reg_valid(reg))
2868 return -EINVAL;
2869 }
2870 break;
2871 default:
2872 return -EINVAL;
2873 }
2874 return 0;
2875}
2876
2877int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2878{
2879 int ret = 0;
2880 u32 idx = 0;
2881 struct radeon_cs_packet pkt;
2882
2883 do {
2884 pkt.idx = idx;
2885 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2886 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2887 pkt.one_reg_wr = 0;
2888 switch (pkt.type) {
2889 case PACKET_TYPE0:
2890 dev_err(rdev->dev, "Packet0 not allowed!\n");
2891 ret = -EINVAL;
2892 break;
2893 case PACKET_TYPE2:
2894 idx += 1;
2895 break;
2896 case PACKET_TYPE3:
2897 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2898 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
2899 idx += pkt.count + 2;
2900 break;
2901 default:
2902 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2903 ret = -EINVAL;
2904 break;
2905 }
2906 if (ret)
2907 break;
2908 } while (idx < ib->length_dw);
2909
2910 return ret;
2911}
2912
