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31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34#include <linux/firmware.h>
35#include <linux/platform_device.h>
36
37#include "radeon_family.h"
38
39
40
41
42#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
43
44#define DRIVER_NAME "radeon"
45#define DRIVER_DESC "ATI Radeon"
46#define DRIVER_DATE "20080528"
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111
112#define DRIVER_MAJOR 1
113#define DRIVER_MINOR 33
114#define DRIVER_PATCHLEVEL 0
115
116enum radeon_cp_microcode_version {
117 UCODE_R100,
118 UCODE_R200,
119 UCODE_R300,
120};
121
122typedef struct drm_radeon_freelist {
123 unsigned int age;
124 struct drm_buf *buf;
125 struct drm_radeon_freelist *next;
126 struct drm_radeon_freelist *prev;
127} drm_radeon_freelist_t;
128
129typedef struct drm_radeon_ring_buffer {
130 u32 *start;
131 u32 *end;
132 int size;
133 int size_l2qw;
134
135 int rptr_update;
136 int rptr_update_l2qw;
137
138 int fetch_size;
139 int fetch_size_l2ow;
140
141 u32 tail;
142 u32 tail_mask;
143 int space;
144
145 int high_mark;
146} drm_radeon_ring_buffer_t;
147
148typedef struct drm_radeon_depth_clear_t {
149 u32 rb3d_cntl;
150 u32 rb3d_zstencilcntl;
151 u32 se_cntl;
152} drm_radeon_depth_clear_t;
153
154struct drm_radeon_driver_file_fields {
155 int64_t radeon_fb_delta;
156};
157
158struct mem_block {
159 struct mem_block *next;
160 struct mem_block *prev;
161 int start;
162 int size;
163 struct drm_file *file_priv;
164};
165
166struct radeon_surface {
167 int refcount;
168 u32 lower;
169 u32 upper;
170 u32 flags;
171};
172
173struct radeon_virt_surface {
174 int surface_index;
175 u32 lower;
176 u32 upper;
177 u32 flags;
178 struct drm_file *file_priv;
179#define PCIGART_FILE_PRIV ((void *) -1L)
180};
181
182#define RADEON_FLUSH_EMITED (1 << 0)
183#define RADEON_PURGE_EMITED (1 << 1)
184
185struct drm_radeon_master_private {
186 drm_local_map_t *sarea;
187 drm_radeon_sarea_t *sarea_priv;
188};
189
190typedef struct drm_radeon_private {
191 drm_radeon_ring_buffer_t ring;
192
193 u32 fb_location;
194 u32 fb_size;
195 int new_memmap;
196
197 int gart_size;
198 u32 gart_vm_start;
199 unsigned long gart_buffers_offset;
200
201 int cp_mode;
202 int cp_running;
203
204 drm_radeon_freelist_t *head;
205 drm_radeon_freelist_t *tail;
206 int last_buf;
207 int writeback_works;
208
209 int usec_timeout;
210
211 int microcode_version;
212
213 struct {
214 u32 boxes;
215 int freelist_timeouts;
216 int freelist_loops;
217 int requested_bufs;
218 int last_frame_reads;
219 int last_clear_reads;
220 int clears;
221 int texture_uploads;
222 } stats;
223
224 int do_boxes;
225 int page_flipping;
226
227 u32 color_fmt;
228 unsigned int front_offset;
229 unsigned int front_pitch;
230 unsigned int back_offset;
231 unsigned int back_pitch;
232
233 u32 depth_fmt;
234 unsigned int depth_offset;
235 unsigned int depth_pitch;
236
237 u32 front_pitch_offset;
238 u32 back_pitch_offset;
239 u32 depth_pitch_offset;
240
241 drm_radeon_depth_clear_t depth_clear;
242
243 unsigned long ring_offset;
244 unsigned long ring_rptr_offset;
245 unsigned long buffers_offset;
246 unsigned long gart_textures_offset;
247
248 drm_local_map_t *sarea;
249 drm_local_map_t *cp_ring;
250 drm_local_map_t *ring_rptr;
251 drm_local_map_t *gart_textures;
252
253 struct mem_block *gart_heap;
254 struct mem_block *fb_heap;
255
256
257 wait_queue_head_t swi_queue;
258 atomic_t swi_emitted;
259 int vblank_crtc;
260 uint32_t irq_enable_reg;
261 uint32_t r500_disp_irq_reg;
262
263 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
264 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
265
266 unsigned long pcigart_offset;
267 unsigned int pcigart_offset_set;
268 struct drm_ati_pcigart_info gart_info;
269
270 u32 scratch_ages[5];
271
272 int have_z_offset;
273
274
275 uint32_t flags;
276 resource_size_t fb_aper_offset;
277
278 int num_gb_pipes;
279 int num_z_pipes;
280 int track_flush;
281 drm_local_map_t *mmio;
282
283
284 int r600_max_pipes;
285 int r600_max_tile_pipes;
286 int r600_max_simds;
287 int r600_max_backends;
288 int r600_max_gprs;
289 int r600_max_threads;
290 int r600_max_stack_entries;
291 int r600_max_hw_contexts;
292 int r600_max_gs_threads;
293 int r600_sx_max_export_size;
294 int r600_sx_max_export_pos_size;
295 int r600_sx_max_export_smx_size;
296 int r600_sq_num_cf_insts;
297 int r700_sx_num_of_sets;
298 int r700_sc_prim_fifo_size;
299 int r700_sc_hiz_tile_fifo_size;
300 int r700_sc_earlyz_tile_fifo_fize;
301 int r600_group_size;
302 int r600_npipes;
303 int r600_nbanks;
304
305 struct mutex cs_mutex;
306 u32 cs_id_scnt;
307 u32 cs_id_wcnt;
308
309 struct drm_buf *blit_vb;
310
311
312 const struct firmware *me_fw, *pfp_fw;
313} drm_radeon_private_t;
314
315typedef struct drm_radeon_buf_priv {
316 u32 age;
317} drm_radeon_buf_priv_t;
318
319struct drm_buffer;
320
321typedef struct drm_radeon_kcmd_buffer {
322 int bufsz;
323 struct drm_buffer *buffer;
324 int nbox;
325 struct drm_clip_rect __user *boxes;
326} drm_radeon_kcmd_buffer_t;
327
328extern int radeon_no_wb;
329extern struct drm_ioctl_desc radeon_ioctls[];
330extern int radeon_max_ioctl;
331
332extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
333extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
334
335#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
336#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
337
338
339
340
341static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
342 u64 off)
343{
344 u32 fb_start = dev_priv->fb_location;
345 u32 fb_end = fb_start + dev_priv->fb_size - 1;
346 u32 gart_start = dev_priv->gart_vm_start;
347 u32 gart_end = gart_start + dev_priv->gart_size - 1;
348
349 return ((off >= fb_start && off <= fb_end) ||
350 (off >= gart_start && off <= gart_end));
351}
352
353
354extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
355
356
357extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
358extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
359extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
360extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
361extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
362extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
363extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
364extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
365extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
366extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
367extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
368extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
369extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
370
371extern void radeon_freelist_reset(struct drm_device * dev);
372extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
373
374extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
375
376extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
377
378extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
379extern int radeon_presetup(struct drm_device *dev);
380extern int radeon_driver_postcleanup(struct drm_device *dev);
381
382extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
383extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
384extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
385extern void radeon_mem_takedown(struct mem_block **heap);
386extern void radeon_mem_release(struct drm_file *file_priv,
387 struct mem_block *heap);
388
389extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
390extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
391extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
392
393
394extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
395extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
396extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
397
398extern void radeon_do_release(struct drm_device * dev);
399extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
400extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
401extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
402extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
403extern void radeon_driver_irq_preinstall(struct drm_device * dev);
404extern int radeon_driver_irq_postinstall(struct drm_device *dev);
405extern void radeon_driver_irq_uninstall(struct drm_device * dev);
406extern void radeon_enable_interrupt(struct drm_device *dev);
407extern int radeon_vblank_crtc_get(struct drm_device *dev);
408extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
409
410extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
411extern int radeon_driver_unload(struct drm_device *dev);
412extern int radeon_driver_firstopen(struct drm_device *dev);
413extern void radeon_driver_preclose(struct drm_device *dev,
414 struct drm_file *file_priv);
415extern void radeon_driver_postclose(struct drm_device *dev,
416 struct drm_file *file_priv);
417extern void radeon_driver_lastclose(struct drm_device * dev);
418extern int radeon_driver_open(struct drm_device *dev,
419 struct drm_file *file_priv);
420extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
421 unsigned long arg);
422extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
423 unsigned long arg);
424
425extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
426extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
427extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
428
429extern void r300_init_reg_flags(struct drm_device *dev);
430
431extern int r300_do_cp_cmdbuf(struct drm_device *dev,
432 struct drm_file *file_priv,
433 drm_radeon_kcmd_buffer_t *cmdbuf);
434
435
436extern int r600_do_engine_reset(struct drm_device *dev);
437extern int r600_do_cleanup_cp(struct drm_device *dev);
438extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
439 struct drm_file *file_priv);
440extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
441extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
442extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
443extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
444extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
445extern int r600_cp_dispatch_indirect(struct drm_device *dev,
446 struct drm_buf *buf, int start, int end);
447extern int r600_page_table_init(struct drm_device *dev);
448extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
449extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
450extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
451extern int r600_cp_dispatch_texture(struct drm_device *dev,
452 struct drm_file *file_priv,
453 drm_radeon_texture_t *tex,
454 drm_radeon_tex_image_t *image);
455
456extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
457extern void r600_done_blit_copy(struct drm_device *dev);
458extern void r600_blit_copy(struct drm_device *dev,
459 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
460 int size_bytes);
461extern void r600_blit_swap(struct drm_device *dev,
462 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
463 int sx, int sy, int dx, int dy,
464 int w, int h, int src_pitch, int dst_pitch, int cpp);
465
466
467#if defined(CONFIG_VGA_SWITCHEROO)
468void radeon_register_atpx_handler(void);
469void radeon_unregister_atpx_handler(void);
470#else
471static inline void radeon_register_atpx_handler(void) {}
472static inline void radeon_unregister_atpx_handler(void) {}
473#endif
474
475
476
477#define RADEON_BOX_DMA_IDLE 0x1
478#define RADEON_BOX_RING_FULL 0x2
479#define RADEON_BOX_FLIP 0x4
480#define RADEON_BOX_WAIT_IDLE 0x8
481#define RADEON_BOX_TEXTURE_LOAD 0x10
482
483
484
485
486#define RADEON_MM_INDEX 0x0000
487#define RADEON_MM_DATA 0x0004
488
489#define RADEON_AGP_COMMAND 0x0f60
490#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060
491# define RADEON_AGP_ENABLE (1<<8)
492#define RADEON_AUX_SCISSOR_CNTL 0x26f0
493# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
494# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
495# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
496# define RADEON_SCISSOR_0_ENABLE (1 << 28)
497# define RADEON_SCISSOR_1_ENABLE (1 << 29)
498# define RADEON_SCISSOR_2_ENABLE (1 << 30)
499
500
501
502
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504
505
506#define RADEON_BUS_CNTL 0x0030
507
508# define RADEON_BUS_MASTER_DIS (1 << 6)
509
510# define RS600_BUS_MASTER_DIS (1 << 14)
511# define RS600_MSI_REARM (1 << 20)
512
513
514#define RADEON_BUS_CNTL1 0x0034
515# define RADEON_PMI_BM_DIS (1 << 2)
516# define RADEON_PMI_INT_DIS (1 << 3)
517
518#define RV370_BUS_CNTL 0x004c
519# define RV370_PMI_BM_DIS (1 << 5)
520# define RV370_PMI_INT_DIS (1 << 6)
521
522#define RADEON_MSI_REARM_EN 0x0160
523
524# define RV370_MSI_REARM_EN (1 << 0)
525
526#define RADEON_CLOCK_CNTL_DATA 0x000c
527# define RADEON_PLL_WR_EN (1 << 7)
528#define RADEON_CLOCK_CNTL_INDEX 0x0008
529#define RADEON_CONFIG_APER_SIZE 0x0108
530#define RADEON_CONFIG_MEMSIZE 0x00f8
531#define RADEON_CRTC_OFFSET 0x0224
532#define RADEON_CRTC_OFFSET_CNTL 0x0228
533# define RADEON_CRTC_TILE_EN (1 << 15)
534# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
535#define RADEON_CRTC2_OFFSET 0x0324
536#define RADEON_CRTC2_OFFSET_CNTL 0x0328
537
538#define RADEON_PCIE_INDEX 0x0030
539#define RADEON_PCIE_DATA 0x0034
540#define RADEON_PCIE_TX_GART_CNTL 0x10
541# define RADEON_PCIE_TX_GART_EN (1 << 0)
542# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
543# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
544# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
545# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
546# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
547# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
548# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
549#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
550#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
551#define RADEON_PCIE_TX_GART_BASE 0x13
552#define RADEON_PCIE_TX_GART_START_LO 0x14
553#define RADEON_PCIE_TX_GART_START_HI 0x15
554#define RADEON_PCIE_TX_GART_END_LO 0x16
555#define RADEON_PCIE_TX_GART_END_HI 0x17
556
557#define RS480_NB_MC_INDEX 0x168
558# define RS480_NB_MC_IND_WR_EN (1 << 8)
559#define RS480_NB_MC_DATA 0x16c
560
561#define RS690_MC_INDEX 0x78
562# define RS690_MC_INDEX_MASK 0x1ff
563# define RS690_MC_INDEX_WR_EN (1 << 9)
564# define RS690_MC_INDEX_WR_ACK 0x7f
565#define RS690_MC_DATA 0x7c
566
567
568#define RS480_MC_MISC_CNTL 0x18
569# define RS480_DISABLE_GTW (1 << 1)
570
571# define RS480_GART_INDEX_REG_EN (1 << 12)
572# define RS690_BLOCK_GFX_D3_EN (1 << 14)
573#define RS480_K8_FB_LOCATION 0x1e
574#define RS480_GART_FEATURE_ID 0x2b
575# define RS480_HANG_EN (1 << 11)
576# define RS480_TLB_ENABLE (1 << 18)
577# define RS480_P2P_ENABLE (1 << 19)
578# define RS480_GTW_LAC_EN (1 << 25)
579# define RS480_2LEVEL_GART (0 << 30)
580# define RS480_1LEVEL_GART (1 << 30)
581# define RS480_PDC_EN (1 << 31)
582#define RS480_GART_BASE 0x2c
583#define RS480_GART_CACHE_CNTRL 0x2e
584# define RS480_GART_CACHE_INVALIDATE (1 << 0)
585#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
586# define RS480_GART_EN (1 << 0)
587# define RS480_VA_SIZE_32MB (0 << 1)
588# define RS480_VA_SIZE_64MB (1 << 1)
589# define RS480_VA_SIZE_128MB (2 << 1)
590# define RS480_VA_SIZE_256MB (3 << 1)
591# define RS480_VA_SIZE_512MB (4 << 1)
592# define RS480_VA_SIZE_1GB (5 << 1)
593# define RS480_VA_SIZE_2GB (6 << 1)
594#define RS480_AGP_MODE_CNTL 0x39
595# define RS480_POST_GART_Q_SIZE (1 << 18)
596# define RS480_NONGART_SNOOP (1 << 19)
597# define RS480_AGP_RD_BUF_SIZE (1 << 20)
598# define RS480_REQ_TYPE_SNOOP_SHIFT 22
599# define RS480_REQ_TYPE_SNOOP_MASK 0x3
600# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
601#define RS480_MC_MISC_UMA_CNTL 0x5f
602#define RS480_MC_MCLK_CNTL 0x7a
603#define RS480_MC_UMA_DUALCH_CNTL 0x86
604
605#define RS690_MC_FB_LOCATION 0x100
606#define RS690_MC_AGP_LOCATION 0x101
607#define RS690_MC_AGP_BASE 0x102
608#define RS690_MC_AGP_BASE_2 0x103
609
610#define RS600_MC_INDEX 0x70
611# define RS600_MC_ADDR_MASK 0xffff
612# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
613# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
614# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
615# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
616# define RS600_MC_IND_AIC_RBS (1 << 20)
617# define RS600_MC_IND_CITF_ARB0 (1 << 21)
618# define RS600_MC_IND_CITF_ARB1 (1 << 22)
619# define RS600_MC_IND_WR_EN (1 << 23)
620#define RS600_MC_DATA 0x74
621
622#define RS600_MC_STATUS 0x0
623# define RS600_MC_IDLE (1 << 1)
624#define RS600_MC_FB_LOCATION 0x4
625#define RS600_MC_AGP_LOCATION 0x5
626#define RS600_AGP_BASE 0x6
627#define RS600_AGP_BASE_2 0x7
628#define RS600_MC_CNTL1 0x9
629# define RS600_ENABLE_PAGE_TABLES (1 << 26)
630#define RS600_MC_PT0_CNTL 0x100
631# define RS600_ENABLE_PT (1 << 0)
632# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
633# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
634# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
635# define RS600_INVALIDATE_L2_CACHE (1 << 29)
636#define RS600_MC_PT0_CONTEXT0_CNTL 0x102
637# define RS600_ENABLE_PAGE_TABLE (1 << 0)
638# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
639#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
640#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
641#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
642#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
643#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
644#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
645#define RS600_MC_PT0_CLIENT0_CNTL 0x16c
646# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
647# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
648# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
649# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
650# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
651# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
652# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
653# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
654# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
655# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
656# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
657# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
658# define RS600_INVALIDATE_L1_TLB (1 << 20)
659
660#define R520_MC_IND_INDEX 0x70
661#define R520_MC_IND_WR_EN (1 << 24)
662#define R520_MC_IND_DATA 0x74
663
664#define RV515_MC_FB_LOCATION 0x01
665#define RV515_MC_AGP_LOCATION 0x02
666#define RV515_MC_AGP_BASE 0x03
667#define RV515_MC_AGP_BASE_2 0x04
668
669#define R520_MC_FB_LOCATION 0x04
670#define R520_MC_AGP_LOCATION 0x05
671#define R520_MC_AGP_BASE 0x06
672#define R520_MC_AGP_BASE_2 0x07
673
674#define RADEON_MPP_TB_CONFIG 0x01c0
675#define RADEON_MEM_CNTL 0x0140
676#define RADEON_MEM_SDRAM_MODE_REG 0x0158
677#define RADEON_AGP_BASE_2 0x015c
678#define RS480_AGP_BASE_2 0x0164
679#define RADEON_AGP_BASE 0x0170
680
681
682#define R400_GB_PIPE_SELECT 0x402c
683#define RV530_GB_PIPE_SELECT2 0x4124
684#define R500_DYN_SCLK_PWMEM_PIPE 0x000d
685#define R300_GB_TILE_CONFIG 0x4018
686# define R300_ENABLE_TILING (1 << 0)
687# define R300_PIPE_COUNT_RV350 (0 << 1)
688# define R300_PIPE_COUNT_R300 (3 << 1)
689# define R300_PIPE_COUNT_R420_3P (6 << 1)
690# define R300_PIPE_COUNT_R420 (7 << 1)
691# define R300_TILE_SIZE_8 (0 << 4)
692# define R300_TILE_SIZE_16 (1 << 4)
693# define R300_TILE_SIZE_32 (2 << 4)
694# define R300_SUBPIXEL_1_12 (0 << 16)
695# define R300_SUBPIXEL_1_16 (1 << 16)
696#define R300_DST_PIPE_CONFIG 0x170c
697# define R300_PIPE_AUTO_CONFIG (1 << 31)
698#define R300_RB2D_DSTCACHE_MODE 0x3428
699# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
700# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
701
702#define RADEON_RB3D_COLOROFFSET 0x1c40
703#define RADEON_RB3D_COLORPITCH 0x1c48
704
705#define RADEON_SRC_X_Y 0x1590
706
707#define RADEON_DP_GUI_MASTER_CNTL 0x146c
708# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
709# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
710# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
711# define RADEON_GMC_BRUSH_NONE (15 << 4)
712# define RADEON_GMC_DST_16BPP (4 << 8)
713# define RADEON_GMC_DST_24BPP (5 << 8)
714# define RADEON_GMC_DST_32BPP (6 << 8)
715# define RADEON_GMC_DST_DATATYPE_SHIFT 8
716# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
717# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
718# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
719# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
720# define RADEON_GMC_WR_MSK_DIS (1 << 30)
721# define RADEON_ROP3_S 0x00cc0000
722# define RADEON_ROP3_P 0x00f00000
723#define RADEON_DP_WRITE_MASK 0x16cc
724#define RADEON_SRC_PITCH_OFFSET 0x1428
725#define RADEON_DST_PITCH_OFFSET 0x142c
726#define RADEON_DST_PITCH_OFFSET_C 0x1c80
727# define RADEON_DST_TILE_LINEAR (0 << 30)
728# define RADEON_DST_TILE_MACRO (1 << 30)
729# define RADEON_DST_TILE_MICRO (2 << 30)
730# define RADEON_DST_TILE_BOTH (3 << 30)
731
732#define RADEON_SCRATCH_REG0 0x15e0
733#define RADEON_SCRATCH_REG1 0x15e4
734#define RADEON_SCRATCH_REG2 0x15e8
735#define RADEON_SCRATCH_REG3 0x15ec
736#define RADEON_SCRATCH_REG4 0x15f0
737#define RADEON_SCRATCH_REG5 0x15f4
738#define RADEON_SCRATCH_UMSK 0x0770
739#define RADEON_SCRATCH_ADDR 0x0774
740
741#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
742
743extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
744
745#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
746
747#define R600_SCRATCH_REG0 0x8500
748#define R600_SCRATCH_REG1 0x8504
749#define R600_SCRATCH_REG2 0x8508
750#define R600_SCRATCH_REG3 0x850c
751#define R600_SCRATCH_REG4 0x8510
752#define R600_SCRATCH_REG5 0x8514
753#define R600_SCRATCH_REG6 0x8518
754#define R600_SCRATCH_REG7 0x851c
755#define R600_SCRATCH_UMSK 0x8540
756#define R600_SCRATCH_ADDR 0x8544
757
758#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
759
760#define RADEON_GEN_INT_CNTL 0x0040
761# define RADEON_CRTC_VBLANK_MASK (1 << 0)
762# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
763# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
764# define RADEON_SW_INT_ENABLE (1 << 25)
765
766#define RADEON_GEN_INT_STATUS 0x0044
767# define RADEON_CRTC_VBLANK_STAT (1 << 0)
768# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
769# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
770# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
771# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
772# define RADEON_SW_INT_TEST (1 << 25)
773# define RADEON_SW_INT_TEST_ACK (1 << 25)
774# define RADEON_SW_INT_FIRE (1 << 26)
775# define R500_DISPLAY_INT_STATUS (1 << 0)
776
777#define RADEON_HOST_PATH_CNTL 0x0130
778# define RADEON_HDP_SOFT_RESET (1 << 26)
779# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
780# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
781
782#define RADEON_ISYNC_CNTL 0x1724
783# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
784# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
785# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
786# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
787# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
788# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
789
790#define RADEON_RBBM_GUICNTL 0x172c
791# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
792# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
793# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
794# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
795
796#define RADEON_MC_AGP_LOCATION 0x014c
797#define RADEON_MC_FB_LOCATION 0x0148
798#define RADEON_MCLK_CNTL 0x0012
799# define RADEON_FORCEON_MCLKA (1 << 16)
800# define RADEON_FORCEON_MCLKB (1 << 17)
801# define RADEON_FORCEON_YCLKA (1 << 18)
802# define RADEON_FORCEON_YCLKB (1 << 19)
803# define RADEON_FORCEON_MC (1 << 20)
804# define RADEON_FORCEON_AIC (1 << 21)
805
806#define RADEON_PP_BORDER_COLOR_0 0x1d40
807#define RADEON_PP_BORDER_COLOR_1 0x1d44
808#define RADEON_PP_BORDER_COLOR_2 0x1d48
809#define RADEON_PP_CNTL 0x1c38
810# define RADEON_SCISSOR_ENABLE (1 << 1)
811#define RADEON_PP_LUM_MATRIX 0x1d00
812#define RADEON_PP_MISC 0x1c14
813#define RADEON_PP_ROT_MATRIX_0 0x1d58
814#define RADEON_PP_TXFILTER_0 0x1c54
815#define RADEON_PP_TXOFFSET_0 0x1c5c
816#define RADEON_PP_TXFILTER_1 0x1c6c
817#define RADEON_PP_TXFILTER_2 0x1c84
818
819#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c
820#define R300_DSTCACHE_CTLSTAT 0x1714
821# define R300_RB2D_DC_FLUSH (3 << 0)
822# define R300_RB2D_DC_FREE (3 << 2)
823# define R300_RB2D_DC_FLUSH_ALL 0xf
824# define R300_RB2D_DC_BUSY (1 << 31)
825#define RADEON_RB3D_CNTL 0x1c3c
826# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
827# define RADEON_PLANE_MASK_ENABLE (1 << 1)
828# define RADEON_DITHER_ENABLE (1 << 2)
829# define RADEON_ROUND_ENABLE (1 << 3)
830# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
831# define RADEON_DITHER_INIT (1 << 5)
832# define RADEON_ROP_ENABLE (1 << 6)
833# define RADEON_STENCIL_ENABLE (1 << 7)
834# define RADEON_Z_ENABLE (1 << 8)
835# define RADEON_ZBLOCK16 (1 << 15)
836#define RADEON_RB3D_DEPTHOFFSET 0x1c24
837#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
838#define RADEON_RB3D_DEPTHPITCH 0x1c28
839#define RADEON_RB3D_PLANEMASK 0x1d84
840#define RADEON_RB3D_STENCILREFMASK 0x1d7c
841#define RADEON_RB3D_ZCACHE_MODE 0x3250
842#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
843# define RADEON_RB3D_ZC_FLUSH (1 << 0)
844# define RADEON_RB3D_ZC_FREE (1 << 2)
845# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
846# define RADEON_RB3D_ZC_BUSY (1 << 31)
847#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
848# define R300_ZC_FLUSH (1 << 0)
849# define R300_ZC_FREE (1 << 1)
850# define R300_ZC_BUSY (1 << 31)
851#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
852# define RADEON_RB3D_DC_FLUSH (3 << 0)
853# define RADEON_RB3D_DC_FREE (3 << 2)
854# define RADEON_RB3D_DC_FLUSH_ALL 0xf
855# define RADEON_RB3D_DC_BUSY (1 << 31)
856#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
857# define R300_RB3D_DC_FLUSH (2 << 0)
858# define R300_RB3D_DC_FREE (2 << 2)
859# define R300_RB3D_DC_FINISH (1 << 4)
860#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
861# define RADEON_Z_TEST_MASK (7 << 4)
862# define RADEON_Z_TEST_ALWAYS (7 << 4)
863# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
864# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
865# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
866# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
867# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
868# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
869# define RADEON_FORCE_Z_DIRTY (1 << 29)
870# define RADEON_Z_WRITE_ENABLE (1 << 30)
871# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
872#define RADEON_RBBM_SOFT_RESET 0x00f0
873# define RADEON_SOFT_RESET_CP (1 << 0)
874# define RADEON_SOFT_RESET_HI (1 << 1)
875# define RADEON_SOFT_RESET_SE (1 << 2)
876# define RADEON_SOFT_RESET_RE (1 << 3)
877# define RADEON_SOFT_RESET_PP (1 << 4)
878# define RADEON_SOFT_RESET_E2 (1 << 5)
879# define RADEON_SOFT_RESET_RB (1 << 6)
880# define RADEON_SOFT_RESET_HDP (1 << 7)
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900#define RADEON_RBBM_STATUS 0x0e40
901
902
903
904# define RADEON_RBBM_FIFOCNT_MASK 0x007f
905# define RADEON_HIRQ_ON_RBB (1 << 8)
906# define RADEON_CPRQ_ON_RBB (1 << 9)
907# define RADEON_CFRQ_ON_RBB (1 << 10)
908# define RADEON_HIRQ_IN_RTBUF (1 << 11)
909# define RADEON_CPRQ_IN_RTBUF (1 << 12)
910# define RADEON_CFRQ_IN_RTBUF (1 << 13)
911# define RADEON_PIPE_BUSY (1 << 14)
912# define RADEON_ENG_EV_BUSY (1 << 15)
913# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
914# define RADEON_E2_BUSY (1 << 17)
915# define RADEON_RB2D_BUSY (1 << 18)
916# define RADEON_RB3D_BUSY (1 << 19)
917# define RADEON_VAP_BUSY (1 << 20)
918# define RADEON_RE_BUSY (1 << 21)
919# define RADEON_TAM_BUSY (1 << 22)
920# define RADEON_TDM_BUSY (1 << 23)
921# define RADEON_PB_BUSY (1 << 24)
922# define RADEON_TIM_BUSY (1 << 25)
923# define RADEON_GA_BUSY (1 << 26)
924# define RADEON_CBA2D_BUSY (1 << 27)
925# define RADEON_RBBM_ACTIVE (1 << 31)
926#define RADEON_RE_LINE_PATTERN 0x1cd0
927#define RADEON_RE_MISC 0x26c4
928#define RADEON_RE_TOP_LEFT 0x26c0
929#define RADEON_RE_WIDTH_HEIGHT 0x1c44
930#define RADEON_RE_STIPPLE_ADDR 0x1cc8
931#define RADEON_RE_STIPPLE_DATA 0x1ccc
932
933#define RADEON_SCISSOR_TL_0 0x1cd8
934#define RADEON_SCISSOR_BR_0 0x1cdc
935#define RADEON_SCISSOR_TL_1 0x1ce0
936#define RADEON_SCISSOR_BR_1 0x1ce4
937#define RADEON_SCISSOR_TL_2 0x1ce8
938#define RADEON_SCISSOR_BR_2 0x1cec
939#define RADEON_SE_COORD_FMT 0x1c50
940#define RADEON_SE_CNTL 0x1c4c
941# define RADEON_FFACE_CULL_CW (0 << 0)
942# define RADEON_BFACE_SOLID (3 << 1)
943# define RADEON_FFACE_SOLID (3 << 3)
944# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
945# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
946# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
947# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
948# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
949# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
950# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
951# define RADEON_FOG_SHADE_FLAT (1 << 14)
952# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
953# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
954# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
955# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
956# define RADEON_ROUND_MODE_TRUNC (0 << 28)
957# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
958#define RADEON_SE_CNTL_STATUS 0x2140
959#define RADEON_SE_LINE_WIDTH 0x1db8
960#define RADEON_SE_VPORT_XSCALE 0x1d98
961#define RADEON_SE_ZBIAS_FACTOR 0x1db0
962#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
963#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
964#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
965# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
966# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
967#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
968#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
969# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
970#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
971#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
972#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
973#define RADEON_SURFACE_CNTL 0x0b00
974# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
975# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
976# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
977# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
978# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
979# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
980# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
981# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
982# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
983#define RADEON_SURFACE0_INFO 0x0b0c
984# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
985# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
986# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
987# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
988# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
989# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
990#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
991#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
992# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
993#define RADEON_SURFACE1_INFO 0x0b1c
994#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
995#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
996#define RADEON_SURFACE2_INFO 0x0b2c
997#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
998#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
999#define RADEON_SURFACE3_INFO 0x0b3c
1000#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
1001#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
1002#define RADEON_SURFACE4_INFO 0x0b4c
1003#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1004#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1005#define RADEON_SURFACE5_INFO 0x0b5c
1006#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1007#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1008#define RADEON_SURFACE6_INFO 0x0b6c
1009#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1010#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1011#define RADEON_SURFACE7_INFO 0x0b7c
1012#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1013#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1014#define RADEON_SW_SEMAPHORE 0x013c
1015
1016#define RADEON_WAIT_UNTIL 0x1720
1017# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1018# define RADEON_WAIT_2D_IDLE (1 << 14)
1019# define RADEON_WAIT_3D_IDLE (1 << 15)
1020# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1021# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1022# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1023
1024#define RADEON_RB3D_ZMASKOFFSET 0x3234
1025#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
1026# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1027# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1028
1029
1030#define RADEON_CP_ME_RAM_ADDR 0x07d4
1031#define RADEON_CP_ME_RAM_RADDR 0x07d8
1032#define RADEON_CP_ME_RAM_DATAH 0x07dc
1033#define RADEON_CP_ME_RAM_DATAL 0x07e0
1034
1035#define RADEON_CP_RB_BASE 0x0700
1036#define RADEON_CP_RB_CNTL 0x0704
1037# define RADEON_BUF_SWAP_32BIT (2 << 16)
1038# define RADEON_RB_NO_UPDATE (1 << 27)
1039# define RADEON_RB_RPTR_WR_ENA (1 << 31)
1040#define RADEON_CP_RB_RPTR_ADDR 0x070c
1041#define RADEON_CP_RB_RPTR 0x0710
1042#define RADEON_CP_RB_WPTR 0x0714
1043
1044#define RADEON_CP_RB_WPTR_DELAY 0x0718
1045# define RADEON_PRE_WRITE_TIMER_SHIFT 0
1046# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1047
1048#define RADEON_CP_IB_BASE 0x0738
1049
1050#define RADEON_CP_CSQ_CNTL 0x0740
1051# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1052# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1053# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1054# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1055# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1056# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1057# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1058
1059#define R300_CP_RESYNC_ADDR 0x0778
1060#define R300_CP_RESYNC_DATA 0x077c
1061
1062#define RADEON_AIC_CNTL 0x01d0
1063# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
1064# define RS400_MSI_REARM (1 << 3)
1065#define RADEON_AIC_STAT 0x01d4
1066#define RADEON_AIC_PT_BASE 0x01d8
1067#define RADEON_AIC_LO_ADDR 0x01dc
1068#define RADEON_AIC_HI_ADDR 0x01e0
1069#define RADEON_AIC_TLB_ADDR 0x01e4
1070#define RADEON_AIC_TLB_DATA 0x01e8
1071
1072
1073#define RADEON_CP_PACKET0 0x00000000
1074# define RADEON_ONE_REG_WR (1 << 15)
1075#define RADEON_CP_PACKET1 0x40000000
1076#define RADEON_CP_PACKET2 0x80000000
1077#define RADEON_CP_PACKET3 0xC0000000
1078# define RADEON_CP_NOP 0x00001000
1079# define RADEON_CP_NEXT_CHAR 0x00001900
1080# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1081# define RADEON_CP_SET_SCISSORS 0x00001E00
1082
1083# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1084# define RADEON_WAIT_FOR_IDLE 0x00002600
1085# define RADEON_3D_DRAW_VBUF 0x00002800
1086# define RADEON_3D_DRAW_IMMD 0x00002900
1087# define RADEON_3D_DRAW_INDX 0x00002A00
1088# define RADEON_CP_LOAD_PALETTE 0x00002C00
1089# define RADEON_3D_LOAD_VBPNTR 0x00002F00
1090# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1091# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1092# define RADEON_3D_CLEAR_ZMASK 0x00003200
1093# define RADEON_CP_INDX_BUFFER 0x00003300
1094# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1095# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1096# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1097# define RADEON_3D_CLEAR_HIZ 0x00003700
1098# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1099# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1100# define RADEON_CNTL_PAINT_MULTI 0x00009A00
1101# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1102# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1103
1104# define R600_IT_INDIRECT_BUFFER_END 0x00001700
1105# define R600_IT_SET_PREDICATION 0x00002000
1106# define R600_IT_REG_RMW 0x00002100
1107# define R600_IT_COND_EXEC 0x00002200
1108# define R600_IT_PRED_EXEC 0x00002300
1109# define R600_IT_START_3D_CMDBUF 0x00002400
1110# define R600_IT_DRAW_INDEX_2 0x00002700
1111# define R600_IT_CONTEXT_CONTROL 0x00002800
1112# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
1113# define R600_IT_INDEX_TYPE 0x00002A00
1114# define R600_IT_DRAW_INDEX 0x00002B00
1115# define R600_IT_DRAW_INDEX_AUTO 0x00002D00
1116# define R600_IT_DRAW_INDEX_IMMD 0x00002E00
1117# define R600_IT_NUM_INSTANCES 0x00002F00
1118# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
1119# define R600_IT_INDIRECT_BUFFER_MP 0x00003800
1120# define R600_IT_MEM_SEMAPHORE 0x00003900
1121# define R600_IT_MPEG_INDEX 0x00003A00
1122# define R600_IT_WAIT_REG_MEM 0x00003C00
1123# define R600_IT_MEM_WRITE 0x00003D00
1124# define R600_IT_INDIRECT_BUFFER 0x00003200
1125# define R600_IT_SURFACE_SYNC 0x00004300
1126# define R600_CB0_DEST_BASE_ENA (1 << 6)
1127# define R600_TC_ACTION_ENA (1 << 23)
1128# define R600_VC_ACTION_ENA (1 << 24)
1129# define R600_CB_ACTION_ENA (1 << 25)
1130# define R600_DB_ACTION_ENA (1 << 26)
1131# define R600_SH_ACTION_ENA (1 << 27)
1132# define R600_SMX_ACTION_ENA (1 << 28)
1133# define R600_IT_ME_INITIALIZE 0x00004400
1134# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1135# define R600_IT_COND_WRITE 0x00004500
1136# define R600_IT_EVENT_WRITE 0x00004600
1137# define R600_IT_EVENT_WRITE_EOP 0x00004700
1138# define R600_IT_ONE_REG_WRITE 0x00005700
1139# define R600_IT_SET_CONFIG_REG 0x00006800
1140# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1141# define R600_SET_CONFIG_REG_END 0x0000ac00
1142# define R600_IT_SET_CONTEXT_REG 0x00006900
1143# define R600_SET_CONTEXT_REG_OFFSET 0x00028000
1144# define R600_SET_CONTEXT_REG_END 0x00029000
1145# define R600_IT_SET_ALU_CONST 0x00006A00
1146# define R600_SET_ALU_CONST_OFFSET 0x00030000
1147# define R600_SET_ALU_CONST_END 0x00032000
1148# define R600_IT_SET_BOOL_CONST 0x00006B00
1149# define R600_SET_BOOL_CONST_OFFSET 0x0003e380
1150# define R600_SET_BOOL_CONST_END 0x00040000
1151# define R600_IT_SET_LOOP_CONST 0x00006C00
1152# define R600_SET_LOOP_CONST_OFFSET 0x0003e200
1153# define R600_SET_LOOP_CONST_END 0x0003e380
1154# define R600_IT_SET_RESOURCE 0x00006D00
1155# define R600_SET_RESOURCE_OFFSET 0x00038000
1156# define R600_SET_RESOURCE_END 0x0003c000
1157# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
1158# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
1159# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
1160# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
1161# define R600_IT_SET_SAMPLER 0x00006E00
1162# define R600_SET_SAMPLER_OFFSET 0x0003c000
1163# define R600_SET_SAMPLER_END 0x0003cff0
1164# define R600_IT_SET_CTL_CONST 0x00006F00
1165# define R600_SET_CTL_CONST_OFFSET 0x0003cff0
1166# define R600_SET_CTL_CONST_END 0x0003e200
1167# define R600_IT_SURFACE_BASE_UPDATE 0x00007300
1168
1169#define RADEON_CP_PACKET_MASK 0xC0000000
1170#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1171#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1172#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1173#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1174
1175#define RADEON_VTX_Z_PRESENT (1 << 31)
1176#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1177
1178#define RADEON_PRIM_TYPE_NONE (0 << 0)
1179#define RADEON_PRIM_TYPE_POINT (1 << 0)
1180#define RADEON_PRIM_TYPE_LINE (2 << 0)
1181#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1182#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1183#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1184#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1185#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1186#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1187#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1188#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1189#define RADEON_PRIM_TYPE_MASK 0xf
1190#define RADEON_PRIM_WALK_IND (1 << 4)
1191#define RADEON_PRIM_WALK_LIST (2 << 4)
1192#define RADEON_PRIM_WALK_RING (3 << 4)
1193#define RADEON_COLOR_ORDER_BGRA (0 << 6)
1194#define RADEON_COLOR_ORDER_RGBA (1 << 6)
1195#define RADEON_MAOS_ENABLE (1 << 7)
1196#define RADEON_VTX_FMT_R128_MODE (0 << 8)
1197#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1198#define RADEON_NUM_VERTICES_SHIFT 16
1199
1200#define RADEON_COLOR_FORMAT_CI8 2
1201#define RADEON_COLOR_FORMAT_ARGB1555 3
1202#define RADEON_COLOR_FORMAT_RGB565 4
1203#define RADEON_COLOR_FORMAT_ARGB8888 6
1204#define RADEON_COLOR_FORMAT_RGB332 7
1205#define RADEON_COLOR_FORMAT_RGB8 9
1206#define RADEON_COLOR_FORMAT_ARGB4444 15
1207
1208#define RADEON_TXFORMAT_I8 0
1209#define RADEON_TXFORMAT_AI88 1
1210#define RADEON_TXFORMAT_RGB332 2
1211#define RADEON_TXFORMAT_ARGB1555 3
1212#define RADEON_TXFORMAT_RGB565 4
1213#define RADEON_TXFORMAT_ARGB4444 5
1214#define RADEON_TXFORMAT_ARGB8888 6
1215#define RADEON_TXFORMAT_RGBA8888 7
1216#define RADEON_TXFORMAT_Y8 8
1217#define RADEON_TXFORMAT_VYUY422 10
1218#define RADEON_TXFORMAT_YVYU422 11
1219#define RADEON_TXFORMAT_DXT1 12
1220#define RADEON_TXFORMAT_DXT23 14
1221#define RADEON_TXFORMAT_DXT45 15
1222
1223#define R200_PP_TXCBLEND_0 0x2f00
1224#define R200_PP_TXCBLEND_1 0x2f10
1225#define R200_PP_TXCBLEND_2 0x2f20
1226#define R200_PP_TXCBLEND_3 0x2f30
1227#define R200_PP_TXCBLEND_4 0x2f40
1228#define R200_PP_TXCBLEND_5 0x2f50
1229#define R200_PP_TXCBLEND_6 0x2f60
1230#define R200_PP_TXCBLEND_7 0x2f70
1231#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1232#define R200_PP_TFACTOR_0 0x2ee0
1233#define R200_SE_VTX_FMT_0 0x2088
1234#define R200_SE_VAP_CNTL 0x2080
1235#define R200_SE_TCL_MATRIX_SEL_0 0x2230
1236#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1237#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1238#define R200_PP_TXFILTER_5 0x2ca0
1239#define R200_PP_TXFILTER_4 0x2c80
1240#define R200_PP_TXFILTER_3 0x2c60
1241#define R200_PP_TXFILTER_2 0x2c40
1242#define R200_PP_TXFILTER_1 0x2c20
1243#define R200_PP_TXFILTER_0 0x2c00
1244#define R200_PP_TXOFFSET_5 0x2d78
1245#define R200_PP_TXOFFSET_4 0x2d60
1246#define R200_PP_TXOFFSET_3 0x2d48
1247#define R200_PP_TXOFFSET_2 0x2d30
1248#define R200_PP_TXOFFSET_1 0x2d18
1249#define R200_PP_TXOFFSET_0 0x2d00
1250
1251#define R200_PP_CUBIC_FACES_0 0x2c18
1252#define R200_PP_CUBIC_FACES_1 0x2c38
1253#define R200_PP_CUBIC_FACES_2 0x2c58
1254#define R200_PP_CUBIC_FACES_3 0x2c78
1255#define R200_PP_CUBIC_FACES_4 0x2c98
1256#define R200_PP_CUBIC_FACES_5 0x2cb8
1257#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1258#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1259#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1260#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1261#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1262#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1263#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1264#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1265#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1266#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1267#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1268#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1269#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1270#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1271#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1272#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1273#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1274#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1275#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1276#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1277#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1278#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1279#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1280#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1281#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1282#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1283#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1284#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1285#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1286#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1287
1288#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1289#define R200_SE_VTE_CNTL 0x20b0
1290#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1291#define R200_PP_TAM_DEBUG3 0x2d9c
1292#define R200_PP_CNTL_X 0x2cc4
1293#define R200_SE_VAP_CNTL_STATUS 0x2140
1294#define R200_RE_SCISSOR_TL_0 0x1cd8
1295#define R200_RE_SCISSOR_TL_1 0x1ce0
1296#define R200_RE_SCISSOR_TL_2 0x1ce8
1297#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1298#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1299#define R200_SE_VTX_STATE_CNTL 0x2180
1300#define R200_RE_POINTSIZE 0x2648
1301#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1302
1303#define RADEON_PP_TEX_SIZE_0 0x1d04
1304#define RADEON_PP_TEX_SIZE_1 0x1d0c
1305#define RADEON_PP_TEX_SIZE_2 0x1d14
1306
1307#define RADEON_PP_CUBIC_FACES_0 0x1d24
1308#define RADEON_PP_CUBIC_FACES_1 0x1d28
1309#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1310#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0
1311#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1312#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1313
1314#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1315
1316#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1317#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1318#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1319#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1320#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1321#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1322#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1323#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1324#define R200_3D_DRAW_IMMD_2 0xC0003500
1325#define R200_SE_VTX_FMT_1 0x208c
1326#define R200_RE_CNTL 0x1c50
1327
1328#define R200_RB3D_BLENDCOLOR 0x3218
1329
1330#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1331
1332#define R200_PP_TRI_PERF 0x2cf8
1333
1334#define R200_PP_AFS_0 0x2f80
1335#define R200_PP_AFS_1 0x2f00
1336
1337#define R200_VAP_PVS_CNTL_1 0x22D0
1338
1339#define RADEON_CRTC_CRNT_FRAME 0x0214
1340#define RADEON_CRTC2_CRNT_FRAME 0x0314
1341
1342#define R500_D1CRTC_STATUS 0x609c
1343#define R500_D2CRTC_STATUS 0x689c
1344#define R500_CRTC_V_BLANK (1<<0)
1345
1346#define R500_D1CRTC_FRAME_COUNT 0x60a4
1347#define R500_D2CRTC_FRAME_COUNT 0x68a4
1348
1349#define R500_D1MODE_V_COUNTER 0x6530
1350#define R500_D2MODE_V_COUNTER 0x6d30
1351
1352#define R500_D1MODE_VBLANK_STATUS 0x6534
1353#define R500_D2MODE_VBLANK_STATUS 0x6d34
1354#define R500_VBLANK_OCCURED (1<<0)
1355#define R500_VBLANK_ACK (1<<4)
1356#define R500_VBLANK_STAT (1<<12)
1357#define R500_VBLANK_INT (1<<16)
1358
1359#define R500_DxMODE_INT_MASK 0x6540
1360#define R500_D1MODE_INT_MASK (1<<0)
1361#define R500_D2MODE_INT_MASK (1<<8)
1362
1363#define R500_DISP_INTERRUPT_STATUS 0x7edc
1364#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1365#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1366
1367
1368#define R600_MC_VM_FB_LOCATION 0x2180
1369#define R600_MC_VM_AGP_TOP 0x2184
1370#define R600_MC_VM_AGP_BOT 0x2188
1371#define R600_MC_VM_AGP_BASE 0x218c
1372#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1373#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1374#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1375
1376#define R700_MC_VM_FB_LOCATION 0x2024
1377#define R700_MC_VM_AGP_TOP 0x2028
1378#define R700_MC_VM_AGP_BOT 0x202c
1379#define R700_MC_VM_AGP_BASE 0x2030
1380#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1381#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1382#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1383
1384#define R600_MCD_RD_A_CNTL 0x219c
1385#define R600_MCD_RD_B_CNTL 0x21a0
1386
1387#define R600_MCD_WR_A_CNTL 0x21a4
1388#define R600_MCD_WR_B_CNTL 0x21a8
1389
1390#define R600_MCD_RD_SYS_CNTL 0x2200
1391#define R600_MCD_WR_SYS_CNTL 0x2214
1392
1393#define R600_MCD_RD_GFX_CNTL 0x21fc
1394#define R600_MCD_RD_HDP_CNTL 0x2204
1395#define R600_MCD_RD_PDMA_CNTL 0x2208
1396#define R600_MCD_RD_SEM_CNTL 0x220c
1397#define R600_MCD_WR_GFX_CNTL 0x2210
1398#define R600_MCD_WR_HDP_CNTL 0x2218
1399#define R600_MCD_WR_PDMA_CNTL 0x221c
1400#define R600_MCD_WR_SEM_CNTL 0x2220
1401
1402# define R600_MCD_L1_TLB (1 << 0)
1403# define R600_MCD_L1_FRAG_PROC (1 << 1)
1404# define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1405
1406# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1407# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1408# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1409# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1410# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1411
1412# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1413# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1414
1415# define R600_MCD_SEMAPHORE_MODE (1 << 10)
1416# define R600_MCD_WAIT_L2_QUERY (1 << 11)
1417# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1418# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1419
1420#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1421#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1422#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1423
1424#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1425#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1426#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1427#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1428
1429# define R700_ENABLE_L1_TLB (1 << 0)
1430# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1431# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1432# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1433# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1434# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1435
1436#define R700_MC_ARB_RAMCFG 0x2760
1437# define R700_NOOFBANK_SHIFT 0
1438# define R700_NOOFBANK_MASK 0x3
1439# define R700_NOOFRANK_SHIFT 2
1440# define R700_NOOFRANK_MASK 0x1
1441# define R700_NOOFROWS_SHIFT 3
1442# define R700_NOOFROWS_MASK 0x7
1443# define R700_NOOFCOLS_SHIFT 6
1444# define R700_NOOFCOLS_MASK 0x3
1445# define R700_CHANSIZE_SHIFT 8
1446# define R700_CHANSIZE_MASK 0x1
1447# define R700_BURSTLENGTH_SHIFT 9
1448# define R700_BURSTLENGTH_MASK 0x1
1449#define R600_RAMCFG 0x2408
1450# define R600_NOOFBANK_SHIFT 0
1451# define R600_NOOFBANK_MASK 0x1
1452# define R600_NOOFRANK_SHIFT 1
1453# define R600_NOOFRANK_MASK 0x1
1454# define R600_NOOFROWS_SHIFT 2
1455# define R600_NOOFROWS_MASK 0x7
1456# define R600_NOOFCOLS_SHIFT 5
1457# define R600_NOOFCOLS_MASK 0x3
1458# define R600_CHANSIZE_SHIFT 7
1459# define R600_CHANSIZE_MASK 0x1
1460# define R600_BURSTLENGTH_SHIFT 8
1461# define R600_BURSTLENGTH_MASK 0x1
1462
1463#define R600_VM_L2_CNTL 0x1400
1464# define R600_VM_L2_CACHE_EN (1 << 0)
1465# define R600_VM_L2_FRAG_PROC (1 << 1)
1466# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1467# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1468# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1469
1470#define R600_VM_L2_CNTL2 0x1404
1471# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1472# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1473#define R600_VM_L2_CNTL3 0x1408
1474# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1475# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1476# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1477# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1478# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1479
1480#define R600_VM_L2_STATUS 0x140c
1481
1482#define R600_VM_CONTEXT0_CNTL 0x1410
1483# define R600_VM_ENABLE_CONTEXT (1 << 0)
1484# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1485
1486#define R600_VM_CONTEXT0_CNTL2 0x1430
1487#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1488#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1489#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1490#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1491#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1492#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1493
1494#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1495#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1496#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1497
1498#define R600_HDP_HOST_PATH_CNTL 0x2c00
1499
1500#define R600_GRBM_CNTL 0x8000
1501# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1502
1503#define R600_GRBM_STATUS 0x8010
1504# define R600_CMDFIFO_AVAIL_MASK 0x1f
1505# define R700_CMDFIFO_AVAIL_MASK 0xf
1506# define R600_GUI_ACTIVE (1 << 31)
1507#define R600_GRBM_STATUS2 0x8014
1508#define R600_GRBM_SOFT_RESET 0x8020
1509# define R600_SOFT_RESET_CP (1 << 0)
1510#define R600_WAIT_UNTIL 0x8040
1511
1512#define R600_CP_SEM_WAIT_TIMER 0x85bc
1513#define R600_CP_ME_CNTL 0x86d8
1514# define R600_CP_ME_HALT (1 << 28)
1515#define R600_CP_QUEUE_THRESHOLDS 0x8760
1516# define R600_ROQ_IB1_START(x) ((x) << 0)
1517# define R600_ROQ_IB2_START(x) ((x) << 8)
1518#define R600_CP_MEQ_THRESHOLDS 0x8764
1519# define R700_STQ_SPLIT(x) ((x) << 0)
1520# define R600_MEQ_END(x) ((x) << 16)
1521# define R600_ROQ_END(x) ((x) << 24)
1522#define R600_CP_PERFMON_CNTL 0x87fc
1523#define R600_CP_RB_BASE 0xc100
1524#define R600_CP_RB_CNTL 0xc104
1525# define R600_RB_BUFSZ(x) ((x) << 0)
1526# define R600_RB_BLKSZ(x) ((x) << 8)
1527# define R600_BUF_SWAP_32BIT (2 << 16)
1528# define R600_RB_NO_UPDATE (1 << 27)
1529# define R600_RB_RPTR_WR_ENA (1 << 31)
1530#define R600_CP_RB_RPTR_WR 0xc108
1531#define R600_CP_RB_RPTR_ADDR 0xc10c
1532#define R600_CP_RB_RPTR_ADDR_HI 0xc110
1533#define R600_CP_RB_WPTR 0xc114
1534#define R600_CP_RB_WPTR_ADDR 0xc118
1535#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1536#define R600_CP_RB_RPTR 0x8700
1537#define R600_CP_RB_WPTR_DELAY 0x8704
1538#define R600_CP_PFP_UCODE_ADDR 0xc150
1539#define R600_CP_PFP_UCODE_DATA 0xc154
1540#define R600_CP_ME_RAM_RADDR 0xc158
1541#define R600_CP_ME_RAM_WADDR 0xc15c
1542#define R600_CP_ME_RAM_DATA 0xc160
1543#define R600_CP_DEBUG 0xc1fc
1544
1545#define R600_PA_CL_ENHANCE 0x8a14
1546# define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1547# define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1548#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1549#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1550#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1551# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1552# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1553#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1554#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1555#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1556#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1557# define R600_S0_X(x) ((x) << 0)
1558# define R600_S0_Y(x) ((x) << 4)
1559# define R600_S1_X(x) ((x) << 8)
1560# define R600_S1_Y(x) ((x) << 12)
1561# define R600_S2_X(x) ((x) << 16)
1562# define R600_S2_Y(x) ((x) << 20)
1563# define R600_S3_X(x) ((x) << 24)
1564# define R600_S3_Y(x) ((x) << 28)
1565# define R600_S4_X(x) ((x) << 0)
1566# define R600_S4_Y(x) ((x) << 4)
1567# define R600_S5_X(x) ((x) << 8)
1568# define R600_S5_Y(x) ((x) << 12)
1569# define R600_S6_X(x) ((x) << 16)
1570# define R600_S6_Y(x) ((x) << 20)
1571# define R600_S7_X(x) ((x) << 24)
1572# define R600_S7_Y(x) ((x) << 28)
1573#define R600_PA_SC_FIFO_SIZE 0x8bd0
1574# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1575# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1576# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1577#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1578# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1579# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1580# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1581#define R600_PA_SC_ENHANCE 0x8bf0
1582# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1583# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1584#define R600_PA_SC_CLIPRECT_RULE 0x2820c
1585#define R700_PA_SC_EDGERULE 0x28230
1586#define R600_PA_SC_LINE_STIPPLE 0x28a0c
1587#define R600_PA_SC_MODE_CNTL 0x28a4c
1588#define R600_PA_SC_AA_CONFIG 0x28c04
1589
1590#define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1591# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1592# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1593# define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1594#define R600_SX_DEBUG_1 0x9054
1595# define R600_SMX_EVENT_RELEASE (1 << 0)
1596# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1597#define R700_SX_DEBUG_1 0x9058
1598# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1599#define R600_SX_MISC 0x28350
1600
1601#define R600_DB_DEBUG 0x9830
1602# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1603#define R600_DB_WATERMARKS 0x9838
1604# define R600_DEPTH_FREE(x) ((x) << 0)
1605# define R600_DEPTH_FLUSH(x) ((x) << 5)
1606# define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1607# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1608#define R700_DB_DEBUG3 0x98b0
1609# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1610#define RV700_DB_DEBUG4 0x9b8c
1611# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1612
1613#define R600_VGT_CACHE_INVALIDATION 0x88c4
1614# define R600_CACHE_INVALIDATION(x) ((x) << 0)
1615# define R600_VC_ONLY 0
1616# define R600_TC_ONLY 1
1617# define R600_VC_AND_TC 2
1618# define R700_AUTO_INVLD_EN(x) ((x) << 6)
1619# define R700_NO_AUTO 0
1620# define R700_ES_AUTO 1
1621# define R700_GS_AUTO 2
1622# define R700_ES_AND_GS_AUTO 3
1623#define R600_VGT_GS_PER_ES 0x88c8
1624#define R600_VGT_ES_PER_GS 0x88cc
1625#define R600_VGT_GS_PER_VS 0x88e8
1626#define R600_VGT_GS_VERTEX_REUSE 0x88d4
1627#define R600_VGT_NUM_INSTANCES 0x8974
1628#define R600_VGT_STRMOUT_EN 0x28ab0
1629#define R600_VGT_EVENT_INITIATOR 0x28a90
1630# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1631#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1632# define R600_VTX_REUSE_DEPTH_MASK 0xff
1633#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1634# define R600_DEALLOC_DIST_MASK 0x7f
1635
1636#define R600_CB_COLOR0_BASE 0x28040
1637#define R600_CB_COLOR1_BASE 0x28044
1638#define R600_CB_COLOR2_BASE 0x28048
1639#define R600_CB_COLOR3_BASE 0x2804c
1640#define R600_CB_COLOR4_BASE 0x28050
1641#define R600_CB_COLOR5_BASE 0x28054
1642#define R600_CB_COLOR6_BASE 0x28058
1643#define R600_CB_COLOR7_BASE 0x2805c
1644#define R600_CB_COLOR7_FRAG 0x280fc
1645
1646#define R600_CB_COLOR0_SIZE 0x28060
1647#define R600_CB_COLOR0_VIEW 0x28080
1648#define R600_CB_COLOR0_INFO 0x280a0
1649#define R600_CB_COLOR0_TILE 0x280c0
1650#define R600_CB_COLOR0_FRAG 0x280e0
1651#define R600_CB_COLOR0_MASK 0x28100
1652
1653#define AVIVO_D1MODE_VLINE_START_END 0x6538
1654#define AVIVO_D2MODE_VLINE_START_END 0x6d38
1655#define R600_CP_COHER_BASE 0x85f8
1656#define R600_DB_DEPTH_BASE 0x2800c
1657#define R600_SQ_PGM_START_FS 0x28894
1658#define R600_SQ_PGM_START_ES 0x28880
1659#define R600_SQ_PGM_START_VS 0x28858
1660#define R600_SQ_PGM_RESOURCES_VS 0x28868
1661#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1662#define R600_SQ_PGM_START_GS 0x2886c
1663#define R600_SQ_PGM_START_PS 0x28840
1664#define R600_SQ_PGM_RESOURCES_PS 0x28850
1665#define R600_SQ_PGM_EXPORTS_PS 0x28854
1666#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1667#define R600_VGT_DMA_BASE 0x287e8
1668#define R600_VGT_DMA_BASE_HI 0x287e4
1669#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
1670#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
1671#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
1672#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
1673#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
1674#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
1675#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
1676#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
1677#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
1678#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
1679#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
1680#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
1681#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
1682#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
1683#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
1684#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
1685
1686#define R600_VGT_PRIMITIVE_TYPE 0x8958
1687
1688#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1689#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1690#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1691
1692#define R600_TC_CNTL 0x9608
1693# define R600_TC_L2_SIZE(x) ((x) << 5)
1694# define R600_L2_DISABLE_LATE_HIT (1 << 9)
1695
1696#define R600_ARB_POP 0x2418
1697# define R600_ENABLE_TC128 (1 << 30)
1698#define R600_ARB_GDEC_RD_CNTL 0x246c
1699
1700#define R600_TA_CNTL_AUX 0x9508
1701# define R600_DISABLE_CUBE_WRAP (1 << 0)
1702# define R600_DISABLE_CUBE_ANISO (1 << 1)
1703# define R700_GETLOD_SELECT(x) ((x) << 2)
1704# define R600_SYNC_GRADIENT (1 << 24)
1705# define R600_SYNC_WALKER (1 << 25)
1706# define R600_SYNC_ALIGNER (1 << 26)
1707# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1708# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1709
1710#define R700_TCP_CNTL 0x9610
1711
1712#define R600_SMX_DC_CTL0 0xa020
1713# define R700_USE_HASH_FUNCTION (1 << 0)
1714# define R700_CACHE_DEPTH(x) ((x) << 1)
1715# define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1716# define R700_STALL_ON_EVENT (1 << 11)
1717#define R700_SMX_EVENT_CTL 0xa02c
1718# define R700_ES_FLUSH_CTL(x) ((x) << 0)
1719# define R700_GS_FLUSH_CTL(x) ((x) << 3)
1720# define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1721# define R700_SYNC_FLUSH_CTL (1 << 8)
1722
1723#define R600_SQ_CONFIG 0x8c00
1724# define R600_VC_ENABLE (1 << 0)
1725# define R600_EXPORT_SRC_C (1 << 1)
1726# define R600_DX9_CONSTS (1 << 2)
1727# define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1728# define R600_DX10_CLAMP (1 << 4)
1729# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1730# define R600_PS_PRIO(x) ((x) << 24)
1731# define R600_VS_PRIO(x) ((x) << 26)
1732# define R600_GS_PRIO(x) ((x) << 28)
1733# define R600_ES_PRIO(x) ((x) << 30)
1734#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1735# define R600_NUM_PS_GPRS(x) ((x) << 0)
1736# define R600_NUM_VS_GPRS(x) ((x) << 16)
1737# define R700_DYN_GPR_ENABLE (1 << 27)
1738# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1739#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1740# define R600_NUM_GS_GPRS(x) ((x) << 0)
1741# define R600_NUM_ES_GPRS(x) ((x) << 16)
1742#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1743# define R600_NUM_PS_THREADS(x) ((x) << 0)
1744# define R600_NUM_VS_THREADS(x) ((x) << 8)
1745# define R600_NUM_GS_THREADS(x) ((x) << 16)
1746# define R600_NUM_ES_THREADS(x) ((x) << 24)
1747#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1748# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1749# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1750#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1751# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1752# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1753#define R600_SQ_MS_FIFO_SIZES 0x8cf0
1754# define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1755# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1756# define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1757# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1758#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1759# define R700_SIMDA_RING0(x) ((x) << 0)
1760# define R700_SIMDA_RING1(x) ((x) << 8)
1761# define R700_SIMDB_RING0(x) ((x) << 16)
1762# define R700_SIMDB_RING1(x) ((x) << 24)
1763#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1764#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1765#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1766#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1767#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1768#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1769#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1770
1771#define R600_SPI_PS_IN_CONTROL_0 0x286cc
1772# define R600_NUM_INTERP(x) ((x) << 0)
1773# define R600_POSITION_ENA (1 << 8)
1774# define R600_POSITION_CENTROID (1 << 9)
1775# define R600_POSITION_ADDR(x) ((x) << 10)
1776# define R600_PARAM_GEN(x) ((x) << 15)
1777# define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1778# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1779# define R600_PERSP_GRADIENT_ENA (1 << 28)
1780# define R600_LINEAR_GRADIENT_ENA (1 << 29)
1781# define R600_POSITION_SAMPLE (1 << 30)
1782# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1783#define R600_SPI_PS_IN_CONTROL_1 0x286d0
1784# define R600_GEN_INDEX_PIX (1 << 0)
1785# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1786# define R600_FRONT_FACE_ENA (1 << 8)
1787# define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1788# define R600_FRONT_FACE_ALL_BITS (1 << 11)
1789# define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1790# define R600_FOG_ADDR(x) ((x) << 17)
1791# define R600_FIXED_PT_POSITION_ENA (1 << 24)
1792# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1793# define R700_POSITION_ULC (1 << 30)
1794#define R600_SPI_INPUT_Z 0x286d8
1795
1796#define R600_SPI_CONFIG_CNTL 0x9100
1797# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1798# define R600_DISABLE_INTERP_1 (1 << 5)
1799#define R600_SPI_CONFIG_CNTL_1 0x913c
1800# define R600_VTX_DONE_DELAY(x) ((x) << 0)
1801# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1802
1803#define R600_GB_TILING_CONFIG 0x98f0
1804# define R600_PIPE_TILING(x) ((x) << 1)
1805# define R600_BANK_TILING(x) ((x) << 4)
1806# define R600_GROUP_SIZE(x) ((x) << 6)
1807# define R600_ROW_TILING(x) ((x) << 8)
1808# define R600_BANK_SWAPS(x) ((x) << 11)
1809# define R600_SAMPLE_SPLIT(x) ((x) << 14)
1810# define R600_BACKEND_MAP(x) ((x) << 16)
1811#define R600_DCP_TILING_CONFIG 0x6ca0
1812#define R600_HDP_TILING_CONFIG 0x2f3c
1813
1814#define R600_CC_RB_BACKEND_DISABLE 0x98f4
1815#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1816# define R600_BACKEND_DISABLE(x) ((x) << 16)
1817
1818#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1819#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1820# define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1821# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1822# define R600_INACTIVE_SIMDS(x) ((x) << 16)
1823# define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1824
1825#define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1826#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1827#define R700_CGTS_TCC_DISABLE 0x9148
1828#define R700_CGTS_USER_TCC_DISABLE 0x914c
1829
1830
1831#define RADEON_MAX_USEC_TIMEOUT 100000
1832
1833#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1834#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1835#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1836#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1837#define RADEON_LAST_DISPATCH 1
1838
1839#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1840#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1841#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1842#define R600_LAST_SWI_REG R600_SCRATCH_REG3
1843
1844#define RADEON_MAX_VB_AGE 0x7fffffff
1845#define RADEON_MAX_VB_VERTS (0xffff)
1846
1847#define RADEON_RING_HIGH_MARK 128
1848
1849#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1850
1851#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1852#define RADEON_WRITE(reg, val) \
1853do { \
1854 if (reg < 0x10000) { \
1855 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1856 } else { \
1857 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1858 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1859 } \
1860} while (0)
1861#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1862#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1863
1864#define RADEON_WRITE_PLL(addr, val) \
1865do { \
1866 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1867 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1868 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1869} while (0)
1870
1871#define RADEON_WRITE_PCIE(addr, val) \
1872do { \
1873 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1874 ((addr) & 0xff)); \
1875 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1876} while (0)
1877
1878#define R500_WRITE_MCIND(addr, val) \
1879do { \
1880 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1881 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1882 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1883} while (0)
1884
1885#define RS480_WRITE_MCIND(addr, val) \
1886do { \
1887 RADEON_WRITE(RS480_NB_MC_INDEX, \
1888 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1889 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1890 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1891} while (0)
1892
1893#define RS690_WRITE_MCIND(addr, val) \
1894do { \
1895 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1896 RADEON_WRITE(RS690_MC_DATA, val); \
1897 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1898} while (0)
1899
1900#define RS600_WRITE_MCIND(addr, val) \
1901do { \
1902 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1903 RADEON_WRITE(RS600_MC_DATA, val); \
1904} while (0)
1905
1906#define IGP_WRITE_MCIND(addr, val) \
1907do { \
1908 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1909 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1910 RS690_WRITE_MCIND(addr, val); \
1911 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1912 RS600_WRITE_MCIND(addr, val); \
1913 else \
1914 RS480_WRITE_MCIND(addr, val); \
1915} while (0)
1916
1917#define CP_PACKET0( reg, n ) \
1918 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1919#define CP_PACKET0_TABLE( reg, n ) \
1920 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1921#define CP_PACKET1( reg0, reg1 ) \
1922 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1923#define CP_PACKET2() \
1924 (RADEON_CP_PACKET2)
1925#define CP_PACKET3( pkt, n ) \
1926 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1927
1928
1929
1930
1931
1932#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1933 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1934 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1935 RADEON_WAIT_HOST_IDLECLEAN) ); \
1936} while (0)
1937
1938#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1939 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1940 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1941 RADEON_WAIT_HOST_IDLECLEAN) ); \
1942} while (0)
1943
1944#define RADEON_WAIT_UNTIL_IDLE() do { \
1945 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1946 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1947 RADEON_WAIT_3D_IDLECLEAN | \
1948 RADEON_WAIT_HOST_IDLECLEAN) ); \
1949} while (0)
1950
1951#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1952 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1953 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1954} while (0)
1955
1956#define RADEON_FLUSH_CACHE() do { \
1957 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1958 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1959 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1960 } else { \
1961 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1962 OUT_RING(R300_RB3D_DC_FLUSH); \
1963 } \
1964} while (0)
1965
1966#define RADEON_PURGE_CACHE() do { \
1967 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1968 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1969 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1970 } else { \
1971 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1972 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1973 } \
1974} while (0)
1975
1976#define RADEON_FLUSH_ZCACHE() do { \
1977 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1978 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1979 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1980 } else { \
1981 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1982 OUT_RING(R300_ZC_FLUSH); \
1983 } \
1984} while (0)
1985
1986#define RADEON_PURGE_ZCACHE() do { \
1987 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1988 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1989 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1990 } else { \
1991 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1992 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1993 } \
1994} while (0)
1995
1996
1997
1998
1999
2000
2001
2002#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
2003do { \
2004 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
2005 u32 head = GET_RING_HEAD( dev_priv ); \
2006 if (head == dev_priv->ring.tail) \
2007 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
2008 } \
2009} while (0)
2010
2011#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
2012do { \
2013 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
2014 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
2015 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
2016 int __ret; \
2017 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2018 __ret = r600_do_cp_idle(dev_priv); \
2019 else \
2020 __ret = radeon_do_cp_idle(dev_priv); \
2021 if ( __ret ) return __ret; \
2022 sarea_priv->last_dispatch = 0; \
2023 radeon_freelist_reset( dev ); \
2024 } \
2025} while (0)
2026
2027#define RADEON_DISPATCH_AGE( age ) do { \
2028 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
2029 OUT_RING( age ); \
2030} while (0)
2031
2032#define RADEON_FRAME_AGE( age ) do { \
2033 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
2034 OUT_RING( age ); \
2035} while (0)
2036
2037#define RADEON_CLEAR_AGE( age ) do { \
2038 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
2039 OUT_RING( age ); \
2040} while (0)
2041
2042#define R600_DISPATCH_AGE(age) do { \
2043 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2044 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2045 OUT_RING(age); \
2046} while (0)
2047
2048#define R600_FRAME_AGE(age) do { \
2049 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2050 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2051 OUT_RING(age); \
2052} while (0)
2053
2054#define R600_CLEAR_AGE(age) do { \
2055 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2056 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2057 OUT_RING(age); \
2058} while (0)
2059
2060
2061
2062
2063
2064#define RADEON_VERBOSE 0
2065
2066#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
2067
2068#define RADEON_RING_ALIGN 16
2069
2070#define BEGIN_RING( n ) do { \
2071 if ( RADEON_VERBOSE ) { \
2072 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
2073 } \
2074 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \
2075 _align_nr += n; \
2076 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
2077 COMMIT_RING(); \
2078 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
2079 } \
2080 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
2081 ring = dev_priv->ring.start; \
2082 write = dev_priv->ring.tail; \
2083 mask = dev_priv->ring.tail_mask; \
2084} while (0)
2085
2086#define ADVANCE_RING() do { \
2087 if ( RADEON_VERBOSE ) { \
2088 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
2089 write, dev_priv->ring.tail ); \
2090 } \
2091 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
2092 DRM_ERROR( \
2093 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
2094 ((dev_priv->ring.tail + _nr) & mask), \
2095 write, __LINE__); \
2096 } else \
2097 dev_priv->ring.tail = write; \
2098} while (0)
2099
2100extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2101
2102#define COMMIT_RING() do { \
2103 radeon_commit_ring(dev_priv); \
2104 } while(0)
2105
2106#define OUT_RING( x ) do { \
2107 if ( RADEON_VERBOSE ) { \
2108 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
2109 (unsigned int)(x), write ); \
2110 } \
2111 ring[write++] = (x); \
2112 write &= mask; \
2113} while (0)
2114
2115#define OUT_RING_REG( reg, val ) do { \
2116 OUT_RING( CP_PACKET0( reg, 0 ) ); \
2117 OUT_RING( val ); \
2118} while (0)
2119
2120#define OUT_RING_TABLE( tab, sz ) do { \
2121 int _size = (sz); \
2122 int *_tab = (int *)(tab); \
2123 \
2124 if (write + _size > mask) { \
2125 int _i = (mask+1) - write; \
2126 _size -= _i; \
2127 while (_i > 0 ) { \
2128 *(int *)(ring + write) = *_tab++; \
2129 write++; \
2130 _i--; \
2131 } \
2132 write = 0; \
2133 _tab += _i; \
2134 } \
2135 while (_size > 0) { \
2136 *(ring + write) = *_tab++; \
2137 write++; \
2138 _size--; \
2139 } \
2140 write &= mask; \
2141} while (0)
2142
2143
2144
2145
2146#define OUT_RING_DRM_BUFFER(buf, sz) do { \
2147 int _size = (sz) * 4; \
2148 struct drm_buffer *_buf = (buf); \
2149 int _part_size; \
2150 while (_size > 0) { \
2151 _part_size = _size; \
2152 \
2153 if (write + _part_size/4 > mask) \
2154 _part_size = ((mask + 1) - write)*4; \
2155 \
2156 if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \
2157 _part_size = PAGE_SIZE - drm_buffer_index(_buf);\
2158 \
2159 \
2160 \
2161 memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \
2162 [drm_buffer_index(_buf)], _part_size); \
2163 \
2164 _size -= _part_size; \
2165 write = (write + _part_size/4) & mask; \
2166 drm_buffer_advance(_buf, _part_size); \
2167 } \
2168} while (0)
2169
2170
2171#endif
2172
